CN103579087B - A kind of manufacture method of three-dimensional integrated circuit structure and three-dimensional integrated circuit structure - Google Patents
A kind of manufacture method of three-dimensional integrated circuit structure and three-dimensional integrated circuit structure Download PDFInfo
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- CN103579087B CN103579087B CN201210261929.0A CN201210261929A CN103579087B CN 103579087 B CN103579087 B CN 103579087B CN 201210261929 A CN201210261929 A CN 201210261929A CN 103579087 B CN103579087 B CN 103579087B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
The invention discloses a kind of manufacture method and three-dimensional integrated circuit structure of three-dimensional integrated circuit structure.The method comprises: provide substrate; Substrate is formed the first chip dielectric layer, in the first chip dielectric layer, forms the first chip groove, in the first chip groove, embed the first chip; First chip dielectric layer forms the first via dielectric layer, in the first via dielectric layer, forms the first conductive through hole and the first conductive trench; First via dielectric layer is formed the second chip dielectric layer, in the second chip dielectric layer, forms the second chip groove, in the second chip groove, embed the second chip; Second chip dielectric layer forms the second via dielectric layer, in the second via dielectric layer, form the second conductive through hole, in the second chip dielectric layer and the second via dielectric layer, form the 3rd conductive through hole, in the second via dielectric layer, form the second conductive trench.This manufacture method can reduce the cost of manufacture of three-dimensional integrated circuit structure.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of manufacture method and three-dimensional integrated circuit structure of three-dimensional integrated circuit structure.
Background technology
Along with the fast development of semiconductor industry, the integration density of integrated circuit improves constantly.The raising of this integration density mainly comes from the reduction of characteristic size, and it allows more device to be integrated in a given region.
The raising of these integration densities is substantially on the basis of two-dimensional integrated circuit.Although the improvement of photoetching technique has promoted the significant improvement of two-dimensional integrated circuit, still there is the restriction to integration density.On the one hand be limited in ripe photoetching technique under characteristic size be difficult to breakthrough reducing; Being limited on the other hand needs more complicated design on a single die by integrated for more device.
Improving in the research of integration density further, develop three dimensional integrated circuits.Fig. 1 is the cutaway view of existing three dimensional integrated circuits.As shown in Figure 1, chip 120,130,140 and 150 overlays in substrate 110 successively, is arranged in middle chip 120-140 and is formed with through-silicon-via (ThroughSiliconVias, TSV) 160.By projection (Bump), through-silicon-via 160 is linked together between adjacent chip and between the chip 120 of the bottom and substrate 110, to make to form electrical connection between stacking multiple chip 110-150.
Each chip in stacked structure is formed separately on a semiconductor substrate.Compared with the thickness and chip itself forming the Semiconductor substrate of these chips, thickness is comparatively large, and the size of through-silicon-via 160 is very little, is approximately tens to hundreds of nanometer.If want to utilize photoetching technique to form through hole in the semiconductor substrate, and fill silicon to form through-silicon-via 160, then need to carry out thinning to the Semiconductor substrate of each chip, and then form through-silicon-via 160 through the technique such as over etching, filling.Therefore, the cost making this three-dimensional integrated circuit structure is higher, is unfavorable for volume production.
Therefore, a kind of manufacture method and three-dimensional integrated circuit structure of three-dimensional integrated circuit structure is badly in need of at present, to solve the problem.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of manufacture method of three-dimensional integrated circuit structure, comprising: steps A, substrate is provided; Step B, forms the first chip dielectric layer on the substrate, in described first chip dielectric layer, form the first chip groove, and in described first chip groove, embed the first chip, the upper surface of described first chip has the first weld pad; Step C, described first chip dielectric layer forms the first via dielectric layer, the first conductive through hole and the first conductive trench is formed in described first via dielectric layer, wherein said first conductive through hole is electrically connected with described first weld pad, and the top of described first conductive through hole connects by the upper surface that described first conductive trench is positioned at described first via dielectric layer; Step D, described first via dielectric layer is formed the second chip dielectric layer, in described second chip dielectric layer, form the second chip groove, and in described second chip groove, embed the second chip, the upper surface of described second chip has the second weld pad; And step e, described second chip dielectric layer forms the second via dielectric layer, in described second via dielectric layer, form the second conductive through hole, in described second chip dielectric layer and described second via dielectric layer, form the 3rd conductive through hole, the second conductive trench is formed in described second via dielectric layer, wherein said second conductive through hole is electrically connected with described second weld pad, described 3rd conductive through hole is electrically connected with described first conductive trench, and described second conductive trench is connected with the top of described second conductive through hole and described 3rd conductive through hole.
Preferably, pad oxide skin(coating) is formed with between described first chip dielectric layer and described substrate.
Preferably, etching stop layer is formed between described first via dielectric layer and described second chip dielectric layer.
Preferably, described etching stop layer is nitrogenous silicon carbide layer.
Preferably, described first conductive trench comprises peripheral conductive trench, and the upper surface that described peripheral conductive trench is embedded in described first via dielectric layer does not correspond in the region of described first chip.
Preferably, described first chip is formed with the first cover layer covering described first weld pad, described second chip is formed with the second cover layer covering described second weld pad.
Preferably, described first cover layer and described second cover layer are nitrogenous silicon carbide layer or oxide skin(coating).
Preferably, described first chip dielectric layer, described first via dielectric layer, described second chip dielectric layer and/or described second via dielectric layer are low k dielectric.
Preferably, described manufacture method also comprises repetition above-mentioned steps D and E, to form multiple stacking chip on the substrate.
Preferably, described substrate is silicon wafer.
Preferably, the thickness of described first chip dielectric layer is greater than the thickness of described first chip, and the thickness of described second chip dielectric layer is greater than the thickness of described second chip.
Preferably, described first via dielectric layer, described second via dielectric layer, described first chip dielectric layer are identical with the material of described second chip dielectric layer.
The present invention also provides a kind of three-dimensional integrated circuit structure, and described three-dimensional integrated circuit structure is that any one method is made as mentioned above.
The manufacture method of three-dimensional integrated circuit structure provided by the invention without the need to carrying out reduction process and the through-silicon-via etching technics of Semiconductor substrate, because this reducing the cost of manufacture of three-dimensional integrated circuit structure.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the cutaway view of existing three dimensional integrated circuits;
Fig. 2 is the flow chart of the making three-dimensional integrated circuit structure according to one embodiment of the present invention;
Fig. 3 A-3J is for making the cutaway view of the device that each step obtains in three-dimensional integrated circuit structure process according to one embodiment of the present invention.
Embodiment
Next, by reference to the accompanying drawings the present invention will more intactly be described, shown in the drawings of embodiments of the invention.But the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.
The invention provides a kind of manufacture method of three-dimensional integrated circuit structure.Fig. 2 is the flow chart of the making three-dimensional integrated circuit structure according to one embodiment of the present invention, and Fig. 3 A-3J is for making the cutaway view of the device that each step obtains in three-dimensional integrated circuit structure process according to one embodiment of the present invention.Below in conjunction with Fig. 2 and Fig. 3 A-3J, method of the present invention is described in detail.
Perform step 201, substrate is provided.
As shown in Figure 3A, substrate 301 is provided.Substrate 301 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Preferably, described substrate 301 is silicon base.
Perform step 202, substrate is formed the first chip dielectric layer, forms the first chip groove in the first chip dielectric layer, in the first chip groove, embed the first chip, the upper surface of the first chip has the first weld pad.
Continue see Fig. 3 A, the material that substrate 301 is formed the first chip dielectric layer 303, first chip dielectric layer 303 can be oxide, nitride etc.Preferably, be also formed and pad oxide skin(coating) 302 between substrate 301 and the first chip dielectric layer 303, this pad oxide skin(coating) 302 can as the transition zone of substrate 301 and the first chip dielectric layer 303.In order to reduce the parasitic capacitance of device, preferably, the material of the first chip dielectric layer 303 can be low k dielectric.
As shown in Figure 3 B, in the first chip dielectric layer 303, the first chip groove 304 is formed.Exemplarily, the figuratum photoresist layer of tool can be formed on the first chip dielectric layer 303, then etch formation first chip groove 304.
As shown in Figure 3 C, the first chip 305 is embedded in the first chip groove 304.Will be contained in the first chip groove 304 in the first chip dielectric layer 303 due to the first chip 305, therefore, the thickness of the first chip dielectric layer 303 can equal the thickness of the first chip 305 substantially.The thickness of the first chip 305 can control be less than 50 microns, and depends on new technology and new technology, and the first chip dielectric layer 303 should be allowed to have certain surplus (such as 900 dusts), can hold the error embedding and cause in engineering.The upper surface of the first chip 305 is formed with the first weld pad 306, first chip 305 and is electrically connected with external circuit by this first weld pad 306.Preferably, the first chip 305 is formed with the first cover layer 307 of covering first weld pad 306, this first cover layer 307 can be used as the etching stop layer of subsequent technique.Preferably, the first cover layer 307 is nitrogenous silicon carbide layer or oxide skin(coating).
Perform step 203, first chip dielectric layer forms the first via dielectric layer, in the first via dielectric layer, form the first conductive through hole and the first conductive trench, wherein the first conductive through hole is electrically connected with the first weld pad, and the first conductive trench is positioned at the upper surface of the first via dielectric layer.
As shown in Figure 3 D, the first chip dielectric layer 303 forms the first via dielectric layer 308.In order to reduce the parasitic capacitance of device, preferably, the material of the first via dielectric layer 308 can be low k dielectric.
As shown in FIGURE 3 E, in the first via dielectric layer 308, the first conductive through hole 309a and the first conductive trench 309b is formed.First conductive through hole 309a is electrically connected with the first weld pad 306, and the first conductive trench 309b is positioned at the upper surface of the first via dielectric layer 308.The top of the first conductive through hole 309a connects at the upper surface of the first via dielectric layer 308 by the first conductive trench 309b, and form interconnection structure, in order to this interconnection structure is electrically connected with external circuit, first conductive trench 309b also comprises peripheral conductive trench, and the upper surface that this peripheral conductive trench is embedded in the first via dielectric layer 308 does not correspond in the region of the first chip 305.The projection of peripheral conductive trench straight down in substrate 301 is not overlapping with the first projection of chip 305 straight down in substrate 301, with the syndeton facilitating subsequent technique to form connection first conductive trench 309b.
First conductive through hole 309a and the first conductive trench 309b can adopt method conventional in this area to be formed.Exemplarily, formed the through hole be communicated with the first weld pad 306 in the position of corresponding first weld pad 306 by etching technics; Then as required can the top of through hole and be not formed through hole position formed groove, to form interconnection structure; Finally in through hole and groove, fill metal (such as copper or tungsten etc.), to form the first conductive through hole 309a and the first conductive trench 309b.
Perform step 204, the first via dielectric layer is formed the second chip dielectric layer, forms the second chip groove in the second chip dielectric layer, in the second chip groove, embed the second chip, the upper surface of the second chip has the second weld pad.
Preferably, before formation second chip dielectric layer, can form etching stop layer 310 (as illustrated in Figure 3 F) in the first via dielectric layer 308, it can be used as the etching stop layer that etching forms connection first conductive trench 309b.Preferably, etching stop layer 310 can be nitrogenous silicon carbide layer.
This step and step 203 are substantially identical, simply introduce just by reference to the accompanying drawings below to forming step 204.As shown in Figure 3 G, first via dielectric layer 308 is formed the second chip dielectric layer 311 (be understandable that, when there is etching stop layer 310, second chip dielectric layer 311 is formed on this etching stop layer 310), the material of the second chip dielectric layer 311 can be oxide, nitride etc.In order to reduce the parasitic capacitance of device, preferably, the material of the second chip dielectric layer 311 can be low k dielectric.Adopt photoetching technique to form the second chip groove in the second chip dielectric layer 311, then the second chip 312 is embedded in this second chip groove.Similarly, the thickness of the second chip 312 can control be less than 50 microns, and depend on new technology and new technology, the second chip dielectric layer 311 should be allowed to have certain surplus (such as 900 dusts), so that the error embedding and cause in engineering can be held.The upper surface of the second chip 312 is formed with the second weld pad 313, second chip 312 and is electrically connected with external circuit by this second weld pad 313.Preferably, the second chip 312 is formed with the second cover layer 314 of covering second weld pad 313, this second cover layer 314 can be used as the etching stop layer of subsequent technique.Preferably, the second cover layer 314 is nitrogenous silicon carbide layer or oxide skin(coating).
Perform step 205, second chip dielectric layer forms the second via dielectric layer, in the second via dielectric layer, form the second conductive through hole, in the second chip dielectric layer and the second via dielectric layer, form the 3rd conductive through hole, the second conductive trench is formed in the second via dielectric layer, wherein the second conductive through hole is electrically connected with the second weld pad, and the 3rd conductive through hole is electrically connected with the first conductive trench.
As shown in figure 3h, the second chip dielectric layer 311 forms the second via dielectric layer 315.In order to reduce the parasitic capacitance of device, preferably, the material of the second via dielectric layer 315 can be low k dielectric.
As shown in fig. 31, in the second via dielectric layer 315, the second conductive through hole 316a and the 3rd conductive through hole 316b is formed.Second conductive through hole 316a is formed in the second via dielectric layer 315, is electrically connected with the second weld pad 313, and the 3rd conductive through hole 316b is formed in the second chip dielectric layer 311 and the second via dielectric layer 315, is electrically connected with the first conductive trench 309b.Second conductive through hole 316a and the 3rd conductive through hole 316b can adopt method conventional in this area to be formed.Exemplarily, form with the position of the first conductive trench 309b the through hole be communicated with the first conductive trench 309b with the second weld pad 313 respectively at corresponding second weld pad 313 by etching technics, the through hole wherein corresponding to the second weld pad 313 place is only formed in the second via dielectric layer 315, and the through hole corresponding to the first conductive trench 309b place is formed in the second chip dielectric layer 311 and the second via dielectric layer 315; Then as required can the top of through hole and be not formed through hole position formed groove, to form interconnection structure; Finally in through hole and groove, fill metal (such as copper or tungsten etc.), to form the second conductive through hole 316a and the 3rd conductive through hole 316b.Preferably, the first via dielectric layer 308, second via dielectric layer 315, first chip dielectric layer 303 is identical with the material of the second chip dielectric layer 311.
Certainly, method provided by the invention is not limited to only integrated two chips, can also form the integrated circuit more than 2 chips.In the case, this manufacture method also comprises repetition above-mentioned steps 204 and step 205, to form multiple stacking chip in substrate 301.
Preferably, at chip be formed with etching stop layer (etching stop layer 317 with reference to shown in Fig. 3 J) between through-hole structure layer and the second via layer and between adjacent chip and through-hole structure layer.
The present invention also provides a kind of three-dimensional integrated circuit structure, and this three-dimensional integrated circuit structure is made up of method as above.
The manufacture method of three-dimensional integrated circuit structure provided by the invention without the need to carrying out reduction process and the through-silicon-via etching technics of Semiconductor substrate, because this reducing the cost of manufacture of three-dimensional integrated circuit structure.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a manufacture method for three-dimensional integrated circuit structure, is characterized in that, comprising:
Steps A, provides substrate;
Step B, forms the first chip dielectric layer on the substrate, in described first chip dielectric layer, form the first chip groove, and in described first chip groove, embed the first chip, the upper surface of described first chip has the first weld pad;
Step C, described first chip dielectric layer forms the first via dielectric layer, the first conductive through hole and the first conductive trench is formed in described first via dielectric layer, wherein said first conductive through hole is electrically connected with described first weld pad, and the top of described first conductive through hole connects by the upper surface that described first conductive trench is positioned at described first via dielectric layer;
Step D, described first via dielectric layer is formed the second chip dielectric layer, in described second chip dielectric layer, form the second chip groove, and in described second chip groove, embed the second chip, the upper surface of described second chip has the second weld pad; And
Step e, described second chip dielectric layer forms the second via dielectric layer, in described second via dielectric layer, form the second conductive through hole, in described second chip dielectric layer and described second via dielectric layer, form the 3rd conductive through hole, the second conductive trench is formed in described second via dielectric layer, wherein said second conductive through hole is electrically connected with described second weld pad, described 3rd conductive through hole is electrically connected with described first conductive trench, and described second conductive trench is positioned on the top of described second conductive through hole and described 3rd conductive through hole.
2. manufacture method as claimed in claim 1, is characterized in that, be formed with pad oxide skin(coating) between described first chip dielectric layer and described substrate.
3. manufacture method as claimed in claim 1, is characterized in that, form etching stop layer between described first via dielectric layer and described second chip dielectric layer.
4. manufacture method as claimed in claim 3, it is characterized in that, described etching stop layer is nitrogenous silicon carbide layer.
5. manufacture method as claimed in claim 1, it is characterized in that, described first conductive trench comprises peripheral conductive trench, and the upper surface that described peripheral conductive trench is embedded in described first via dielectric layer does not correspond in the region of described first chip.
6. manufacture method as claimed in claim 1, is characterized in that, described first chip is formed with the first cover layer covering described first weld pad, described second chip is formed with the second cover layer covering described second weld pad.
7. manufacture method as claimed in claim 6, it is characterized in that, described first cover layer and described second cover layer are nitrogenous silicon carbide layer or oxide skin(coating).
8. manufacture method as claimed in claim 1, it is characterized in that, described first chip dielectric layer, described first via dielectric layer, described second chip dielectric layer and/or described second via dielectric layer are low k dielectric.
9. manufacture method as claimed in claim 1, it is characterized in that, described manufacture method also comprises repetition above-mentioned steps D and E, to form multiple stacking chip on the substrate.
10. manufacture method as claimed in claim 1, it is characterized in that, described substrate is silicon wafer.
11. manufacture methods as claimed in claim 1, is characterized in that, the thickness of described first chip dielectric layer is greater than the thickness of described first chip, and the thickness of described second chip dielectric layer is greater than the thickness of described second chip.
12. manufacture methods as claimed in claim 1, is characterized in that, described first via dielectric layer, described second via dielectric layer, described first chip dielectric layer are identical with the material of described second chip dielectric layer.
13. 1 kinds of three-dimensional integrated circuit structures, is characterized in that, described three-dimensional integrated circuit structure is that the method according to any one of claim 1-12 is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210261929.0A CN103579087B (en) | 2012-07-26 | 2012-07-26 | A kind of manufacture method of three-dimensional integrated circuit structure and three-dimensional integrated circuit structure |
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| CN1499590A (en) * | 2002-11-05 | 2004-05-26 | �¹������ҵ��ʽ���� | Semiconductor device and its mfg. method |
| CN101552247A (en) * | 2008-04-02 | 2009-10-07 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| CN102044512A (en) * | 2009-10-09 | 2011-05-04 | 台湾积体电路制造股份有限公司 | Integrated circuit and multi-chip module stacked in three dimensions |
| CN102376737A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Integrated circuit embedded into MRAM(Magnetic Random Access Memory) and preparation method of integrated circuit |
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| US8399350B2 (en) * | 2010-02-05 | 2013-03-19 | International Business Machines Corporation | Formation of air gap with protection of metal lines |
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| CN1499590A (en) * | 2002-11-05 | 2004-05-26 | �¹������ҵ��ʽ���� | Semiconductor device and its mfg. method |
| CN101552247A (en) * | 2008-04-02 | 2009-10-07 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| CN102044512A (en) * | 2009-10-09 | 2011-05-04 | 台湾积体电路制造股份有限公司 | Integrated circuit and multi-chip module stacked in three dimensions |
| CN102376737A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Integrated circuit embedded into MRAM(Magnetic Random Access Memory) and preparation method of integrated circuit |
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