CN103579087A - Manufacturing method of three-dimensional integrated circuit structure and three-dimensional integrated circuit structure - Google Patents
Manufacturing method of three-dimensional integrated circuit structure and three-dimensional integrated circuit structure Download PDFInfo
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- CN103579087A CN103579087A CN201210261929.0A CN201210261929A CN103579087A CN 103579087 A CN103579087 A CN 103579087A CN 201210261929 A CN201210261929 A CN 201210261929A CN 103579087 A CN103579087 A CN 103579087A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
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Abstract
The invention discloses a manufacturing method of a three-dimensional integrated circuit structure and the three-dimensional integrated circuit structure. The manufacturing method of the three-dimensional integrated circuit structure comprises the steps that a substrate is provided; a first chip dielectric layer is formed on the substrate, a first chip groove is formed in the first chip dielectric layer, and a first chip is embedded in the first chip groove; a first through hole dielectric layer is formed on the first chip dielectric layer, and a first conductive through hole and a first conductive groove are formed in the first through hole dielectric layer; a second chip dielectric layer is formed on the first through hole dielectric layer, a second chip groove is formed in the second chip dielectric layer, and a second chip is embedded in the second chip groove; a second through hole dielectric layer is formed on the second chip dielectric layer, a second conductive through hole is formed in the second through hole dielectric layer, third conductive through holes are formed in the second chip dielectric layer and in the second through hole dielectric layer, and a second conductive groove is formed in the second through hole dielectric layer. According to the manufacturing method of the three-dimensional integrated circuit structure, the manufacturing cost of the three-dimensional integrated circuit structure can be reduced.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of manufacture method and three-dimensional integrated circuit structure of three-dimensional integrated circuit structure.
Background technology
Along with the fast development of semiconductor industry, the integration density of integrated circuit improves constantly.The raising of this integration density mainly comes from reducing of characteristic size, and it allows more device to be integrated in a given region.
The raising of these integration densities is substantially on the basis of two-dimentional integrated circuit.Although the improvement of photoetching technique has promoted the significant improvement of two-dimentional integrated circuit, still there is the restriction to integration density.The characteristic size under ripe photoetching technique that is limited in is on the one hand difficult to breakthrough dwindling; Being limited in is on the other hand integrated in more device on a chip and needs more complicated design.
Further improving in the research of integration density, developed three dimensional integrated circuits.Fig. 1 is the cutaway view of existing three dimensional integrated circuits.As shown in Figure 1, chip 120,130,140 and 150 overlays in substrate 110 successively, and the chip 120-140 in the middle of being arranged in is formed with through-silicon-via (Through Silicon Vias, TSV) 160.Between adjacent chip and between the chip 120 of the bottom and substrate 110, by projection (Bump), through-silicon-via 160 is linked together, so that form and be electrically connected between stacking a plurality of chip 110-150.
Each chip in stacked structure forms separately in Semiconductor substrate.It is larger that the thickness and chip that forms the Semiconductor substrate of these chips itself is compared thickness, and the size of through-silicon-via 160 is very little, is approximately tens to hundreds of nanometer.If want to utilize photoetching technique to form through hole in Semiconductor substrate, and fill silicon to form through-silicon-via 160, need the Semiconductor substrate of each chip to carry out attenuate, and then form through-silicon-via 160 through techniques such as over etching, fillings.Therefore, the cost of making this three-dimensional integrated circuit structure is higher, is unfavorable for volume production.
Therefore, be badly in need of at present a kind of manufacture method and three-dimensional integrated circuit structure of three-dimensional integrated circuit structure, to address the above problem.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of manufacture method of three-dimensional integrated circuit structure, comprising: steps A, provides substrate; Step B forms the first chip dielectric layer in described substrate, in described the first chip dielectric layer, forms the first chip groove, in described the first chip groove, embeds the first chip, and the upper surface of described the first chip has the first weld pad; Step C, on described the first chip dielectric layer, form the first via dielectric layer, in described the first via dielectric layer, form the first conductive through hole and the first conductive trench, wherein said the first conductive through hole is electrically connected to described the first weld pad, and described the first conductive trench is positioned at the upper surface of described the first via dielectric layer; Step D forms the second chip dielectric layer in described the first via dielectric layer, in described the second chip dielectric layer, forms the second chip groove, in described the second chip groove, embeds the second chip, and the upper surface of described the second chip has the second weld pad; And step e, on described the second chip dielectric layer, form the second via dielectric layer, in described the second via dielectric layer, form the second conductive through hole, in described the second chip dielectric layer and described the second via dielectric layer, form the 3rd conductive through hole, in described the second via dielectric layer, form the second conductive trench, wherein said the second conductive through hole is electrically connected to described the second weld pad, and described the 3rd conductive through hole is electrically connected to described the first conductive trench.
Preferably, between described the first chip dielectric layer and described substrate, be formed with pad oxide skin(coating).
Preferably, between described the first via dielectric layer and described the second chip dielectric layer, form etching stop layer.
Preferably, described etching stop layer is nitrogenous silicon carbide layer.
Preferably, described the first conductive trench comprises peripheral conductive trench, and the upper surface that described peripheral conductive trench is embedded in described the first via dielectric layer does not correspond in the region of described the first chip.
Preferably, on described the first chip, be formed with the first cover layer that covers described the first weld pad, on described the second chip, be formed with the second cover layer that covers described the second weld pad.
Preferably, described the first cover layer and described the second cover layer are nitrogenous silicon carbide layer or oxide skin(coating).
Preferably, described the first chip dielectric layer, described the first via dielectric layer, described the second chip dielectric layer and/or described the second via dielectric layer are low k dielectric.
Preferably, described manufacture method also comprises repetition above-mentioned steps D and E, to form a plurality of stacking chips in described substrate.
Preferably, described substrate is silicon wafer.
Preferably, the thickness of described the first chip dielectric layer is greater than the thickness of described the first chip, and the thickness of described the second chip dielectric layer is greater than the thickness of described the second chip.
Preferably, described the first via dielectric layer, described the second via dielectric layer, described the first chip dielectric layer are identical with the material of described the second chip dielectric layer.
The present invention also provides a kind of three-dimensional integrated circuit structure, and described three-dimensional integrated circuit structure as mentioned above any method is made.
The manufacture method of three-dimensional integrated circuit structure provided by the invention, without the reduction process and the through-silicon-via etching technics that carry out Semiconductor substrate, has therefore reduced the cost of manufacture of three-dimensional integrated circuit structure.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the cutaway view of existing three dimensional integrated circuits;
Fig. 2 is according to the flow chart of the making three-dimensional integrated circuit structure of one embodiment of the present invention;
Fig. 3 A-3J is for making the cutaway view of the device that in three-dimensional integrated circuit structure process, each step obtains according to one embodiment of the present invention.
Embodiment
Next, in connection with accompanying drawing, the present invention is more intactly described, shown in the drawings of embodiments of the invention.But the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to know that size and the relative size in ，Ceng He district may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or can there is element or layer between two parties.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, there is not element or layer between two parties.
The invention provides a kind of manufacture method of three-dimensional integrated circuit structure.Fig. 2 is according to the flow chart of the making three-dimensional integrated circuit structure of one embodiment of the present invention, and Fig. 3 A-3J is for making the cutaway view of the device that in three-dimensional integrated circuit structure process, each step obtains according to one embodiment of the present invention.Below in conjunction with Fig. 2 and Fig. 3 A-3J, method of the present invention is described in detail.
As shown in Figure 3A, provide substrate 301.Substrate 301 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Preferably, described substrate 301 is silicon base.
Continuation is referring to Fig. 3 A, and the material that forms the first chip dielectric layer 303, the first chip dielectric layers 303 in substrate 301 can be oxide, nitride etc.Preferably, be also formed with pad oxide skin(coating) 302 between substrate 301 and the first chip dielectric layer 303, this pad oxide skin(coating) 302 can be used as the transition zone of substrate 301 and the first chip dielectric layer 303.In order to reduce the parasitic capacitance of device, preferably, the material of the first chip dielectric layer 303 can be low k dielectric.
As shown in Figure 3 B, in the first chip dielectric layer 303, form the first chip groove 304.As example, can on the first chip dielectric layer 303, form the figuratum photoresist layer of tool, then etching forms the first chip groove 304.
As shown in Figure 3 C, the first chip 305 is embedded in the first chip groove 304.Because the first chip 305 will be contained in the first chip groove 304 in the first chip dielectric layer 303, therefore, the thickness of the first chip dielectric layer 303 can equal the thickness of the first chip 305 substantially.The thickness of the first chip 305 can be controlled at and be less than 50 microns, and depends on new technology and new technology, should allow the first chip dielectric layer 303 to have certain surplus (for example 900 dusts), holding, embeds the error causing in engineering.The upper surface of the first chip 305 is formed with the first weld pad 306, the first chips 305 and is electrically connected to external circuit by this first weld pad 306.Preferably, be formed with the first cover layer 307 that covers the first weld pad 306 on the first chip 305, this first cover layer 307 can be as the etching stop layer of subsequent technique.Preferably, the first cover layer 307 is nitrogenous silicon carbide layer or oxide skin(coating).
As shown in Figure 3 D, on the first chip dielectric layer 303, form the first via dielectric layer 308.In order to reduce the parasitic capacitance of device, preferably, the material of the first via dielectric layer 308 can be low k dielectric.
As shown in Fig. 3 E, in the first via dielectric layer 308, form the first conductive through hole 309a and the first conductive trench 309b.The first conductive through hole 309a is electrically connected to the first weld pad 306, and the first conductive trench 309b is positioned at the upper surface of the first via dielectric layer 308.The first conductive trench 309b connects the top of the first conductive through hole 309a at the upper surface of the first via dielectric layer 308, and form interconnection structure, for this interconnection structure is electrically connected to external circuit, the first conductive trench 309b also comprises peripheral conductive trench, and the upper surface that this periphery conductive trench is embedded in the first via dielectric layer 308 does not correspond in the region of the first chip 305.The projection cloth in substrate 301 is overlapping straight down for the peripheral conductive trench projection in substrate 301 straight down and the first chip 305, to facilitate subsequent technique to form the syndeton that connects the first conductive trench 309b.
The first conductive through hole 309a and the first conductive trench 309b can adopt method conventional in this area to form.As example, by etching technics, in the position of corresponding the first weld pad 306, form the through hole being communicated with the first weld pad 306; The position of then as required can be at the top of through hole and not being formed with through hole forms groove, to form interconnection structure; Finally in through hole and groove, fill metal (such as copper or tungsten etc.), to form the first conductive through hole 309a and the first conductive trench 309b.
Preferably, before forming the second chip dielectric layer, can in the first via dielectric layer 308, form etching stop layer 310(as shown in Fig. 3 F), it can form the etching stop layer that is communicated with the first conductive trench 309b as etching.Preferably, etching stop layer 310 can be nitrogenous silicon carbide layer.
This step and step 203 are basic identical, simply introduce just by reference to the accompanying drawings below to forming step 204.As shown in Fig. 3 G, in the first via dielectric layer 308, forming the second chip dielectric layer 311(is understandable that, when there is etching stop layer 310, the second chip dielectric layer 311 is formed on this etching stop layer 310), the material of the second chip dielectric layer 311 can be oxide, nitride etc.In order to reduce the parasitic capacitance of device, preferably, the material of the second chip dielectric layer 311 can be low k dielectric.Adopt photoetching technique in the second chip dielectric layer 311, to form the second chip groove, then the second chip 312 is embedded in this second chip groove.Similarly, the thickness of the second chip 312 can be controlled at and be less than 50 microns, and depends on new technology and new technology, should allow the second chip dielectric layer 311 to have certain surplus (for example 900 dusts), holding, embeds the error causing in engineering.The upper surface of the second chip 312 is formed with the second weld pad 313, the second chips 312 and is electrically connected to external circuit by this second weld pad 313.Preferably, be formed with the second cover layer 314 that covers the second weld pad 313 on the second chip 312, this second cover layer 314 can be as the etching stop layer of subsequent technique.Preferably, the second cover layer 314 is nitrogenous silicon carbide layer or oxide skin(coating).
As shown in Fig. 3 H, on the second chip dielectric layer 311, form the second via dielectric layer 315.In order to reduce the parasitic capacitance of device, preferably, the material of the second via dielectric layer 315 can be low k dielectric.
As shown in Fig. 3 I, in the second via dielectric layer 315, form the second conductive through hole 316a and the 3rd conductive through hole 316b.The second conductive through hole 316a is formed in the second via dielectric layer 315, is electrically connected to the second weld pad 313, and the 3rd conductive through hole 316b is formed in the second chip dielectric layer 311 and the second via dielectric layer 315, is electrically connected to the first conductive trench 309b.The second conductive through hole 316a and the 3rd conductive through hole 316b can adopt method conventional in this area to form.As example, by etching technics, in the position of corresponding the second weld pad 313 and the first conductive trench 309b, form the through hole being communicated with the second weld pad 313 and the first conductive trench 309b respectively, wherein the through hole corresponding to the second weld pad 313 places is only formed in the second via dielectric layer 315, corresponding to the through hole at the first conductive trench 309b place, is formed in the second chip dielectric layer 311 and the second via dielectric layer 315; The position of then as required can be at the top of through hole and not being formed with through hole forms groove, to form interconnection structure; Finally in through hole and groove, fill metal (such as copper or tungsten etc.), to form the second conductive through hole 316a and the 3rd conductive through hole 316b.Preferably, the first via dielectric layer 308, the second via dielectric layer 315, the first chip dielectric layer 303 are identical with the material of the second chip dielectric layer 311.
Certainly, method provided by the invention is not limited to only integrated two chips, can also form the integrated circuit more than 2 chips.In the case, this manufacture method also comprises repetition above-mentioned steps 204 and step 205, to form a plurality of stacking chips in substrate 301.
Preferably, between chip and through-hole structure layer and the second via layer and between adjacent chip and through-hole structure layer, be formed with etching stop layer (with reference to the etching stop layer 317 shown in Fig. 3 J).
The present invention also provides a kind of three-dimensional integrated circuit structure, and this three-dimensional integrated circuit structure is made by method as above.
The manufacture method of three-dimensional integrated circuit structure provided by the invention, without the reduction process and the through-silicon-via etching technics that carry out Semiconductor substrate, has therefore reduced the cost of manufacture of three-dimensional integrated circuit structure.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a manufacture method for three-dimensional integrated circuit structure, is characterized in that, comprising:
Steps A, provides substrate;
Step B forms the first chip dielectric layer in described substrate, in described the first chip dielectric layer, forms the first chip groove, in described the first chip groove, embeds the first chip, and the upper surface of described the first chip has the first weld pad;
Step C, on described the first chip dielectric layer, form the first via dielectric layer, in described the first via dielectric layer, form the first conductive through hole and the first conductive trench, wherein said the first conductive through hole is electrically connected to described the first weld pad, and described the first conductive trench is positioned at the upper surface of described the first via dielectric layer;
Step D forms the second chip dielectric layer in described the first via dielectric layer, in described the second chip dielectric layer, forms the second chip groove, in described the second chip groove, embeds the second chip, and the upper surface of described the second chip has the second weld pad; And
Step e, on described the second chip dielectric layer, form the second via dielectric layer, in described the second via dielectric layer, form the second conductive through hole, in described the second chip dielectric layer and described the second via dielectric layer, form the 3rd conductive through hole, in described the second via dielectric layer, form the second conductive trench, wherein said the second conductive through hole is electrically connected to described the second weld pad, and described the 3rd conductive through hole is electrically connected to described the first conductive trench.
2. manufacture method as claimed in claim 1, is characterized in that, between described the first chip dielectric layer and described substrate, is formed with pad oxide skin(coating).
3. manufacture method as claimed in claim 1, is characterized in that, between described the first via dielectric layer and described the second chip dielectric layer, forms etching stop layer.
4. manufacture method as claimed in claim 3, is characterized in that, described etching stop layer is nitrogenous silicon carbide layer.
5. manufacture method as claimed in claim 1, is characterized in that, described the first conductive trench comprises peripheral conductive trench, and the upper surface that described peripheral conductive trench is embedded in described the first via dielectric layer does not correspond in the region of described the first chip.
6. manufacture method as claimed in claim 1, is characterized in that, is formed with the first cover layer that covers described the first weld pad on described the first chip, is formed with the second cover layer that covers described the second weld pad on described the second chip.
7. manufacture method as claimed in claim 6, is characterized in that, described the first cover layer and described the second cover layer are nitrogenous silicon carbide layer or oxide skin(coating).
8. manufacture method as claimed in claim 1, is characterized in that, described the first chip dielectric layer, described the first via dielectric layer, described the second chip dielectric layer and/or described the second via dielectric layer are low k dielectric.
9. manufacture method as claimed in claim 1, is characterized in that, described manufacture method also comprises repetition above-mentioned steps D and E, to form a plurality of stacking chips in described substrate.
10. manufacture method as claimed in claim 1, is characterized in that, described substrate is silicon wafer.
11. manufacture methods as claimed in claim 1, is characterized in that, the thickness of described the first chip dielectric layer is greater than the thickness of described the first chip, and the thickness of described the second chip dielectric layer is greater than the thickness of described the second chip.
12. manufacture methods as claimed in claim 1, is characterized in that, described the first via dielectric layer, described the second via dielectric layer, described the first chip dielectric layer are identical with the material of described the second chip dielectric layer.
13. 1 kinds of three-dimensional integrated circuit structures, is characterized in that, described three-dimensional integrated circuit structure is that the method described in any one is made in claim 1-12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210261929.0A CN103579087B (en) | 2012-07-26 | 2012-07-26 | A kind of manufacture method of three-dimensional integrated circuit structure and three-dimensional integrated circuit structure |
Applications Claiming Priority (1)
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| WO2022227189A1 (en) * | 2021-04-26 | 2022-11-03 | 武汉新芯集成电路制造有限公司 | Three-dimensional integrated circuit module and fabrication method therefor |
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