CN103577110A - System on chip and read-write method thereof - Google Patents
System on chip and read-write method thereof Download PDFInfo
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- CN103577110A CN103577110A CN201210250227.2A CN201210250227A CN103577110A CN 103577110 A CN103577110 A CN 103577110A CN 201210250227 A CN201210250227 A CN 201210250227A CN 103577110 A CN103577110 A CN 103577110A
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Abstract
The invention discloses a system on a chip and a read-write method thereof. According to the system on the chip and the read-write method thereof, by enabling a read-write clock signal of a central processing unit and a read-write clock signal of a memory controller to a memory to be non-synchronous, instantaneous peak power consumption of the read-write operation of the central processing unit and the read-write operation of the memory controller to the memory occurs at different time. By the above technical scheme, the problem that the read-write operation of the central processing unit and the read-write operation of the storage controller to the memory are performed at the same time to result in the over-high instantaneous peak power consumption and further to affect system performance in the prior art can be solved.
Description
Technical field
The present invention relates to integrated circuit fields, relate in particular to the method for SOC (system on a chip) and read-write thereof.
Background technology
At present, along with developing rapidly of integrated circuit, the use of portable type electronic product is more and more extensive, SOC (system on a chip) also appears in portable electronic products more and more, and integrated degree is more and more higher, power problems, especially the problem of instantaneous peak value power consumption shows gradually.
SOC (system on a chip) generally comprises central processor CPU, storer ROM/RAM, non-volatile memory module (for example Flash/EEPROM) and other functional units, and wherein, the use of CPU and ROM/RAM is the most frequent, and power consumption is relatively large; Please refer to Fig. 1, existing SOC (system on a chip) generally adopts synchronous clock design, easily brings the too high phenomenon of instantaneous peak value power consumption, when system enters low-power consumption mode, system clock is frequency reducing thereupon, if instantaneous peak value power consumption is too high, can causes power-supply system job insecurity and affect the performance of system.
Summary of the invention
The invention provides the reading/writing method of a kind of SOC (system on a chip) and SOC (system on a chip), solve prior art SOC (system on a chip) and adopt Synchronization Design, easily occur that instantaneous peak value power consumption is too high, cause power work unstable and affect the problem of the performance of system.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
, comprise central processing unit, memory controller and storer; Wherein, described central processing unit receives the first clock signal, and the data that adopt described the first clock signal to carry out read-write operation and the transmission of reception memory controller to memory controller are processed; Described memory controller receives second clock signal, and adopts described second clock signal to carry out read-write operation and send data to described central processing unit described reservoir; The clock signal of upset when described second clock signal is different from described the first clock signal; Described storer, for storing data, and carries out read-write operation according to described second clock signal to the data of storage.
In an embodiment of the present invention, described SOC (system on a chip) also comprises clock controller, and wherein, described controller clock signal is for generation of described the first clock signal, and outputs in described central processing unit; Described memory controller receives the first clock signal and described the first clock signal is processed and obtained described second clock signal.
In an embodiment of the present invention, described SOC (system on a chip) also comprises clock controller, and wherein, described clock controller is for generation of described the first clock signal and described second clock signal; By described controller clock signal, produced, and output to respectively in described central processing unit and described memory controller.
In an embodiment of the present invention, described SOC (system on a chip) also comprises two clock controllers, wherein, two clock controllers be respectively used to produce described the first clock signal with and described second clock signal by two clock controllers, produced.
In an embodiment of the present invention, described memory controller comprises control module and data register, and wherein, described data register is for the data of buffer memory read-write; The first clock signal that described control module sends for receiving central processing unit, and delay process produces second clock signal described storer is carried out to read-write operation, or directly receive described second clock signal described storer is carried out to read-write operation.
A reading/writing method for SOC (system on a chip), comprises the following steps: produce the first clock signal and second clock signal; Central processing unit receives described the first clock signal, and the data that adopt described the first clock signal to carry out read-write operation and the transmission of reception memory controller to memory controller are processed; Memory controller receives second clock signal, and adopts described second clock signal to carry out read-write operation and send data to described central processing unit described reservoir; The clock signal of upset when described second clock signal is different from described the first clock signal.
In an embodiment of the present invention, described the first clock signal is produced and is outputed in described central processing unit by clock controller by gate; The first clock signal delay process that described second clock signal receives central processing unit output by memory controller produces.
In an embodiment of the present invention, described the first clock signal and second clock signal carry out different gates by clock controller and produce.
In an embodiment of the present invention, described the first clock signal and described second clock signal carry out a generation by two different clock controllers respectively.
In an embodiment of the present invention, memory controller carries out the step of read-write operation to storer according to second clock signal, also comprises the data of read-write are carried out to caching process.
Effective effect of the present invention is, adopt asynchronous design, central processing unit adopts respectively different clock signals to carry out read-write operation from memory controller controls storer, the read-write of central processing unit is separated the read-write operation of storer with memory controller, can not go out a peak power simultaneously, effectively reduce system instantaneous peak value power consumption; Solve prior art central processing unit read-write operation and memory controller the read-write operation of storer is carried out simultaneously, occur instantaneous peak value power consumption and affect the problem of system performance.
Accompanying drawing explanation
Fig. 1 is the SOC (system on a chip) read-write sequence figure that prior art adopts Synchronization Design;
The system on chip structure schematic diagram that Fig. 2 provides for the technical program one embodiment;
The SOC (system on a chip) read-write sequence figure that Fig. 3 provides for the technical program one embodiment.
Embodiment
Below by embodiment, by reference to the accompanying drawings the present invention is described in further detail.
Main inventive concept of the present invention is: by design central processing unit, adopt the first clock signal to carry out read-write operation, memory controller adopts second clock signal to carry out read-write operation to storer, make both in read-write operation process, can not occur instantaneous peak value power consumption simultaneously, effectively reduce system peak power consumption.
Please refer to Fig. 2, the system on chip structure schematic diagram that Fig. 2 provides for the technical program one embodiment; Comprise central processing unit 100, clock controller 200, memory controller 3 and storer 400; Wherein, clock controller 200 provides clock signal for SOC (system on a chip); Described central processing unit 100 initiates reservoir 400 to carry out the order of read-write operation to described memory controller 300 according to received clock signal, and the data that memory controller 300 is returned are processed; Memory controller 300 is responsible for, according to the read write command of described central processing unit 100, reservoir is carried out to read-write operation, and returns to corresponding data to described central processing unit 100.The entity that described reservoir 400 is storage data, the sequential of sending by memory controller 300 completes carries out read-write operation to stored data.
Described central processing unit 100 adopts the first clock signal to carry out read-write operation, described memory controller 300 adopts second clock signal to carry out read-write operation to storer 400, like this, described central processing unit 100 and be not simultaneously to carry out to the read-write operation of storer 400, trigger along can not overturn simultaneously, therefore, central processing unit 100 and the peak power that storer 400 is read and write can not occur simultaneously, effectively reduce SOC (system on a chip) instantaneous peak value power consumption number, even if system enters low-power consumption mode, peak power value can be not too high, makes power-supply system working stability.
Described the first clock signal carries out gate by described clock controller 200 or otherwise processed obtains, and outputs in described central processing unit 100, for described central processing unit 100, reads and writes sequential is provided; Described second clock signal carries out by clock controller 200 clock signal that gate or otherwise processed obtain being different from described the first clock signal, output in described memory controller 300, for 300 pairs of described storeies 400 of described memory controller, read and write sequential is provided.Having described clock controller 200 to produce respectively two-way different clocks signal outputs in described central processing unit 100 and described memory controller 300, so that work clock signal to be provided, can guarantee that described central processing unit 100 carries out read-write operation and 300 pairs of storeies of memory controller and carries out read-write operation and can not carry out simultaneously, instantaneous peak value power consumption can not occur simultaneously.
In another embodiment of the technical program, described second clock signal can not be directly by described clock controller 200, to be produced, described clock controller 200 produces the first clock signal and outputs in central processing unit 100, described memory controller 3 connects central processing unit 100 and receives described the first clock signal, described the first clock signal delay process is obtained to described second clock signal, and the second clock signal that then adopts time delay mode to process to obtain carries out read-write operation to described storer 400.Certainly, described memory controller is also nonessential by described the first clock signal of described central processing unit 100 acquisition, can directly connect described clock controller 200 and obtain described the first clock signal.
Further, described the first clock signal and described second clock signal, can be produced respectively and be outputed to respectively in described central processing unit 100 and described memory controller 300 by two different clock controllers 200 respectively.
In another embodiment of the technical program, described the first clock signal and described second clock the signal also nonessential clock controller by SOC (system on a chip) produce, can process and produce by other parts, even can receive the SOC (system on a chip) clock signal of other signal source input in addition.
In another embodiment of the technical program, described memory controller 300 comprises control module 301 and data register 302, wherein, the read write command that described control module 301 sends for receiving central processing unit 100, and according to described second clock signal, storer is carried out to read-write operation; Described data register 302 carries out mutual data message for temporary described storer 400 with described central processing unit 100; Generally, due to 3 pairs of described storeies 400 of described memory controller, to read and write adopted clock signal different from the clock signal that described central processing unit 1 read-write operation adopts, the data that described memory controller 3 is read can not directly turn back in central processing unit 100 by bus, need to the data of reading are temporary, when bus timing is appropriate, temporary data are returned in described central processing unit 100 by bus.
In another embodiment of the technical program, described clock controller 200 produces the first clock signal and outputs in described central processing unit 100 and memory controller 3, and described central processing unit 100 just triggers read-write operation along (being that clock signal changes to 1 rising edge by 0) according to the first clock signal; Described memory controller 300 triggers the read-write operation to storer 400 according to the negative edge of described the first clock signal (being that clock signal changes to 0 negative edge by 1).Like this, equally can so that described central processing unit 100 carry out when peak power that 300 pairs of storeies of peak power and described memory controller of read-write operation carry out read-write operation is different occurring, reduce the size of SOC (system on a chip) peak power, guarantee power-supply system steady operation.
In the technical program one embodiment, the reading/writing method of above-mentioned SOC (system on a chip) comprises the following steps:
Produce the first clock signal and second clock signal; Wherein, described the first clock signal and second clock signal are that two upsets when different trigger the clock signal on edge;
Central processing unit receives described the first clock signal, and the data that adopt described the first clock signal to carry out read-write operation and the transmission of reception memory controller to memory controller are processed;
Memory controller receives second clock signal, and adopts described second clock signal to carry out read-write operation and send data to described central processing unit described reservoir; The clock signal of upset when described second clock signal is different from described the first clock signal.
Wherein, the operation that the read-write operation of described central processing unit and described memory controller are read and write storer can be carried out according to just edge or the negative edge of clock signal.
In the technical program one embodiment, described the first clock signal can be processed generation by gate or other by clock controller 200; Described second clock signal can receive described the first clock signal by described memory controller 300 and carry out time delay or other processing generations.
In another embodiment of the technical program, described the first clock signal and described second clock signal can be controlled and produce two different clock signals for same clock controller 200.Wherein, described the first clock signal and described second clock signal condition can not overturn simultaneously.
In another embodiment of the technical program, described the first clock signal and described second clock signal can be produced by different clock controller 200 respectively.
In another embodiment of the technical program, described central processing unit 100 receives and carries out read-write operation according to same clock signal with described memory controller 300, wherein, described central processing unit 100 just carries out read-write operation along (being that signal changes to 1 rising edge by 0) according to clock signal, and described memory controller 300 carries out read-write operation according to the negative edge of clock signal (be signal transform to 0 negative edge by 1).
Please refer to Fig. 3, the SOC (system on a chip) read-write sequence figure that Fig. 3 provides for the technical program one embodiment.With SOC (system on a chip) central processing unit, sending continuously two data commands in read memory is described further.
Described central processing unit 100 sends the instruction of reading HADDR1 address constantly at t1, synchronization, described memory controller 300 receives the instruction that described central processing unit 100 sends, because described memory controller 300 carries out read-write operation according to second clock signal to storer 400, memory controller 300 receives the instruction that central processing unit sends can not carry out read-write operation to storer 400 immediately, at t1 ' constantly, 300 pairs of storeies of described memory controller 400 carry out read-write operation, and described storer 400 returns to described memory controller 300 by data; The clock signal of reading and writing due to 300 pairs of storeies 400 of memory controller is different from bus clock, therefore, the data that storer 400 returns need to be temporarily stored in data register 302, and produce a control signal, control the data in register are turned back in central processing unit 100 by bus; The data of when control signal is 0, storer 400 being returned directly output to bus concurrency and deliver in described central processing unit 100, when control signal is 1, the data in storage register 302 is outputed to bus concurrency and deliver in described central processing unit 100 and process.
Described central processing unit 100 sends the instruction of reading HADDR2 address constantly at t2, and starts to receive the data that memory controller 300 returns simultaneously; Synchronization, reads the instruction of HADDR2 address described in memory controller 300 receives, at t2 ' constantly, 300 pairs of storeies 400 of described memory controller start to carry out read-write operation, and described storer 400 returns to data in described memory controller 300; At t2 ' and t3 ' constantly, the data that storer 400 returns need to be kept in data register 302, and according to control signal, data are turned back in described central processing unit 100 and processed by bus.
Above content is in conjunction with concrete embodiment further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (10)
1. a SOC (system on a chip), comprises central processing unit, memory controller and storer; Wherein,
Described central processing unit receives the first clock signal, and the data that adopt described the first clock signal to carry out read-write operation and the transmission of reception memory controller to memory controller are processed;
Described memory controller receives second clock signal, and adopts described second clock signal to carry out read-write operation and send data to described central processing unit described reservoir; The clock signal of upset when described second clock signal is different from described the first clock signal;
Described storer, for storing data, and carries out read-write operation according to described second clock signal to the data of storage.
2. SOC (system on a chip) as claimed in claim 1, is characterized in that, also comprises clock controller, and wherein, described controller clock signal is for generation of described the first clock signal, and outputs in described central processing unit; Described memory controller receives the first clock signal and described the first clock signal is processed and obtained described second clock signal.
3. SOC (system on a chip) as claimed in claim 1, is characterized in that, also comprises clock controller, and wherein, described clock controller is for generation of described the first clock signal and described second clock signal; By described controller clock signal, produced, and output to respectively in described central processing unit and described memory controller.
4. SOC (system on a chip) as claimed in claim 1, is characterized in that, also comprises two clock controllers, wherein, two clock controllers be respectively used to produce described the first clock signal with and described second clock signal by two clock controllers, produced.
5. the SOC (system on a chip) as described in claim 1-4 any one, is characterized in that, described memory controller comprises control module and data register, and wherein, described data register is for the data of buffer memory read-write; The first clock signal that described control module sends for receiving central processing unit, and delay process produces second clock signal described storer is carried out to read-write operation, or directly receive described second clock signal described storer is carried out to read-write operation.
6. a reading/writing method for SOC (system on a chip), comprises the following steps;
Produce the first clock signal and second clock signal;
Central processing unit receives described the first clock signal, and the data that adopt described the first clock signal to carry out read-write operation and the transmission of reception memory controller to memory controller are processed;
Memory controller receives second clock signal, and adopts described second clock signal to carry out read-write operation and send data to described central processing unit described reservoir; The clock signal of upset when described second clock signal is different from described the first clock signal.
7. reading/writing method as claimed in claim 6, is characterized in that, described the first clock signal is produced and outputed in described central processing unit by clock controller by gate; Described second clock signal receives the first clock signal delay process by memory controller and produces.
8. reading/writing method as claimed in claim 6, is characterized in that, described the first clock signal and second clock signal carry out different gates by clock controller and produce.
9. reading/writing method as claimed in claim 1, is characterized in that, described the first clock signal and described second clock signal carry out gate generation by two different clock controllers respectively.
10. the reading/writing method as described in claim 6-9 any one, memory controller carries out the step of read-write operation to storer according to second clock signal, also comprise the data of read-write are carried out to caching process.
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| CN104460825A (en) * | 2014-11-25 | 2015-03-25 | 上海高性能集成电路设计中心 | Multi-core processor clock distribution device |
| CN106774799A (en) * | 2016-12-08 | 2017-05-31 | 上海爱信诺航芯电子科技有限公司 | A kind of reduction Soc systems list claps the method and device of peak power |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104268347A (en) * | 2014-09-30 | 2015-01-07 | 中国电子科技集团公司第三十八研究所 | Anti-radiation SRAM chip rear end physical design method applicable to nanoscale processes |
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