CN103516455B - Data synchronism method and device - Google Patents
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- CN103516455B CN103516455B CN201210207815.8A CN201210207815A CN103516455B CN 103516455 B CN103516455 B CN 103516455B CN 201210207815 A CN201210207815 A CN 201210207815A CN 103516455 B CN103516455 B CN 103516455B
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Abstract
The embodiment of the invention provides a data synchronism method and a device. The method comprises the following steps: 1:N demultiplexing is conducted on inputted data by the utilization of a set asynchronous clock to obtain N-path data with transmission rate being 1/N of transmission rate of the inputted data and a first synchronizing signal with cycle being 2N of the cycle of the asynchronous clock; delay is conducted on the first synchronizing signal by the utilization of a set synchronous clock to obtain a second synchronizing signal and a third synchronizing signal; whether the second synchronizing signal is equal to the third synchronizing signal is determined at each sampling edge of the synchronized clock and an edge trigger signal is generated to carry out count operation; and sampling is conducted successively on the N-path data by the utilization of the synchronized clock and each outputted count value so as to obtain N:1 multiplexing output data. According to the invention, the problems of high RAM resource requirement and long delay time are solved.
Description
Technical field
The present invention relates to digital signal transmission field, more particularly, to a kind of method and device of data syn-chronization.
Background technology
With digital display circuit scale is increasing, complexity more and more higher, two or more clock zones set in logic
Application in meter gets more and more.In different clock zones, inevitably run into the mutual transmission of data.Due to two not
With clock between can there is certain phase contrast and frequency jitter in short-term, in order that data can transmitting, carrying out
During design it is necessary to when taking into full account ordered pair function impact, otherwise can shine into the failure of data synchronization between two clock zones.
At present, data is transformed into, by asynchronous clock domain, the method that synchronous clock domains generally adopt double-interface RAM buffer data
To realize：Write clock with asynchronous clock as dual port RAM, write the write address that clock produces dual port RAM, by writing clock at one
Port writes data；Use synchronised clock again as reading clock, and produce the reading address of dual port RAM, read clock in another port
Read data；This dual port RAM depth is the scope of frequency difference in short-term tolerated as needed to be determined.Respectively that read/write address is synchronous
Whether clock sampling is simultaneously compared, to judge the distance between read/write address less than it may happen that the narrow spacing of reading and writing conflict
From, i.e. " risk distance ", if it is, by read address redirect, go to behind the farthest address in current location, then execute reading behaviour
Make；Reading address otherwise need not be adjusted, directly execute read operation.
The data reading out through said method although can reach not only stable but also correct, can also shield asynchronous clock and
Phase contrast between local synchronous clock and frequency jitter problem in short-term, are capable of the data syn-chronization of asynchronous clock domain,
But utilize the method, need to rely on the RAM resource of PLD, additionally, the delay time of synchrodata is longer, need
To be determined by the projected depth of dual port RAM.
Content of the invention
Embodiments provide a kind of method and device of data syn-chronization, in order to solve in available data simultaneous techniquess
And delay time longer problem higher to the depth requirements of RAM.
Based on the problems referred to above, a kind of method of data syn-chronization provided in an embodiment of the present invention, including：
Using the asynchronous clock setting, 1 is carried out to the data of input：N demultiplexes, and obtaining every road transfer rate is input
The N circuit-switched data of the 1/N of data and cycle are first synchronizing signal in 2N asynchronous clock cycle, and wherein N is the integer more than 1；
Using the synchronised clock setting, described first synchronizing signal is carried out with delay and obtain the second synchronizing signal and the 3rd together
Step signal, described second synchronizing signal differs at least one synchronised clock cycle with described 3rd synchronizing signal；
On each edge of sampling of described synchronised clock, judge whether are described second synchronizing signal and described 3rd synchronizing signal
Equal, and when first time judging unequal, generate along trigger and be counted as the first numerical value setting, and counting
For proceeding to count according to the cycle of synchronised clock after the first numerical value of setting, when on generating once along trigger
Judge whether upper one numerical value counting is the second value setting, if so, proceed to count；If it is not, setting described in being counted as
The first fixed numerical value；It is sequentially output the numerical value of each counting；
Using the numerical value of described synchronised clock and each counting of output, successively described N circuit-switched data is sampled, obtain N：
The output data of 1 multiplexing.
A kind of device of data syn-chronization provided in an embodiment of the present invention, including：
Demultiplexing module, for carrying out 1 using the asynchronous clock setting to the data of input：N demultiplexes, and obtains every road and passes
Defeated speed is the N circuit-switched data of the 1/N of data inputting and the cycle is first synchronizing signal in 2N asynchronous clock cycle, wherein N
It is the integer more than 1；
Synchronization module, for believing using the synchronised clock setting is synchronous to described first obtaining through described demultiplexing module
Number carrying out delay obtains the second synchronizing signal and the 3rd synchronizing signal, described second synchronizing signal and described 3rd synchronizing signal phase
Differ from a synchronised clock cycle, and for each edge of sampling in described synchronised clock, judge described second synchronizing signal and institute
Whether equal state the 3rd synchronizing signal, and generate along trigger when unequal；
Counting module, generates along trigger when first time judging unequal for receiving described synchronization module, and
And be counted as the first numerical value setting, and proceed to count according to the cycle of synchronised clock after the first numerical value being counted as setting
Number, described counting module is receiving the upper once counting along in the moment judgement of trigger that described synchronization module generates
Numerical value be whether the second value setting, if so, proceed to count；If it is not, being counted as the first numerical value of described setting；Institute
State the numerical value that counting module is sequentially output each counting；
Multiplexing module, for the numerical value using described synchronised clock and each counting of described counting module output, right successively
Described N circuit-switched data is sampled, and obtains N：The output data of 1 multiplexing.
The beneficial effect of the embodiment of the present invention includes：The method and device of data syn-chronization provided in an embodiment of the present invention, profit
With the asynchronous clock setting, 1 is carried out to the data of input：After N demultiplexing obtains N circuit-switched data and the first synchronizing signal, recycling sets
Fixed synchronised clock carries out delay and obtains the second synchronizing signal and the 3rd synchronizing signal, then according to synchronization to the first synchronizing signal
Clock sampling, along judging whether the second synchronizing signal and the 3rd synchronizing signal are equal, generates and carries out counting operation along trigger,
Finally utilize the numerical value of each counting of synchronised clock and output, successively N circuit-switched data being carried out sampling can get synchrodata.This
Inventive embodiments can make the data of input after demultiplexing generates multichannel data, is compared according to two-way synchronizing signal,
Flip-flop number is counted, the numerical value according to enumerator is sampled to multichannel data and is multiplexed output, decreases data transfer
Time delay, it is to avoid in available data simultaneous techniquess, needs the RAM resource relying on PLD to solve asking of data syn-chronization
Topic, meanwhile, the synchronizing relay of data can also preferably be controlled it is not necessary to be determined by the projected depth of dual port RAM.
Brief description
Fig. 1 is the flow chart of the method for data syn-chronization provided in an embodiment of the present invention；
Fig. 2 is one of sequential chart of data synchronization process provided in an embodiment of the present invention；
Fig. 3 is the two of the sequential chart of data synchronization process provided in an embodiment of the present invention；
Fig. 4 is the structural representation of the device of data syn-chronization provided in an embodiment of the present invention；
Fig. 5 interacts schematic diagram for synchronization module provided in an embodiment of the present invention with counting module.
Specific embodiment
With reference to Figure of description, concrete to a kind of method and device of data syn-chronization provided in an embodiment of the present invention
Embodiment illustrates.
A kind of method of data syn-chronization provided in an embodiment of the present invention, as shown in figure 1, specifically include following steps：
S101：Using the asynchronous clock setting, 1 is carried out to the data of input：N demultiplexes, and it is defeated for obtaining every road transfer rate
The N circuit-switched data of the 1/N of the data entering and cycle are first synchronizing signal in 2N asynchronous clock cycle, and wherein N is whole more than 1
Number.
It is preferred that above-mentioned first synchronizing signal can be obtained by following manner：
Using the frame header position of any one circuit-switched data after demultiplexing as the rising edge of the first synchronizing signal or trailing edge, with
At least above 2 asynchronous clock cycles as the pulse width of the first synchronizing signal, obtain the first synchronizing signal.
Specifically, in embodiments of the present invention, can be using the rising edge of asynchronous clock setting or trailing edge to input
Data carry out 1：N demultiplexes, and makes the speed of the data of input drop to original 1/N during demultiplexing.
As shown in Fig. 2 by homology but it is assumed that N=3 as a example having the asynchronous clock of transmission delay change, using asynchronous when
The rising edge of clock demultiplexes to 1 circuit-switched data (data A+ data B+ data C) of input, after demultiplexing in t1 moment, t2
Carve and the t3 moment exports 3 circuit-switched data respectively, i.e. data D0(data A after corresponding speed reduction), data D1(corresponding speed reduces
Data B afterwards) data D2(data C after corresponding speed reduction)；Data D with the t1 moment0As a example, output data D0When
Speed is 1/3 of data A in original 1 circuit-switched data inputting；
In the process, also with data D0Frame header position as rising edge, to make at least above 2 asynchronous clock cycles
The cycle obtaining for pulse width is first synchronizing signal in 6 asynchronous clock cycles（sync）.In embodiments of the present invention, it is
Ensure that the follow-up synchronised clock setting reliable samples can arrive data, the pulse width needs of sync are at least above 2 asynchronous
Clock cycle.
S102：Using the synchronised clock setting, the first synchronizing signal is carried out with delay and obtain the second synchronizing signal and the 3rd together
Step signal, the second synchronizing signal differs a synchronised clock cycle with the 3rd synchronizing signal.
It is preferred that the second synchronizing signal and the 3rd synchronizing signal are obtained by following manner：
Rising edge or trailing edge according to synchronised clock postpone to the first synchronizing signal, obtain the second synchronizing signal；
3rd synchronizing signal is obtained to one synchronised clock cycle of the second sync signal delay.
As shown in Fig. 2 postponing to the sync obtaining using the trailing edge of synchronised clock, obtain second in the k0 moment same
Step signal (sync1), postpones 1 synchronizing cycle to sync1 and obtains the 3rd synchronizing signal (sync2) in the k1 moment.
S103：On each edge of sampling of synchronised clock, judge whether the second synchronizing signal and the 3rd synchronizing signal are equal, and
When first time judging unequal, generate along trigger and be counted as the first numerical value setting, and be counted as setting
The first numerical value after according to the cycle of synchronised clock proceed count, generate on once along trigger moment judge along
Whether the numerical value of one counting is the second value setting, and if so, proceeds to count；If it is not, be counted as setting first sets
Fixed number value；It is sequentially output the numerical value of each counting.
It is preferred that above-mentioned can be counted using M digit counter, whereinI.e. the value of M is log2N
On round.
In above-mentioned steps S103, each sampling using synchronised clock judges sync1 and sync2 not along in first time
When equal, generate along trigger, in this moment, enumerator starts counting up, be counted as the first numerical value setting, i.e. the first number
Value refers to the numerical value that enumerator starts counting up.In embodiments of the present invention, enumerator can carry out accumulated counts from 0 to N-1,
Countdown can be carried out from N-1 to 0, counting can also be proceeded by from 2 or 3 etc., that is, the first numerical value setting can for 0,
2nd, 3 or N-1 etc..
Specifically, in practical application, in order to avoid loss of clock or burr can cause the slip of output data, under
Once generate the moment along trigger, last count value can be judged, if it is judged that the meter of last time
Number numerical value is the second value setting, then enumerator is without adjustment, continue to add up according to the cycle of counting (synchronised clock same period) (or
Successively decrease) counted, if not the second value setting, then rolling counters forward is the first numerical value setting.In this bright enforcement
In example, the second value of setting be for be subsequently generated the moment along trigger on the count value of once enumerator enter
The numerical value that row judges, the value of second value can flexibly select, for example, the second value of setting can be 2 or 5,
6 or 0.In embodiments of the present invention, the first numerical value of setting and the second value setting can identical it is also possible to different.
As illustrated in fig. 2, it is assumed that N=3, then M=2, counted using 2 digit counters, in FIG. 2, it is assumed that set
First numerical value be 0, that is, enumerator start counting up from 0, the second value setting be 2, generation along trigger the y0 moment, sentence
Break and last count results for 2, the as second value of setting, this hour counter proceeds to count, and is counted as 0, after
Continue and export 1,2 and 0 respectively in y1, y2 and y3 moment.
S104：Using the numerical value of synchronised clock and each counting of output, successively N circuit-switched data is sampled, obtain N：1 is multiple
Output data.
It is preferred that the embodiment of the present invention can be entered to N circuit-switched data using synchronised clock from the beginning of arbitrary count value successively
Row sampling, obtains N：The output data of 1 multiplexing.
As shown in Fig. 2 being output as 0 in y0 time trigger enumerator, synchronised clock is sampled as 0 in the y1 moment to enumerator,
According to count value 0 to data D0Sampling output (one piece of data A)；In the y2 moment, according to count value 1 to data D1Sampling is defeated
Go out (one piece of data B)；In the y3 moment according to count value 2 to data D2Sampling output (one piece of data C).Concrete sampling process belongs to
In prior art, will not be described here.
Above-mentioned Fig. 2 is the explanation embodiment of the present invention being carried out taking N=3 as a example, for comprising D (0), D (1) ... D (N-
1) multiple segment data carries out 1 using asynchronous clock to the data of input：The situation of N demultiplexing, as shown in figure 3, asynchronous clock adopts
Rising edge is processed, and input data is started demultiplex in the t0 moment, after demultiplexing respectively when the ensuing t1 moment is to t (N)
The N number of clock cycle carved, export D respectively0、D1、D2、....DN-1Data after the demultiplexing of common N road, the speed of every circuit-switched data is former
Carry out the 1/N of input data, synchronizing signal sync with 2N asynchronous clock width as cycle, in t0 moment saltus step, with D0Frame head position
Put alignment.By sync and synchronised clock, synchronizing signal sync1 after being postponed and sync2, after both are compared, count
Device is counted as 0,1,2 ... N-1, and the value according to rolling counters forward is respectively to D0、D1、D2、....DN-1Sampled, multiplexing output
Data.D (0), the data of D (1) ' ... and D0、D1、D2、....DN-1The synchronous method of data is similar to.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of device of data syn-chronization, by this device institute
The principle of the solve problem method synchronous to aforementioned data is similar, and the enforcement of therefore this device may refer to the reality of preceding method
Apply, repeat no more in place of repetition.
As shown in figure 4, the embodiment of the present invention provides the device of data syn-chronization, including：
Demultiplexing module 401, for carrying out 1 using the asynchronous clock setting to the data of input：N demultiplexes, and obtains every
Individual width is the N circuit-switched data in N number of asynchronous clock cycle and the cycle is first synchronizing signal in 2N asynchronous clock cycle, wherein N
It is the integer more than 1.
It is preferred that demultiplexing module 401 specifically for any one circuit-switched data after to demultiplex frame header position as the
The rising edge of one synchronizing signal or trailing edge, using at least above 2 asynchronous clock cycles as the first synchronizing signal pulse width
Degree, obtains the first synchronizing signal.
Synchronization module 402, for the first synchronizing signal demultiplexed module 401 being obtained using the synchronised clock setting
Carry out delay and obtain the second synchronizing signal and the 3rd synchronizing signal, the second synchronizing signal differs at least one with the 3rd synchronizing signal
The synchronised clock cycle, and for each edge of sampling in synchronised clock, judge whether are the second synchronizing signal and the 3rd synchronizing signal
Equal, and generate along trigger when unequal.
It is preferred that synchronization module 402 specifically for according to the rising edge of synchronised clock or trailing edge to the first synchronizing signal
Postponed, obtained the second synchronizing signal；3rd synchronizing signal is obtained to one synchronised clock cycle of the second sync signal delay.
Counting module 403, generates along trigger when first time judging unequal for receiving synchronization module 402,
And it is counted as the first numerical value setting, and proceed according to the cycle of synchronised clock after the first numerical value being counted as setting
Count, counting module 403 is receiving a upper once counting along in the moment judgement of trigger of synchronization module 402 generation
Numerical value be whether the second value setting, if so, proceed to count；If it is not, being counted as the first numerical value setting；Count module
Block 403 is sequentially output the numerical value of each counting.
It is preferred that counting module 403 isEnumerator.
In embodiments of the present invention, synchronization module 402 in the specific implementation, can be synchronous by signal as shown in Figure 5
Unit 501（Generate two-way synchronizing signal sync1 and sync2）, judging unit 502（Two-way synchronizing signal is judged whether equal）
And M digit counter 403 realizes, certainly, the embodiment of the present invention is also not necessarily limited to this kind of specific structure zoned format.
Multiplexing module 404, for the numerical value using synchronised clock and each counting of counting module output, successively to N way
According to being sampled, obtain N：The output data of 1 multiplexing.
It is preferred that Multiplexing module 404 can be entered to N circuit-switched data using synchronised clock from the beginning of arbitrary count value successively
Row sampling, obtains N：The output data of 1 multiplexing.
The method and device of data syn-chronization provided in an embodiment of the present invention, using the data to input for the asynchronous clock setting
Carry out 1：After N demultiplexing obtains N circuit-switched data and the first synchronizing signal, recycle the synchronised clock setting that the first synchronizing signal is entered
Row delay obtains the second synchronizing signal and the 3rd synchronizing signal, then according to synchronised clock sampling along judge the second synchronizing signal with
Whether the 3rd synchronizing signal is equal, generates and carries out counting operation along trigger, finally utilizes each meter of synchronised clock and output
The numerical value of number, successively N circuit-switched data being carried out sampling can get synchrodata.The embodiment of the present invention can make the data of input exist
After demultiplexing generates multichannel data, according to the count value that two-way synchronizing signal is compared with generation, multichannel data is sampled
And synchronism output, decrease the time delay of data transfer, it is to avoid in available data simultaneous techniquess, need to rely on programmable logic device
The RAM resource of part solves the problems, such as data syn-chronization, meanwhile, the synchronizing relay of data can also preferably be controlled it is not necessary to
To be determined by the projected depth of dual port RAM.
Obviously, those skilled in the art can carry out the various changes and modification essence without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprise these changes and modification.
Claims (8)
1. a kind of method of data syn-chronization is it is characterised in that include：
Using the asynchronous clock setting, 1 is carried out to the data of input：N demultiplexes, and obtains the data that every road transfer rate is input
The N circuit-switched data of the 1/N of transfer rate and cycle are first synchronizing signal in 2N asynchronous clock cycle, and wherein N is whole more than 1
Number；Using the synchronised clock setting, described first synchronizing signal is carried out with delay and obtain the second synchronizing signal and the 3rd synchronous letter
Number, described second synchronizing signal differs a synchronised clock cycle with described 3rd synchronizing signal；
On each edge of sampling of described synchronised clock, judge described second synchronizing signal and described 3rd synchronizing signal whether phase
Deng, and when first time judging unequal, generate along trigger and be counted as the first numerical value setting, and be counted as
Proceed to count according to the cycle of synchronised clock after the first numerical value setting, once sentence along the moment of trigger on generating
Whether the numerical value of a disconnected upper counting is the second value setting, and if so, proceeds to count, if it is not, being counted as described setting
The first numerical value；It is sequentially output the numerical value of each counting；
Using the numerical value of described synchronised clock and each counting of output, successively described N circuit-switched data is sampled, obtain N：1 is multiple
Output data.
2. the method for claim 1 is it is characterised in that the first synchronizing signal is obtained by following manner：To demultiplex
The frame header position of any one circuit-switched data afterwards as the rising edge of the first synchronizing signal or trailing edge, with least above 2
The asynchronous clock cycle, as the pulse width of the first synchronizing signal, obtains described first synchronizing signal.
3. the method for claim 1 is it is characterised in that entered to described first synchronizing signal using the synchronised clock setting
Row delay obtains the second synchronizing signal and the 3rd synchronizing signal, including：
Rising edge or trailing edge according to described synchronised clock postpone to described first synchronizing signal, obtain described second same
Step signal；
Described 3rd synchronizing signal is obtained to described one synchronised clock cycle of second sync signal delay.
4. the method for claim 1 is it is characterised in that counted using M digit counter, wherein
5. a kind of device of data syn-chronization is it is characterised in that include：Demultiplexing module, for using the asynchronous clock pair setting
The data of input carries out 1：N demultiplexes, and obtains the N way that every road transfer rate is the 1/N of message transmission rate of input
According to the cycle for 2N asynchronous clock cycle the first synchronizing signal, wherein N is the integer more than 1；
Synchronization module, for being entered to described first synchronizing signal obtaining through described demultiplexing module using the synchronised clock setting
Row delay obtains the second synchronizing signal and the 3rd synchronizing signal, and described second synchronizing signal differs one with described 3rd synchronizing signal
The individual synchronised clock cycle, and for each edge of sampling in described synchronised clock, judge described second synchronizing signal and described the
Whether three synchronizing signals are equal, and generate along trigger when unequal；
Counting module, generates along trigger when first time judging unequal for receiving described synchronization module, and counts
Number is the first numerical value setting, and proceeds to count according to the cycle of synchronised clock after the first numerical value being counted as setting,
Described counting module is receiving the upper once counting along in the moment judgement of trigger that described synchronization module generates
Whether numerical value is the second value setting, and if so, proceeds to count；If it is not, being counted as the first numerical value of described setting；Described
Counting module is sequentially output the numerical value of each counting；
Multiplexing module, for the numerical value using described synchronised clock and each counting of described counting module output, successively to described N
Circuit-switched data is sampled, and obtains N：The output data of 1 multiplexing.
6. the device of data syn-chronization as claimed in claim 5 is it is characterised in that described Multiplexing module, specifically for demultiplex
With after any one circuit-switched data frame header position as the rising edge of the first synchronizing signal or trailing edge, with different at least above 2
The step clock cycle, as the pulse width of the first synchronizing signal, obtains described first synchronizing signal.
7. the device of data syn-chronization as claimed in claim 5 is it is characterised in that described synchronization module, specifically for according to institute
State the rising edge of synchronised clock or trailing edge postpones to described first synchronizing signal, obtain described second synchronizing signal；Right
Described one synchronised clock cycle of second sync signal delay obtains described 3rd synchronizing signal.
8. the device of data syn-chronization as claimed in claim 5 is it is characterised in that described counting module for digit is
Enumerator.
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| CN105515752B (en) * | 2015-12-07 | 2018-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of method of data synchronization for eliminating network clocking deviation |
| CN106897233B (en) * | 2015-12-17 | 2021-06-18 | 格科微电子（上海）有限公司 | Source synchronous circuit of data transmission interface |
| CN111740829B (en) * | 2020-08-03 | 2020-12-04 | 北京中创为南京量子通信技术有限公司 | Synchronization method and device of quantum key distribution system |
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| CN102204204A (en) * | 2011-05-20 | 2011-09-28 | 华为技术有限公司 | A method for realizing pulse synchronization and a device thereof |
| WO2011134251A1 (en) * | 2010-04-30 | 2011-11-03 | 中兴通讯股份有限公司 | Method and system for synchronously transmitting asynchronous data |
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| CN101834683A (en) * | 2010-03-24 | 2010-09-15 | 珠海市佳讯实业有限公司 | Device for realizing fixed forwarding delay of V.24 interface multiplexer |
| WO2011134251A1 (en) * | 2010-04-30 | 2011-11-03 | 中兴通讯股份有限公司 | Method and system for synchronously transmitting asynchronous data |
| CN102204204A (en) * | 2011-05-20 | 2011-09-28 | 华为技术有限公司 | A method for realizing pulse synchronization and a device thereof |
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Effective date of registration: 20160914 Address after: 300308 Tianjin Airport Economic Zone, Binhai New Area seven East Road No. 2 Zhongxing Industrial Base Applicant after: ZTE INTELLIGENT IOT TECHNOLOGY Co.,Ltd. Address before: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Applicant before: ZTE Corp. |
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Address after: Room 401, building 12, east area, airport business park, No. 80, Huanhe North Road, free trade zone (Airport Economic Zone), Binhai New Area, Tianjin 300000 Patentee after: Gaoxing Zhilian Technology Co.,Ltd. Address before: 300308, Zhongxing Industrial base, 2 East seven, Airport Economic Zone, Tianjin Binhai New Area Patentee before: ZTE INTELLIGENT IOT TECHNOLOGY Co.,Ltd. |
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Address after: Room 401, building 12, East Airport Business Park, 80 Huanhe North Road, Tianjin Binhai New Area pilot free trade zone (Airport Economic Zone) Patentee after: Zte Intelligent Iot Technology Co.,Ltd. Address before: Room 401, building 12, East Airport Business Park, 80 Huanhe North Road, Tianjin Binhai New Area pilot free trade zone (Airport Economic Zone) Patentee before: Gaoxing Zhilian Technology Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder |