CN102301639B - Method and device for correcting clock jitter - Google Patents
Method and device for correcting clock jitter Download PDFInfo
- Publication number
- CN102301639B CN102301639B CN201180001223.4A CN201180001223A CN102301639B CN 102301639 B CN102301639 B CN 102301639B CN 201180001223 A CN201180001223 A CN 201180001223A CN 102301639 B CN102301639 B CN 102301639B
- Authority
- CN
- China
- Prior art keywords
- clock
- data
- buffer
- local clock
- ethernet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 55
- 230000001360 synchronised effect Effects 0.000 claims abstract description 22
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 claims description 163
- 125000001033 ether group Chemical group 0.000 claims description 15
- 238000012937 correction Methods 0.000 claims description 13
- 238000011084 recovery Methods 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 6
- 238000012545 processing Methods 0.000 abstract description 13
- 238000006243 chemical reaction Methods 0.000 description 11
- 101100311460 Schizosaccharomyces pombe (strain 972 / ATCC 24843) sum2 gene Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 230000026676 system process Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
An embodiment of the present invention provides a method and a device for correcting a clock jitter. The method comprises the steps of: inputting received data into a register according to an Ethernet clock recovered from the received data, wherein the received data comprises Ethernet Frames and interframe spaces between the adjacent Ethernet Frames; and during the process of reading the received data from the register according to a local clock, if data volume of the received data registered in the register is more than a first threshold, deducting invalid data with a first defined amount from the interframe spaces, or if data volume of the received data registered in the register is less than a second threshold, inserting invalid data with a second defined amount into the interframe spaces, so as to obtain output data output from the register, wherein the local clock is synchronous with the Ethernet clock. By adopting the above technical scheme, the influence of the clock jitter to follow-up system processing, which is introduced by the Ethernet, can be reduced, restricted requirements for the clock jitter can be satisfied, and the clock jitter can be restricted within an index acceptable scope.
Description
Technical field
The present invention relates to the communications field, and more specifically, relate to the method and apparatus of position shake in the communications field.
Background technology
Common public radio interface (The Common Public Radio Interface, CPRI) defined radio equipment controller (Radio Equipment Controller, REC) with wireless device (Radio Equipment, RE) interface relationship between, a kind of far-drawing system of formation base station.
Not only there is at present non-grouping CPRI transmission, also have grouping CPRI transmission.In grouping CPRI transmission, CPRI base frame is encapsulated in Ether frame and is transmitted, now CPRI base frame will pass through Ethernet and arrive receiving terminal.
For instance, in the time that REC sends CPRI base frame by Ethernet to RE, REC generates CPRI base frame under the effect of CPRI master clock, and each CPRI base frame has the length of 260.4ns, and there is no interval between adjacent C PRI base frame.For CPRI base frame is sent into Ethernet, CPRI clock need to be converted to ethernet clock and CPRI base frame data are carried in Ether frame, the frame head of adjacent Ether frame remains on 260.4ns apart from hope.But, after Ether frame is outputed to Ethernet link, by the forwarding of Ethernet switch, isolate the clock of communicating pair, and introduced larger clock jitter for Ether frame, make the frame head of the Ether frame that RE receives apart from occurring larger shake.Through clock zone, conversion is converted to CPRI after clock by ethernet clock to RE, for the CPRI base frame obtaining from Ether frame, there is larger shake in the length of each CPRI base frame, be difficult to meet the REC master clock of CPRI system requirements and RE are less than 0.002ppm index from the shake between clock, make RE be difficult to be locked into REC master clock from clock, follow-up CPRI base frame processing is brought to adverse effect.
As can be seen here, in the time carrying the Ether frame of CPRI base frame data and transmit in Ethernet, due to the existence of clock jitter, although make to there is equal interFrameGap from the Ether frame of REC output, but there is shake in the interFrameGap of the Ether frame that RE receives, the interval of Ether frame becomes disorderly and unsystematic.Due to the interFrameGap shake between Ether frame, cause the CPRI base frame extracting from Ether frame to occur shake, little when large when between CPRI base frame the interval, this can not meet the shake index of CPRI system requirements, for the processing real-time of CPRI base frame has caused great difficulty, even cause the follow-up collapse to the processing of CPRI base frame.
Summary of the invention
The embodiment of the present invention provides the method and apparatus of position shake, can reduce the impact of clock jitter on follow-up system processing that Ethernet is introduced, make to meet the restriction requirement to clock jitter, clock jitter is limited in the acceptable scope of index.
An aspect of of the present present invention, a kind of method that provides position to shake, comprising: according to the ethernet clock recovering from receive data, by described reception data input buffer, described reception data comprise the interFrameGap between Ether frame and adjacent Ether frame; Reading the process of described reception data from described buffer according to local clock, if the data volume of the reception data of buffer memory exceedes the first thresholding in described buffer, in interFrameGap, deduct the invalid data of the first predetermined quantity, or, if the data volume of the reception data of buffer memory is lower than the second thresholding in described buffer, in interFrameGap, insert the invalid data of the second predetermined quantity, obtain from output data, wherein said local clock and the described ethernet clock synchronised of described buffer output.
Another aspect of the present invention, provides a kind of device for position shake, comprising: clock recovery module, and for recovering ethernet clock from receiving data, described reception data comprise the interFrameGap between Ether frame and adjacent Ether frame; Buffer, the reception data of inputting according to described ethernet clock for buffer memory; Local clock, is used to and reads described reception data from described buffer clock frequency is provided; Shake correction module, be used in the process that reads described reception data according to described local clock from described buffer, if the data volume of the reception data of buffer memory exceedes the first thresholding in described buffer, in interFrameGap, deduct the invalid data of the first predetermined quantity, or, if the data volume of the reception data of buffer memory is lower than the second thresholding in described buffer, in interFrameGap, insert the invalid data of the second predetermined quantity, obtain from output data, wherein said local clock and the described ethernet clock synchronised of described buffer output.
Based on technique scheme, receive data according to ethernet clock input buffer, and according to the local clock output state of ethernet clock synchronised, utilize the data volume of buffer memory and the relation of thresholding in buffer, the interFrameGap data that receive in data are removed and inserted, thereby can proofread and correct the clock jitter that Ethernet is introduced, make to there is data flow form stably from the output data of buffer output, can reduce thus the impact of clock jitter on follow-up system processing that Ethernet is introduced, clock jitter can be limited in to follow-up system processes in acceptable scope.
Brief description of the drawings
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, to the accompanying drawing of required use in embodiment be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those skilled in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the schematic diagram of the example of application scenarios.
Fig. 2 is according to the flow chart of the method for the position shake of the embodiment of the present invention.
Fig. 3 is the flow chart that passes through to deduct and insert invalid data and come the method for position shake according to the embodiment of the present invention.
Fig. 4 is according to the flow chart of the method that local clock is synchronizeed with ethernet clock of the embodiment of the present invention.
Fig. 5 is the block diagram of realizing according to the method that local clock is synchronizeed with ethernet clock of the embodiment of the present invention.
Fig. 6 is the schematic diagram of realizing the object lesson of method shown in Fig. 5.
Fig. 7 is the block diagram of realizing according to the object lesson of the method for the position shake of the embodiment of the present invention.
Fig. 8 is according to the structured flowchart of the device for position shake of the embodiment of the present invention.
Fig. 9 is according to the structured flowchart of another device for position shake of the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme of the embodiment of the present invention is clearly and completely described, obviously, described embodiment is a part of embodiment of the present invention, instead of whole embodiment.Based on the described embodiment in the present invention, the every other embodiment that those skilled in the art obtain under the prerequisite of not making creative work, should belong to the scope of protection of the invention.
First, the concrete scene of the method for utilizing the position shake that the embodiment of the present invention provides is described in conjunction with Fig. 1.This concrete scene is an example, protection scope of the present invention is not formed to any restriction.
In the application scenarios shown in Fig. 1, transmitting terminal can be REC, and now receiving terminal is RE; Or transmitting terminal can be also RE, now receiving terminal is REC.Easy for what describe, below taking transmitting terminal as REC, receiving terminal is described as RE as example.
For example, REC generates CPRI base frame according to CPRI clock, and each CPRI base frame can be 260.4ns.For CPRI base frame is transmitted by Ethernet, through clock zone conversion process, frame conversion process, the valid data in CPRI base frame are encapsulated in Ether frame.Wherein, clock zone conversion in REC can be converted to ethernet clock by CPRI clock, frame conversion in REC can be by separating CPRI base frame, valid data are wherein extracted, valid data be carried in Ether frame again and be combined into Ether frame, the interFrameGap after each Ether frame adds is 260.4ns.But because very little randomized jitter A is introduced in clock zone conversion, therefore each Ether frame adds that interFrameGap is afterwards 260.4ns+A.
In the process that Ether frame transmits via Ethernet, due to the impact of Ethernet switch etc., be that Ether frame is introduced larger randomized jitter B, therefore, the frame head of the Ether frame that RE receives is spaced apart 260.4ns+A+B, has exceeded the restriction index of 0.002ppm.
If obtain CPRI base frame the Ether frame directly receiving from RE, CPRI base frame will have larger clock jitter, the clock jitter that can not meet CPRI standard-required maintains the requirement within the scope of 0.002ppm, will be affected to the subsequent treatment of CPRI base frame, even causes the collapse of system.The Ether frame position shake that therefore, need to receive RE.
In clock jitter correction module in RE, utilize according to the method for the position shake of the embodiment of the present invention, thereby what can combing RE receive has compared with the Ether frame of scale clock shake, make the distance between the frame head of adjacent Ether frame maintain 260.4ns+C, C is the randomized jitter that variance is less than 0.002ppm.After through clock zone conversion process, frame conversion process, can there is for the system output of subsequent treatment CPRI base frame the CPRI base frame of 260.4ns+D length.Clock zone conversion in RE can be converted to ethernet clock CPRI clock, and the frame conversion in RE can, by separating Ether frame, extract the valid data of CPRI base frame wherein, then valid data are consisted of to CPRI base frame.Because the shake that clock zone conversion process is newly brought is very little, the shake D of the CPRI base frame therefore obtaining in RE still can maintain in the randomized jitter that is less than 0.002ppm.Thereby, for the CPRI base frame sending for REC and the CPRI base frame that receives of RE, within clock jitter can being controlled to 0.002ppm, thereby meet the requirement of CPRI standard to clock jitter index, be conducive to the processing of follow-up system.In addition,, because the ethernet clock using in RE and CPRI clock all produce based on local clock, if local clock is high steady clock, ethernet clock and CPRI clock are all high steady clocks.
Next, describe in detail according to the method for the position shake of the embodiment of the present invention with reference to figure 2.
As shown in Figure 2, the method for Fig. 2 comprises:
In S210, will receive data input buffer according to the ethernet clock recovering from receive data, and receive data and comprise the interFrameGap between Ether frame and adjacent Ether frame.
As an example, receiving data can be the above-mentioned Ether frame transmitting by Fast Ethernet; And Ether frame can be for carrying CPRI frame data.
In S220, receive the process of data reading from buffer according to local clock, if the data volume of the reception data of buffer memory exceedes the first thresholding in buffer, in interFrameGap, deduct the invalid data of the first predetermined quantity, if the data volume of the reception data of buffer memory is lower than the second thresholding in buffer, in interFrameGap, insert the invalid data of the second predetermined quantity, obtain from the output data of buffer output, wherein local clock and ethernet clock synchronised.
Wherein, for buffer memory receives the buffer of data, the clock of writing of buffer is ethernet clock, and this clock can recover from receive data, and the clock of reading of buffer is local clock, local clock need to ethernet clock synchronised.By buffer by isolated to Ethernet territory and local clock territory.Buffer can be a memory space of opening up out in memory, is used for carrying out buffer memory to receiving data, and receiving in the input/output procedure of data, helps to realize the correction of clock jitter.
The reception data of buffer buffer memory comprise Ether frame and interFrameGap.In Ether frame, can carry the data under other agreements.For example, can in Ether frame, carry the data under CPRI agreement, transmit CPRI frame data by Ether frame.
According to one embodiment of present invention, local clock can be high steady clock.Like this, local clock has good stability, is conducive to the processing of follow-up system.
By the invalid data in interFrameGap being carried out in S220, many buttons are few to be mended, and can realize the correction to clock jitter.
Below, in conjunction with Fig. 3 specifically describe according to the embodiment of the present invention pass through deduction and data inserting carrys out the flow chart of method that position is shaken.
Receive data under the effect of the ethernet clock recovering constantly in input buffer, and from buffer, constantly read reception data according to local clock.For read position shake the process that receives data from buffer, can carry out the few processing of mending of many buttons to the invalid data in interFrameGap, specific as follows.
In S310, the data volume of the reception data of buffer memory in statistics buffer.
In S320, judge whether the data volume of the reception data of buffer memory in buffer is greater than the first thresholding.
The first thresholding can be the predetermined number of samples Th1 sum that fixed value M and Ether frame comprise.Th1 can be the predetermined number of samples that the Ether frame of known length in the ideal case comprises, and for example, in CPRI system, Th1 can be the frequency that the Ether frame that is packaged with CPRI data is multiplied by ethernet clock.Fixed value M can equal Th1, and now the first thresholding is 2Th1.In the time that the data of buffer memory in buffer exceed the first thresholding, illustrate that the speed of writing buffer is greater than the speed of reading buffer, need to deduct to interFrameGap the operation of invalid data, therefore advance to S330; In the time that the data of buffer memory in buffer do not exceed the first thresholding, advance to S340.Certainly, the first thresholding can be also other value.The size of buffer is not less than the first thresholding.
In S330, in the time that the data volume in buffer is greater than the first thresholding, the invalid data in deduction interFrameGap, the number of deduction is the first predetermined quantity.
The data of interFrameGap can have set form, for example interFrameGap data can originate in termination (Terminate) symbol, with available free (Idle) symbol, therefore receiving terminal can easily determine that receiving which part in data belongs to interFrameGap afterwards.
The invalid data of deduction can be idle symbol, does not affect like this basic structure of interFrameGap.When each deduction invalid data, can only deduct an invalid data, deduct the invalid data reading in the local clock cycle.Like this, can reach the effect of level and smooth deduction invalid data, avoid the number of deduction too much to introduce extra deviation.
In S340, judge that whether the data volume of reception data of buffer memory in buffer is lower than the second thresholding.
The second thresholding can be the poor of the predetermined number of samples Th1 that comprises of fixed value M and Ether frame.The implication of Th1 is described above.Fixed value M can equal Th1, and now the second thresholding is 0.When the data of buffer memory in buffer are during lower than the first thresholding, illustrate that the speed of writing buffer is less than the speed of reading buffer, in buffer, be not cached with data, need to insert to interFrameGap the operation of invalid data, therefore advance to S350; In the time that the data of buffer memory in buffer do not have lower than the first thresholding, advance to S310.Certainly, the second thresholding can be also other value.
For example, suppose that the first thresholding is M and TT sum, the second thresholding is the poor of M and TT, and supposes that TT is the integral multiple of maximum Ether frame length.If M is larger, TT is larger, the fixed delay of bringing is just larger, considers that time delay is the smaller the better, can be set to an Ether frame length by TT.Because the second thresholding can not be negative, consider that a store M data mean the constant time lag of bringing M clock cycle simultaneously, so wish that M is the smaller the better, can be set to TT by M.Therefore M and TT can be set to an Ether frame length.
In S350, in the time that the data volume in buffer is less than the second thresholding, insert invalid data in interFrameGap, the number of insertion is the second predetermined quantity.
The invalid data inserting can be idle symbol, does not affect like this basic structure of interFrameGap.When each insertion invalid data, can only insert an invalid data, within a local clock cycle, insert an invalid data.Like this, can reach the effect of level and smooth insertion invalid data, avoid the number of inserting to introduce extra deviation when too much.
In addition, the invalid data of interFrameGap being carried out in the few processes of mending of many buttons, local clock need to ethernet clock synchronised.The mode that local clock is synchronizeed with ethernet clock can adopt the mode of existing synchronous two clocks, can also adopt the synchronous method of describing in conjunction with Fig. 4.
In the method that local clock is synchronizeed with ethernet clock shown in Fig. 4, utilize from the output data of buffer output, owing to mending less having carried out many buttons from the process of buffer reading out data, be therefore to have experienced the reception data of many buttons after mending less from the output data of buffer output.
In the method shown in Fig. 4, based on the output data from buffer output, local clock is synchronizeed with ethernet clock.
In S410, output data are carried out to frame synchronization, determine the Ether frame number comprising in output data, obtain the first count value.
Because Ether frame has fixing frame head form, therefore, by output data are carried out to frame synchronization, can determine in output data and comprise how many Ether frames.The counter initial value that records Ether frame number is 0, is often synchronized to an Ether frame frame head, and the counting of counter adds 1.In this article, the count value recording in this counter is called to the first count value, represents with sum1.
In S420, based on local clock, according to the scheduled time length between adjacent Ether frame frame head, Ether frame number is counted, obtained the second count value.
Due to the time span that can preset between adjacent Ether frame frame head, therefore can be as the criterion with local clock, in the time that this scheduled time length is expired, think through an Ether frame.For example, under the application scenarios shown in Fig. 1, the scheduled time length between adjacent Ether frame frame head is 260.4ns, and the full 260.4ns of the every meter of local clock, thinks through an Ether frame.
Thereby determining that by scheduled time length being carried out to timing the counter initial value that records Ether frame number is also 0 Ether frame number in the situation that, whenever in the full scheduled time length of local clock, just the counting of this counter is added to 1.In this article, the count value recording in this counter is called to the second count value, represents with sum2.
In S430, based on the first count value and the second count value, adjust local clock, with ethernet clock synchronised.
According to embodiments of the invention, can utilize FUZZY ALGORITHMS FOR CONTROL to determine the adjustment amount of local clock, adjust local clock frequency according to this adjustment amount, progressively converge to and make local clock and ethernet clock synchronised.Concrete adjustment process can be in conjunction with the description of carrying out with reference to figure 6.In the example of the adjustment local clock shown in Fig. 6, based on the first count value and described the second count value, utilize FUZZY ALGORITHMS FOR CONTROL, obtain digital signal; After digital signal is converted to analog signal, input the constant temperature oscillator that phase-locked loop (Phase-Locked Loop, PLL) comprises, wherein phase-locked loop generates local clock based on local crystal oscillator.
Next.First describe the block diagram of realizing of method that local clock is synchronizeed with ethernet clock with reference to figure 5, and then describe how to adjust local clock by the object lesson of Fig. 6.
In Fig. 5, the initial value of the second count value sum2 of the first count value sum1 sum counter 2 of counter 1 is 0, and both start counting simultaneously, for example can be from starting to receive first Ether frame, and counter 1 sum counter 2 is counted simultaneously.
From the output data Din incoming frame synchronization module of mending less through too much button of buffer output.In frame synchronization module, Ether frame is carried out to frame synchronization, be often synchronized to an Ether frame, the first count value sum1 of counter 1 is added to 1.
The second count value sum2 of counter 2 carries out timing under the driving of local clock, the scheduled time length between the adjacent Ether frame frame head of every meter full phase, and the second count value sum2 adds 1.For example, in the application scenarios shown in Fig. 1, counter 2 taking the CPRI base frame period as unit, whenever the meter time in full CPRI base frame period, adds 1 by the second count value sum2 under the driving of local clock.
Sum1 and sum2 are compared, result is relatively input to Fuzzy control system, the frequency of local clock is adjusted in the output producing by Fuzzy control system.Fuzzy control system is a kind of control system that adopts FUZZY ALGORITHMS FOR CONTROL, and input variable is larger, and the dynamics of correction is also larger, thereby realizes the Fast Convergent of output variable.
Figure 6 illustrates the object lesson that local clock is synchronizeed with ethernet clock.
As described in reference to figure 5, by obtaining the first count value sum1 to carrying out frame synchronization from the output data Din of buffer output, in scheduled time length, carry out timing by being as the criterion with local clock and obtain the second count value sum2.
With fix computing time computation of Period sum1 and sum2 between difference, obtain Xn, n represents cycle computing time of n.And, Xn is carried out to two-level cache, calculated the relative difference between the counter difference in this cycle and the counter difference in a upper cycle, i.e. Δ X=Xn-Xn-1.If ethernet clock is higher than local clock, Δ X positive growth; If ethernet clock is lower than local clock, Δ X negative growth.
In each cycle computing time, under the enabling of timer, Δ X and Xn are inputted to Fuzzy control system.Fuzzy control system carries out computation of table lookup according to the value of Xn and Δ X, obtains the adjusted value L for adjusting local clock frequency, and this adjusted value L is a digital signal.Can be by the fuzzy control table value of the being adjusted L shown in look-up table 1.
Table 1
If the adjusted value L obtaining is 0, illustrate that local clock and ethernet clock are with frequently.If this adjusted value L is not 0, need this digital signal to send into digital to analog converter (Digital-to-Analog Converter, DAC).Digital signal is converted to analog signal by DAC, constant temperature oscillator (the Oven Controlled Crystal Oscillator that phase-locked loop by this analog signal input based on local crystal oscillator generation local clock comprises, OCXO), thus can adjust the frequency of the local clock that this phase-locked loop generates.
The method of the position shake providing according to the embodiment of the present invention, receive data according to ethernet clock input buffer, and according to the local clock output state of ethernet clock synchronised, utilize the data volume of buffer memory and the relation of thresholding in buffer, the interFrameGap data that receive in data are removed and inserted, thereby can proofread and correct the clock jitter that Ethernet is introduced, make to there is data flow form stably from the output data of buffer output, can reduce thus the impact of clock jitter on follow-up system processing that Ethernet is introduced, clock jitter can be limited in to follow-up system processes in acceptable scope.In addition, due to the clock jitter that can remove from the output data of buffer output, therefore can obtain data flow more stably, be conducive to the follow-up real-time processing to data flow, reduce the required memory space expense of subsequent treatment.
In conjunction with Fig. 7, the block diagram of realizing according to the object lesson of the method for the position shake of the embodiment of the present invention is described below.In this object lesson, not only comprise the stability adjustment member of position shake, also comprise the accuracy adjustment member that local clock is synchronizeed with ethernet clock.
Object lesson shown in Fig. 7 can be arranged in the clock jitter correction module of the application scenarios receiving terminal shown in Fig. 1.In the example shown in Fig. 7, taking REC as transmitting terminal, RE as receiving terminal be example, and REC and the equal proportion stability of RE be better than the clock source of CPRI standard-required, REC and RE can adopt high steady clock.
In RE, can comprise 10GE PHY unit, PLL, XAUI (10GigabitAttachment Unit Interface, 10,000,000,000 ether Attachment Unit Interfaces) unit, buffer, local clock, stability adjustment member and accuracy adjustment member.
10GE PHY unit is the physical layer interface of 10GE Ethernet, except providing data-signal, the clock signal of recovering from network interface card is also provided, and the clock signal of recovering is ethernet clock, and clock reference using this clock as XAUI unit reads data and buffer write clock.
PLL is hardware phase-locked-loop, and the clock recovering from 10GE PHY unit by reference to local clock adjustment reaches the effect of the ethernet clock medium-high frequency component of filtering recovery.
XAUI unit is to be operated in the expansion to XGMII (10Gigabit Media Independent Interface, with 10,000,000,000 interfaces of media independent) that connects physical layer and media access control layer in Ethernet model.Here, XAUI simultaneously need to be from the clock signal of PLL and from the data-signal of 10GE PHY unit.
Buffer is used for isolating ethernet clock territory and local clock territory, can ensure receive that data do not occur overflowing while passing through different clock-domains or under overflow.Meanwhile, buffer can be used as data access container when many buttons are few mends operation, is conducive to realize frequency stability adjustment.
The frequency stability of local clock self is better than index request, can adopt high steady clock as local clock, to avoid introducing larger clock jitter in REC and RE.
The operation of stability adjustment member can be with reference to the description in conjunction with Fig. 3.Be position when shake carrying out stability adjustment, if the data volume of buffer memory exceedes the first thresholding in buffer, from interFrameGap, deduct invalid data; If the data volume of buffer memory is lower than the second thresholding in buffer, in interFrameGap, insert invalid data.
Accuracy adjustment member can comprise rolling counters forward module and Fuzzy control system, and the operation of accuracy adjustment member can be with reference to the description of carrying out in conjunction with Fig. 5 and Fig. 6.In the time carrying out accuracy adjustment and local clock synchronizeed with ethernet clock, can count to get respectively the first count value and the second count value by two counters, the first count value obtains by frame synchronization, and the second count value is by obtaining with local clock timing.Utilize FUZZY ALGORITHMS FOR CONTROL to obtain frequency adjusted signal to two count values, frequency adjusted signal is quantified as to digital signal and sends into DAC (as shown in Figure 6), the analog signal of DAC output is inputted the frequency of the OCXO of the PLL that generates local clock again and is adjusted port, realizes the adjustment of local clock.
Stability adjustment member and accuracy adjustment member blocked operation, the local clock after accuracy adjustment continues to read reception data from buffer as the clock of reading of buffer, and in the process reading, carry out many buttons and mend less the clock jitter of introducing to proofread and correct Ethernet, and the data of detaining after few benefit continue to help to carry out the accuracy adjustment of local clock more as the input data of accuracy adjustment.
In addition, being admitted to subsequent treatment system from the output data of buffer output processes.For example, under the application scenarios of Fig. 1, owing to having proofreaied and correct clock jitter, there is interFrameGap stably from the Ether frame of buffer output, through operations such as decapsulations, can obtain CPRI base frame stably and supply subsequent treatment.Because the subsequent treatment that the Ether frame of buffer output is carried out is same as the prior art, therefore, for easy, do not repeat them here.
Above, described according to the method for the position shake of the embodiment of the present invention.In conjunction with Fig. 8 and Fig. 9, the device for position shake according to the embodiment of the present invention is described below.
Fig. 8 is according to the structured flowchart of the device 800 for position shake of the embodiment of the present invention.
Device 800 comprises clock recovery module 810, buffer 820, local clock 830 and shake correction module 840.Device 800 can be arranged in receiving device, and device 800 receives data from Ethernet, and will send into the subsequent treatment module such as decapsulation from the Ether frame of buffer output.Clock recovery module 810 can be network interface card, can from receive data, recover clock.Shake correction module 840 can be processor, the output data of buffer is carried out to few benefit of many buttons and operate.
Wherein, clock recovery module 810 can be used for recovering ethernet clock from receive data, receives data and comprises the interFrameGap between Ether frame and adjacent Ether frame.Buffer 820 can be used for buffer memory according to the reception data of ethernet clock input.Local clock 830 can be used for providing clock frequency for read reception data from buffer 820.Shake correction module 840 is used according to local clock and reads the process that receives data from buffer 820, if the data volume of the reception data of buffer memory exceedes the first thresholding in buffer 820, in interFrameGap, deduct the invalid data of the first predetermined quantity, or, if the data volume of the reception data of buffer memory is lower than the second thresholding in buffer 820, in interFrameGap, insert the invalid data of the second predetermined quantity, obtain the output data of exporting from buffer 820, wherein local clock and ethernet clock synchronised.
Above-mentioned and other operation of clock recovery module 810, buffer 820, local clock 830 and shake correction module 840 and/or function can, with reference to the corresponding description in the method for above-mentioned Fig. 2, for fear of repetition, not repeat them here.
The device for position shake providing according to the embodiment of the present invention, by receiving data according to ethernet clock input buffer, and according to the local clock output state of ethernet clock synchronised, , can utilize the data volume of buffer memory and the relation of thresholding in buffer, the interFrameGap data that receive in data are removed and inserted, thereby can proofread and correct the clock jitter that Ethernet is introduced, make to there is data flow form stably from the output data of buffer output, can reduce thus the impact of clock jitter on follow-up system processing that Ethernet is introduced, thereby clock jitter can be limited in to follow-up system processes in acceptable scope.
Fig. 9 is according to the structured flowchart of the device 900 for position shake of the embodiment of the present invention.
Clock recovery module 910, buffer 920, local clock 930 and the shake correction module 940 of device 900 are basic identical with clock recovery module 810, buffer 820, local clock 830 and the shake correction module 840 of device 800.
According to one embodiment of present invention, device 900 can also comprise synchronization module 950.Synchronization module 950 can be used for, based on output data, local clock being synchronizeed with ethernet clock.
For example, synchronization module 950 can comprise the first counter unit 952, the second counter unit 954 and adjustment unit 956.The first counter unit 952 can be used for output data to carry out frame synchronization, determines the Ether frame number comprising in output data, obtains the first count value.The second counter unit 952 can be used for based on local clock, according to the scheduled time length between adjacent Ether frame frame head, Ether frame number is counted, and obtains the second count value.Adjustment unit 956 can be used for based on the first count value and the second count value, adjust local clock, with ethernet clock synchronised.
According to one embodiment of present invention, adjustment unit 956 can comprise computation subunit 956-1, digital to analog converter 956-2 and phase-locked loop 956-3.Computation subunit 956-1 can be used for, based on the first count value and the second count value, utilizing FUZZY ALGORITHMS FOR CONTROL, obtains digital signal.Digital to analog converter 956-2 can be used for digital signal to be converted to analog signal, and analog signal is inputted to the constant temperature oscillator that phase-locked loop comprises.Phase-locked loop 956-3 can be used for generating local clock based on local crystal oscillator.
According to one embodiment of present invention, local clock 930 can be high steady clock.
According to one embodiment of present invention, the first thresholding can be the predetermined number of samples sum that fixed value and Ether frame comprise, and the second thresholding can be the poor of the predetermined number of samples that comprises of fixed value and Ether frame.
According to one embodiment of present invention, the first predetermined quantity is 1, and the second predetermined quantity is 1.
Above-mentioned and other operation and/or the function of the first counter unit 952, the second counter unit 954, adjustment unit 956, computation subunit 956-1, digital to analog converter 956-2 and phase-locked loop 956-3 can be with reference to the corresponding descriptions in above-mentioned Fig. 2 to Fig. 6, for fear of repetition, do not repeat them here.
The device for position shake providing according to the embodiment of the present invention, by the invalid data of interFrameGap is carried out, many buttons are few to be mended, can effectively correct the clock jitter that Ethernet is introduced, thereby can obtain data flow more stably, be conducive to the follow-up real-time processing to data flow, reduce the required memory space expense of subsequent treatment.
Those skilled in the art can recognize, in conjunction with the various method steps of describing in embodiment disclosed herein and unit, can realize with electronic hardware, computer software or the combination of the two, for the interchangeability of hardware and software is clearly described, step and the composition of each embodiment described according to function in the above description in general manner.These functions are carried out with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Those skilled in the art can realize described function with distinct methods to each specific application, but this realization should not thought and exceeds scope of the present invention.
The software program that the method step of describing in conjunction with embodiment disclosed herein can be carried out with hardware, processor or the combination of the two are implemented.Software program can be placed in the storage medium of any other form known in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
Although illustrated and described some embodiments of the present invention, it should be appreciated by those skilled in the art that without departing from the principles and spirit of the present invention, can carry out various amendments to these embodiment, such amendment should fall within the scope of the present invention.
Claims (10)
1. a method for position shake, is characterized in that, comprising:
According to the ethernet clock recovering from receive data, by described reception data input buffer, described reception data comprise the interFrameGap between Ether frame and adjacent Ether frame;
Reading the process of described reception data from described buffer according to local clock, if the data volume of the reception data of buffer memory exceedes the first thresholding in described buffer, in interFrameGap, deduct the invalid data of the first predetermined quantity, or, if the data volume of the reception data of buffer memory is lower than the second thresholding in described buffer, in interFrameGap, insert the invalid data of the second predetermined quantity, obtain from the output data of described buffer output, wherein said local clock and described ethernet clock synchronised;
Wherein, described local clock and described ethernet clock synchronised comprise: based on described output data, described local clock is synchronizeed with described ethernet clock;
Described based on described output data, described local clock is synchronizeed with described ethernet clock, comprising:
Described output data are carried out to frame synchronization, determine the Ether frame number comprising in described output data, obtain the first count value;
Based on described local clock, according to the scheduled time length between adjacent Ether frame frame head, Ether frame number is counted, obtain the second count value;
Based on described the first count value and described the second count value, adjust described local clock, with described ethernet clock synchronised.
2. method according to claim 1, is characterized in that, described based on described the first count value and described the second count value, adjust described local clock and comprise:
Based on described the first count value and described the second count value, utilize FUZZY ALGORITHMS FOR CONTROL, obtain digital signal;
After described digital signal is converted to analog signal, input the constant temperature oscillator that phase-locked loop comprises, wherein said phase-locked loop generates described local clock based on local crystal oscillator.
3. method according to claim 1 and 2, is characterized in that, described the first thresholding is the predetermined number of samples sum that fixed value and Ether frame comprise, and described the second thresholding is the poor of the predetermined number of samples that comprises of described fixed value and described Ether frame.
4. method according to claim 3, is characterized in that, described fixed value is the predetermined number of samples that described Ether frame comprises.
5. method according to claim 1 and 2, is characterized in that, described the first predetermined quantity is 1, and described the second predetermined quantity is 1.
6. for a device for position shake, it is characterized in that, comprising:
Clock recovery module, for recovering ethernet clock from receiving data, described reception data comprise the interFrameGap between Ether frame and adjacent Ether frame;
Buffer, the reception data of inputting according to described ethernet clock for buffer memory;
Local clock, is used to and reads described reception data from described buffer clock frequency is provided;
Shake correction module, be used in the process that reads described reception data according to described local clock from described buffer, if the data volume of the reception data of buffer memory exceedes the first thresholding in described buffer, in interFrameGap, deduct the invalid data of the first predetermined quantity, or, if the data volume of the reception data of buffer memory is lower than the second thresholding in described buffer, in interFrameGap, insert the invalid data of the second predetermined quantity, obtain from the output data of described buffer output, wherein said local clock and described ethernet clock synchronised;
Also comprise: synchronization module, for based on described output data, described local clock is synchronizeed with described ethernet clock;
Wherein, described synchronization module comprises:
The first counter unit, for described output data are carried out to frame synchronization, determines the Ether frame number comprising in described output data, obtains the first count value;
The second counter unit, for based on described local clock, counts Ether frame number according to the scheduled time length between adjacent Ether frame frame head, obtains the second count value;
Adjustment unit, for based on described the first count value and described the second count value, adjusts described local clock, with described ethernet clock synchronised.
7. device according to claim 6, is characterized in that, described adjustment unit comprises:
Computation subunit, for based on described the first count value and described the second count value, utilizes FUZZY ALGORITHMS FOR CONTROL, obtains digital signal;
Digital to analog converter, for described digital signal is converted to analog signal, and the constant temperature oscillator that described analog signal input phase-locked loop is comprised;
Described phase-locked loop, for generating described local clock based on local crystal oscillator.
8. according to the device described in claim 6 or 7, it is characterized in that, described the first thresholding is the predetermined number of samples sum that fixed value and Ether frame comprise, and described the second thresholding is the poor of the predetermined number of samples that comprises of described fixed value and described Ether frame.
9. device according to claim 8, is characterized in that, described fixed value is the predetermined number of samples that described Ether frame comprises.
10. according to the device described in claim 6 or 7, it is characterized in that, described the first predetermined quantity is 1, and described the second predetermined quantity is 1.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2011/077383 WO2012106910A1 (en) | 2011-07-20 | 2011-07-20 | Method and device for correcting clock jitter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102301639A CN102301639A (en) | 2011-12-28 |
| CN102301639B true CN102301639B (en) | 2014-07-30 |
Family
ID=45360531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201180001223.4A Active CN102301639B (en) | 2011-07-20 | 2011-07-20 | Method and device for correcting clock jitter |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102301639B (en) |
| WO (1) | WO2012106910A1 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103684736A (en) * | 2013-11-21 | 2014-03-26 | 国网上海市电力公司 | Clock synchronization method for high-speed communication |
| CN105284184B (en) * | 2014-05-21 | 2019-06-21 | 华为技术有限公司 | A kind of data transmission method, device and network system |
| CN104393961B (en) * | 2014-12-12 | 2017-05-03 | 成都朗锐芯科技发展有限公司 | Received packet sorting and invalid packet processing method |
| CN104410483B (en) * | 2014-12-12 | 2017-06-09 | 成都朗锐芯科技发展有限公司 | One kind receives packet sequencing and invalid bag processing system |
| CN109412740B (en) * | 2017-08-16 | 2020-09-29 | 深圳市中兴微电子技术有限公司 | Method and device for processing delay jitter |
| CN108882287B (en) * | 2018-06-07 | 2021-08-17 | 烽火通信科技股份有限公司 | Method and system for controlling time delay jitter of CPRI data transmission |
| CN114205065A (en) * | 2020-09-02 | 2022-03-18 | 深圳市朗强科技有限公司 | Clock frequency synchronization method, device, equipment and computer storage medium |
| CN112462717B (en) * | 2020-12-03 | 2021-11-30 | 摩通传动与控制(深圳)有限公司 | High-precision multi-axis clock synchronization method based on EtherCAT |
| CN112736901B (en) * | 2020-12-23 | 2022-11-01 | 国网湖南省电力有限公司 | Synchronization method and system for multi-source asynchronous sampling mixed data in distribution network |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1581845A (en) * | 2003-08-01 | 2005-02-16 | 华为技术有限公司 | Apparatus and method for clock recovery for time division multiplexing business |
| CN1852087A (en) * | 2005-12-21 | 2006-10-25 | 华为技术有限公司 | Clock synchronizing method in bag-exchanging network and realizing apparatus tehrefor |
| CN101141351A (en) * | 2007-08-09 | 2008-03-12 | 中兴通讯股份有限公司 | Method of settling frequency offset |
| CN101820324A (en) * | 2010-04-30 | 2010-09-01 | 中兴通讯股份有限公司 | Synchronous transmission method and system for asynchronous data |
| CN102082653A (en) * | 2009-11-26 | 2011-06-01 | 中兴通讯股份有限公司 | Method, system and device for clock synchronization |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7095737B2 (en) * | 2002-02-28 | 2006-08-22 | Sun Microsystems, Inc. | Variable length inter-packet gap |
| CN101364863B (en) * | 2008-09-27 | 2011-11-02 | 华为技术有限公司 | Time synchronizing method, apparatus and system for master, slave time clock side in synchronous network |
-
2011
- 2011-07-20 WO PCT/CN2011/077383 patent/WO2012106910A1/en active Application Filing
- 2011-07-20 CN CN201180001223.4A patent/CN102301639B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1581845A (en) * | 2003-08-01 | 2005-02-16 | 华为技术有限公司 | Apparatus and method for clock recovery for time division multiplexing business |
| CN1852087A (en) * | 2005-12-21 | 2006-10-25 | 华为技术有限公司 | Clock synchronizing method in bag-exchanging network and realizing apparatus tehrefor |
| CN101141351A (en) * | 2007-08-09 | 2008-03-12 | 中兴通讯股份有限公司 | Method of settling frequency offset |
| CN102082653A (en) * | 2009-11-26 | 2011-06-01 | 中兴通讯股份有限公司 | Method, system and device for clock synchronization |
| CN101820324A (en) * | 2010-04-30 | 2010-09-01 | 中兴通讯股份有限公司 | Synchronous transmission method and system for asynchronous data |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012106910A1 (en) | 2012-08-16 |
| CN102301639A (en) | 2011-12-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102301639B (en) | Method and device for correcting clock jitter | |
| US20200267669A1 (en) | Methods and apparatus for synchronization of media playback within a wireless network | |
| CN101960770B (en) | Clock synchronization system, node, clock synchronization method | |
| CN101252429B (en) | Method for enhancing clock synchronization accuracy in distributed network system | |
| CN103532652B (en) | A kind of time synchronism apparatus and method | |
| US20060020843A1 (en) | Technique to create link determinism | |
| EP3223431B1 (en) | Adjustment of clock signals regenerated from a data stream | |
| CN105743598B (en) | A kind of Industrial Ethernet clock synchronizing method and system | |
| CN103650406A (en) | Apparatus for synchronizing a data handover between a first clock domain and a second clock domain | |
| US9402092B2 (en) | Communication device, communication program, and communication method | |
| WO2010119326A1 (en) | Embedded clock recovery | |
| CN108880723A (en) | A kind of method and apparatus that clock is synchronous | |
| KR101526025B1 (en) | Frequency synchronization | |
| US8913190B2 (en) | Method and apparatus for regenerating a pixel clock signal | |
| CN101399653B (en) | Time clock synchronization implementation method | |
| CN110768664B (en) | Data sampling method and device | |
| CN111092713B (en) | Clock synchronization device and clock synchronization method | |
| CN107636627B (en) | Time synchronization device, time synchronization system, and time synchronization method | |
| CN106341127A (en) | Video clock recovery method and apparatus thereof | |
| TW201703439A (en) | Glitch-free digitally controlled oscillator code update | |
| JP2011066621A (en) | Data transfer apparatus | |
| CN203722758U (en) | Synchronizer for distributed video system | |
| CN111181679A (en) | IEEE 1588-based high-speed streaming media bus accurate clock synchronization system | |
| US8068177B2 (en) | Methods and devices for signal synchronization | |
| JP2013034087A (en) | Serial communication interface circuit and parallel-serial conversion circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |