CN103684736A - Clock synchronization method for high-speed communication - Google Patents
Clock synchronization method for high-speed communication Download PDFInfo
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- CN103684736A CN103684736A CN201310594634.XA CN201310594634A CN103684736A CN 103684736 A CN103684736 A CN 103684736A CN 201310594634 A CN201310594634 A CN 201310594634A CN 103684736 A CN103684736 A CN 103684736A
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Abstract
The invention relates to a clock synchronization method for high-speed communication, and relates to digital signal transmission method and equipment, in particular to a method of clock synchronization for receiving and transmitting ends in high-speed communication. The method includes the steps: synchronous clocks are set for the transmitting end and the receiving end, and the transmitting end transmits sync signals to the receiving end; the receiving end corrects local clock signals and establishes sync; according to the received normal communication signals, the receiving end calculates the period of each signal and synchronously corrects in real time to maintain sync; when long zero and long 1 data signals occur, the transmitting end adds the sync signals to allow the receiving end to continue extracting the sync signals and calculate the periods of signals in real time; shortest cold length with step-out possibility is calculated and experimentally verified, and when data under transmission exceeds the shortest code length, the sync correction signals are inserted to allow the receiving end to correct sync accumulative errors in time. Through the application of the method, the problem that communication fails to failure of signal clock extraction or interrupt of clock extraction can be solved, and data communication efficiency is improved.
Description
Technical field
The present invention relates to the method and apparatus for transmission of digital signals, relate in particular to the method for receiving terminal and the transmitting terminal clock synchronous of high-speed communication.
Background technology
High speed data transfer needs considering efficiency, conventionally without asynchronous transmission, because every eight data bit of asynchronous transmission must be inserted a start bit and a stop bits, sometimes may also to there is check digit, actual efficiency is generally the highest is 80%, if forward error correction, except increasing error correcting code, error correcting code also will have check digit, efficiency is lower so, therefore conventionally adopt synchronous transmission, because synchronous transmission is without start bit, position of rest and check digit, but synchronous transmission needs sending and receiving end signal strictly synchronous, in the time of so just must transmitting beginning, add a segment sync code, make the sending and receiving end can be strictly synchronous, when data volume trend is infinitely great, efficiency of transmission also tends to 100%, but while applying to wireless transmission, because the path of signal is different, time delay between adjacent signals is also not quite similar, when transmission reaches some, the accumulated error of time delay is stacked into after certain value, can cause the sync fail of transmitting-receiving two-end.
Chinese invention patent application " a kind of synchronization transfer method of asynchronous data and system " (application for a patent for invention number: 201010165369.X publication number: CN101820324A) disclose a kind of synchronization transfer method and system of asynchronous data, comprised that transmitting terminal is encapsulated into synchrodata frame by asynchronous data and is transferred to receiving terminal; This receiving terminal receiving isochronous data carries out decapsulation, this asynchronous data obtaining is write to the buffering area of this receiving terminal, utilizes reading this asynchronous data of Clockreading and outputing to outside receiving system of an asynchronous data; This receiving terminal also utilizes the data depth information of buffering area to adjust the frequency that this reads clock, when the data depth in this buffering area increases, increases the frequency that this reads clock, and when this buffering area is sky, output represents idle data.Although this invention has solved the slip problem of continuous synchronization transmitting asynchronous data,, when high speed communication of signals cannot be extracted signal clock because there is long distance of zero mark one this class, or when extracting clock and interrupting, the accumulated error of time delay still can cause communication failure.
Summary of the invention
The method that the object of this invention is to provide clock synchronous in a kind of high-speed communication, by delay calibration is carried out in local oscillations source, solves because extracting signal clock or extract the problem that clock interrupts causing communication failure.
The present invention solves the problems of the technologies described above adopted technical scheme:
A method for clock synchronous in high-speed communication, for the receiving terminal of high-speed communication and the clock synchronous of transmitting terminal, is characterized in that comprising the following steps:
S100: transmitting terminal arranges synchronised clock, when communication initial, sends synchronizing signal to receiving terminal by transmitting terminal;
S200: the local clock of same frequency is set at receiving terminal, and receiving terminal, according to the synchronizing signal receiving, is revised local clock signal, sets up synchronous;
S300: the normal communications signal that receiving terminal basis is received, the cycle of calculating each signal, synchronously revise in real time, remain synchronous;
S400: when long " 0 " and long " 1 " appears in data-signal, transmitting terminal adds synchronizing signal in growing " 0 " and long " 1 ", makes receiving terminal can continue to extract synchronizing signal, calculates in real time the correct signal period;
S500: calculate and verification experimental verification may to produce the short code of step-out long, when the data of transmission surpass short code when long, insertion synchronization correction signal, makes receiving terminal can revise in time synchronous accumulated error.
A kind of preferably technical scheme of the method for clock synchronous in high-speed communication of the present invention, characterized by further comprising following steps:
S600: add the redundant code for forward error correction in the frame structure of data communication, described synchronization correction signal is inserted in redundant code, receiving terminal can, in executing data error correction, be extracted for revising the clock sync signal of local clock.
A kind of better technical scheme of the method for clock synchronous in high-speed communication of the present invention, characterized by further comprising following steps:
S700: set up breakpoint memory and retransmission mechanism at transmitting terminal and receiving terminal, when abnormal step-out occurs in data communication, transmitting terminal records step-out point, and resends synchronizing signal to receiving terminal according to the step-out point of record, the Frame after the step-out point that retransfers.
The invention has the beneficial effects as follows:
1. the method for clock synchronous in high-speed communication of the present invention, can, by delay calibration is carried out in local oscillations source, solve because extracting signal clock or extract the problem that clock interrupts causing communication failure.
2. the method for clock synchronous in high-speed communication of the present invention, by synchronization correction signal is inserted in redundant code, is used forward error correction and the clock synchronous function of the same section of complete paired data of redundant code, can further improve the efficiency of data communication.
Accompanying drawing explanation
Fig. 1 is the control flow chart of the method for clock synchronous in high-speed communication of the present invention;
Fig. 2 is the electrical schematic diagram that uses the datel circuit of clock synchronizing method in high-speed communication of the present invention.
In figure, 1-monolithic synchronous/asynchronous transducer, 2-modulator-demodulator, 3-local oscillations source module, the input of TD_in-asynchronous data, the output of RD_out-asynchronous data, STD_C_out-synchrodata input clock signal, the input of STD_in-synchrodata, SRD_C_out-synchrodata clock signal, the output of SRD_out-synchrodata.
Embodiment
In order to understand better technique scheme of the present invention, below in conjunction with drawings and Examples, describe in detail further.
In high-speed communication of the present invention, the control flow of the method for clock synchronous as shown in Figure 1, for the receiving terminal of high-speed communication and the clock synchronous of transmitting terminal, comprises the following steps:
S100: transmitting terminal arranges synchronised clock, when communication initial, sends synchronizing signal to receiving terminal by transmitting terminal;
S200: the local clock of same frequency is set at receiving terminal, and receiving terminal, according to the synchronizing signal receiving, is revised local clock signal, sets up synchronous;
S300: the normal communications signal that receiving terminal basis is received, the cycle of calculating each signal, synchronously revise in real time, remain synchronous;
S400: when long " 0 " and long " 1 " appears in data-signal, transmitting terminal adds synchronizing signal in growing " 0 " and long " 1 ", makes receiving terminal can continue to extract synchronizing signal, calculates in real time the correct signal period;
S500: calculate and verification experimental verification may to produce the short code of step-out long, when the data of transmission surpass short code when long, insertion synchronization correction signal, makes receiving terminal can revise in time synchronous accumulated error.
Asynchronous and the synchronous difference of data communication is synchronously to take oscillation source as basis, and according to each cycle transmission data, and the effective start bit of asynchronous basis is identified.If the speed of synchronous serial can not fit like a glove with the speed of asynchronous serial, the result finally causing is the error code of transfer of data.In high-speed communication of the present invention, the method for clock synchronous can avoid high speed communication of signals cannot extract signal clock or extract the communication failure occurring when clock interrupts because there is long distance of zero mark one this class.In high-speed communication of the present invention, the method for clock synchronous can adopt multiple circuit to realize, its basic circuit comprises: local oscillations source, signal sampling clock extracting circuit, comparison circuit, local oscillator correction circuit, wherein, local oscillations source provides reference clock, signal sampling provides signal clock, and comparison circuit calculates the difference of two kinds of clocks, according to this difference, by local oscillator correction circuit, delay calibration is carried out in local oscillations source.The clock source of transmitting terminal and the clock source of receiving terminal (local oscillations source) can adopt crystal oscillator, signal sampling Clock Extraction module is AD sample circuit, and clock comparison, correcting module are conventionally carried out control method of the present invention by single-chip microcomputer by program control and realized.
Fig. 2 is an embodiment who uses the datel circuit of clock synchronizing method in high-speed communication of the present invention, in figure, adopt FX469 modulator-demodulator 2 to work in synchronous serial mode, external interface is asynchronous serial port, by the synchronous/asynchronous of MAS7838 monolithic synchronous/asynchronous transducer 1 executive communication data, changes.Local oscillations source module 3 is comprised of crystal oscillator and 4 binary counter HC93, is connected to the TMG input of monolithic synchronous/asynchronous transducer 1.
In the embodiment shown in Figure 2, the clock when STD_C_out of transmitting terminal provides a local signal as synchronous transmission, MAS7838 monolithic synchronous/asynchronous transducer 1 is according to this clock, data on asynchronous serial port are removed after start bit, check digit, position of rest, by STD_in, be sent to FX469 modulator-demodulator 2, carry out synchronized transmission, this process can be understood as DA conversion.Before authentic data sends, FX469 modulator-demodulator 2 first sends one section of signal that comprises STD_C_out information as receiving terminal clock alignment benchmark.
The FX469 modulator-demodulator 2 of receiving terminal carries out AD conversion by the synchronizing signal receiving, and extracts the clock reference signal of transmitting terminal; Clock comparison, correcting module (not shown) are according to the clock reference signal of transmitting terminal, calibration local side clock, make it consistent with transmitting terminal height, and using this clock as receiving synchronizing signal SRD_C_out, offer MAS7838 monolithic synchronous/asynchronous transducer 1, MSA7838 receives data-signal SRD_out by turn according to this clock, then according to the requirement of asynchronous communication, carries out assembledly, adds start bit, check digit, position of rest.
In the embodiment of the method for clock synchronous, further comprising the steps of in the high-speed communication of the present invention shown in Fig. 1:
S600: add the redundant code for forward error correction in the frame structure of data communication, described synchronization correction signal inserts in redundant code, same section of redundant code be the forward error correction function of complete paired data both, also take into account the use that allows receiving terminal extract synchronised clock, receiving terminal can, in executing data error correction, be extracted for revising the clock sync signal of local clock.
According to a kind of improved embodiment of the method for clock synchronous in high-speed communication of the present invention, data communication also comprises breakpoint transmission mechanism, and its control procedure comprises the following steps:
S700: set up breakpoint memory and retransmission mechanism at transmitting terminal and receiving terminal, when abnormal step-out occurs in data communication, transmitting terminal records step-out point, and resends synchronizing signal to receiving terminal according to the step-out point of record, the Frame after the step-out point that retransfers.
Those of ordinary skill in the art will be appreciated that; above embodiment is only for technical scheme of the present invention is described; and be not used as limitation of the invention; any variation of the above embodiment being done based on connotation of the present invention, modification, all will drop in the protection range of claim of the present invention.
Claims (3)
1. a method for clock synchronous in high-speed communication, for the receiving terminal of high-speed communication and the clock synchronous of transmitting terminal, is characterized in that comprising the following steps:
S100: transmitting terminal arranges synchronised clock, when communication initial, sends synchronizing signal to receiving terminal by transmitting terminal;
S200: the local clock of same frequency is set at receiving terminal, and receiving terminal, according to the synchronizing signal receiving, is revised local clock signal, sets up synchronous;
S300: the normal communications signal that receiving terminal basis is received, the cycle of calculating each signal, synchronously revise in real time, remain synchronous;
S400: when long " 0 " and long " 1 " appears in data-signal, transmitting terminal adds synchronizing signal in growing " 0 " and long " 1 ", makes receiving terminal can continue to extract synchronizing signal, calculates in real time the correct signal period;
S500: calculate and verification experimental verification may to produce the short code of step-out long, when the data of transmission surpass short code when long, insertion synchronization correction signal, makes receiving terminal can revise in time synchronous accumulated error.
2. the method for clock synchronous in high-speed communication according to claim 1, characterized by further comprising following steps:
S600: add the redundant code for forward error correction in the frame structure of data communication, described synchronization correction signal is inserted in redundant code, receiving terminal can, in executing data error correction, be extracted for revising the clock sync signal of local clock.
3. the method for clock synchronous in high-speed communication according to claim 1 and 2, characterized by further comprising following steps:
S700: set up breakpoint memory and retransmission mechanism at transmitting terminal and receiving terminal, when abnormal step-out occurs in data communication, transmitting terminal records step-out point, and resends synchronizing signal to receiving terminal according to the step-out point of record, the Frame after the step-out point that retransfers.
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| WO2017000713A1 (en) * | 2015-06-29 | 2017-01-05 | 中兴通讯股份有限公司 | Method and device for synchronizing clock time transport modes in optical transport network |
| CN109286483A (en) * | 2018-11-13 | 2019-01-29 | 珠海格力电器股份有限公司 | A kind of method and apparatus acquiring data |
| CN112291039A (en) * | 2020-10-15 | 2021-01-29 | 天津大学 | Data coding transmission method based on channel signal period |
| CN113824545A (en) * | 2021-11-22 | 2021-12-21 | 深圳市思远半导体有限公司 | Asynchronous communication method, device and related equipment |
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Application publication date: 20140326 |