CN103440171B - A kind of implementation method of componentization hardware real-time operation system - Google Patents
A kind of implementation method of componentization hardware real-time operation system Download PDFInfo
- Publication number
- CN103440171B CN103440171B CN201310396603.3A CN201310396603A CN103440171B CN 103440171 B CN103440171 B CN 103440171B CN 201310396603 A CN201310396603 A CN 201310396603A CN 103440171 B CN103440171 B CN 103440171B
- Authority
- CN
- China
- Prior art keywords
- task
- processor
- command
- hardware
- manager
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The invention discloses the implementation method of a kind of componentization hardware real-time operation system, first real time operating system is divided into hardware-core and software interface two parts by the method；Then in hardware-core, in the way of componentization, realize the task manager of the Realtime Operating System Nucleus, interrupt manager, counting semaphore manager, mutex amount manager, message queue manager, hardware-core is with register interface module and software communication, with controller lock, each manager is synchronized, between manager, use the intermodule command interface bus communication of standard；Finally realize between processor message queue manager between counting semaphore manager and processor, it is achieved Multiprocessor operation system hardware-core.The present invention uses componentization mode to realize hardware real-time operation system kernel, obtains bigger raising, make hardware real-time operation system reach the motility of software on system Scalability with extensibility.
Description
Technical field
The invention belongs to real time operating system Hardware and realize field, relate to the implementation method of a kind of componentization hardware real-time operation system.
Background technology
Development along with embedded system industry, real time operating system RTOS(RealTimeOperatingSystem) all it is widely applied in fields such as Industry Control, medical apparatus and instruments, Aero-Space, automotive electronics, household electrical appliance, and occupied larger share in embedded systems.Real time operating system refers to respond external trigger in time within the time determined and perform a type operating system of corresponding task.Why RTOS can be widely used in computer Embedded Application, and being because RTOS can become multitask by Task-decomposing, simplifies the design of application systems software.RTOS makes the real-time of control system be ensured, good multitask design, can improve reliability and the safety of embedded system.
Deepening constantly and refining along with application, performance and the stability requirement of RTOS are also gradually being strengthened by the application scenarios of various complexity.General desktop operating system has more comprehensively consideration in terms of reliability, to meet complex application context, avoids deadlock, malicious attack etc..But majority RTOS is in order to ensure under the performance requirements such as real-time, the reliability of system is carried out simplification process, the author of application program is proposed higher technology requirement, thus leaves potential safety hazard.Traditional RTOS cannot meet higher real-time and reliability requirement simultaneously.Use software-hardware synergism means, RTOS functional module is carried out cure process and function remodeling, is a kind of effective means taking into account system real time and reliability.This is also one of the focus of current RTOS research.
The nineties in 20th century, the concept of real time operating system Hardware is abroad proposed, uses hardware logic electric circuit or sequence circuit to realize the functions such as the task scheduling in tradition real time operating system, interrupt processing, resource management.The achievement in research of aftershaping start to occur.Within 2003, PaulKohout is by real-time task manager hardware, carries out the scheduling based on priority and timeslice.2008, the Cui Jianhua of School of Information Technology of PLA, frame structure based on " ppu+FPGA ", devise the hardware RTOS supporting the functions such as task scheduling, interrupt management, timer management.2011, the AndersBlaabjergLange of Syddansk Uni has designed and Implemented the most complete hardware real-time operation system HartOS, HartOS includes task manager, interrupt manager, explorer, and uses APIProcessor to realize the communication between CPU and manager.2012, the paddy duckweed duckweed of domestic Harbin University of Science and Technology used genetic algorithm NSGA-II as hardware/software partitioning algorithms, needs UCOSII real time operating system is carried out fractional hardware according to application, obtained balance between hardware resource consumption and performance boost.
For application angle, the evaluation of a real time operating system is embodied in five aspects: (1) systematic function, i.e. system real time and complete the speed of every kernel operation；(2) software memory space and amount of hardware resources shared by system resources consumption, i.e. system；(3) system reliability, i.e. system error ability and abnormal restoring ability；(4) system expandability and Scalability, i.e. system need to carry out the ability of cutting or expansion according to application；(5) system reusability, i.e. system are applicable to the ability of different running environment.But existing major part hardware real-time operation system, although have a respective advantage, but all existing defects in terms of one or more evaluation.Or because too much bus communication causes performance to reduce, or it is difficult to cutting and extension because the system degree of coupling is too high, or can only realize on specific hardware, or software manipulation check deficiency is existed the defect in reliability, or functionally there is bigger gap with software real time operating system.
Summary of the invention
Present invention aims to the deficiencies in the prior art, it is provided that the implementation method of a kind of componentization hardware real-time operation system.
The technical solution adopted for the present invention to solve the technical problems is: the implementation method of a kind of componentization hardware real-time operation system, and the method comprises the following steps:
(1) real time operating system is divided into hardware-core and software interface two parts, and determines software and hardware communication mode；
(2) in hardware-core, the componentization implementation of each functional module of the Realtime Operating System Nucleus is determined so that it is can adjust the most neatly, cutting and extension；
(3) in hardware-core, it is achieved hardware task manager；
(4) in hardware-core, it is achieved hardware interrupts manager；
(5) in hardware-core, it is achieved hardware counting semaphore manager；
(6) in hardware-core, it is achieved hardware mutex amount manager；
(7) in hardware-core, it is achieved hardware message queue management device；
(8) by comprising multiple uniprocessor hardware-core, it is achieved the operation system function of multiprocessor；
(9) in multiprocessor hardware kernel, it is achieved counting semaphore manager between processor；
(10) in multiprocessor hardware kernel, it is achieved message queue manager between processor；
(11) complete multiprocessor hardware the Realtime Operating System Nucleus is realized.
The invention have the advantages that:
1, for from systematic function, the present invention is full the Realtime Operating System Nucleus Hardware, at utmost decreases software and hardware communication overhead, improves a lot than the real time operating system of fractional hardware change in performance；
2, from system resources consumption, the present invention uses componentization mode to realize hardware real-time operation system kernel, cutting can be carried out as required and be sized, at utmost reduce unnecessary resource overhead, the memorizer of the Realtime Operating System Nucleus functional module simultaneously, all use FPGA ram in slice to realize, compared with other hardware real-time operation system, at utmost decrease the consumption of hardware logic unit；
3, from system reliability, the present invention uses various ways to ensure system reliability, be included in task manager interpolation watchdog module, in task manager add stack pointer check logic, in mutex amount manager add Deadlock Detection, carry out various status checkout and parameter testing when hardware command performs, to make full use of the reliability of hardware to ensure the reliability of real time operating system；
4, from the system expandability with Scalability, the present invention uses componentization mode to realize hardware real-time operation system kernel, and intermodule is communicated by self-defined bus, and the degree of coupling is the lowest, is suitable for extension and cutting；
5, from system reusability, hardware-core uses hardware logic unit and ram in slice to realize completely, need not special hardware supported, and software and hardware communication mode is encapsulated in outside functional module, can replace neatly, need not special bus support, therefore can reach the highest reusing degree.
6, the present invention achieves same priority task scheduling based on timeslice, task blocking based on the priority queue of all kinds of resource, the Priority Inheritance Protocol of mutex amount dexterously with a small amount of hardware resource, breaches the problem that hardware real-time operation system complexity is low, be difficult to compare favourably with software real time operating system；
7, the present invention uses the hardware real-time operation system that componentization mode realizes, and may be conveniently used multiprocessor and the multi-core processor system supporting that current industry is the most popular, and this is a kind of breakthrough for existing hardware real time operating system.
Accompanying drawing explanation
Accompanying drawing is for providing a further understanding of the present invention, and constitutes a part for description, is provided commonly for explaining the present invention with embodiments of the invention, is not intended that limitation of the present invention.
Fig. 1 is the uniprocessor componentization real time operating system Organization Chart on AlteraFPGA chip.
Fig. 2 is the multiprocessor componentization real time operating system Organization Chart on XilinxFPGA chip.
Detailed description of the invention
Describe the embodiment of this explanation in detail below with reference to drawings and Examples, to the present invention, how application technology means solve technical problem whereby, and the process that realizes reaching technique effect can fully understand and implement according to this.
The present invention, for realizing the hardware real-time operation system of componentization, specifically includes following steps:
1, real time operating system is divided into hardware-core and software interface two parts, and determines software and hardware communication mode.It includes following sub-step:
(1.1) hardware-core being existed as coprocessor or external equipment, when as coprocessor, software and hardware is communicated by the general register of processor, and when as external equipment, software and hardware is communicated by system bus.
(1.2) the Realtime Operating System Nucleus function package is become hardware command, hardware command to include command number, input data, return value, output data by hardware-core.Hardware command is encapsulated as system and calls by software interface further, it is provided that use to application program.
(1.3) in addition to hardware command communicates, hardware-core also provides for two interrupt signals to processor, and one is used for task handover request, and one is used for abnormality processing application；Software interface is responsible for carrying out hardware-core and is sent the process of interruption, when task handover request interrupt signal is brought, carries out task switching, when abnormality processing application interrupt signal arrives, carries out abnormality processing；Abnormality processing application is except software processes, it is also possible to directly trigger processor reset
2, in hardware-core, the componentization implementation of each functional module of the Realtime Operating System Nucleus is determined so that it is can adjust the most neatly, cutting and extension.It includes following sub-step:
(2.1) hardware-core uses register interface module as the interface between software interface and the Realtime Operating System Nucleus functional module.Register interface module, by hardware command incoming for software interface, is converted to the processor command interface communication of the corresponding function module.The processor command interface bus signal of the Realtime Operating System Nucleus functional module is as follows:
Cpu_target [7:0], the functional module address that processor command is corresponding；
Cpu_input_wr, inputs data write signal；
Cpu_input_data [31:0], inputs data, when cpu_input_wr is 1 effectively, and writable most 16 input data；
Cpu_cmd_data [31:0], order numbering；
Cpu_cmd_req, order is initiated request, after input data and order numbering are in place, can be initiated command request；
Cpu_cmd_ack, order complement mark；
Cpu_cmd_ret [7:0], order return value；
Cpu_cmd_output_num [3:0], order output data amount check, be up to 15 output data；
Cpu_output_rd, exports data reading signal；
Cpu_output_data [31:0], Data Data, next output data it is switched to when cpu_output_rd is 1.
(2.2) the Realtime Operating System Nucleus functional module is connected in intermodule command interface bus by the intermodule command interface of standard, and the core functions module assignment of each instantiation has an independent address, to carry out intermodule command communication；In bus, the same time only allows one to have a main equipment and one to initiate order from equipment, main equipment, perform order from equipment.Intermodule command interface bus signals is as follows:
Slave_target [7:0], from device address；
Input_wr, inputs data write signal；
Input_data [31:0], inputs data, when input_wr is 1 effectively, and writable most 16 input data；
Cmd_data [31:0], order numbering；
Cmd_req, order is initiated request, after input data and order numbering are in place, can be initiated command request；
Cmd_ack, order complement mark；
Cmd_ret [7:0], order return value；
Cmd_output_num [3:0], order output data amount check, be up to 15 output data；
Output_rd, exports data reading signal；
Output_data [31:0], Data Data, next output data it is switched to when output_rd is 1.
(2.3) every class real time operating system functional module all includes following sections structure: memorizer, controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface；Wherein, memorizer is mainly realized by the ram in slice of FPGA；Various command interfaces are to communicate with outside for module；All parts action the most under control of the controller in module, controller finite state machine realizes.
(2.4) hardware-core uses a controller lock module to synchronize all real time operating system functional modules, when the request of a processor command, timeslice wake events ticking, asynchronous or task scheduling arrives, request can be sent to controller lock module, the every secondary response of controller lock module one request, the controller of each real time operating system functional module can complete to ask operation accordingly according to controller lock state.
(2.5) every class real time operating system functional module can have several examples, the number of resources in each instantiation module to be configured flexibly as required.There is not master slave relation between functional module, can add neatly, be deleted or modified, only communicated by intermodule command interface bus between functional module, keep the low degree of coupling.In a uniprocessor hardware-core, it is achieved task manager, several interrupt managers, several counting semaphore managers, several mutex amount manager and several message queue manager.
3, in hardware-core, it is achieved hardware task manager.It includes following sub-step:
(3.1) hardware task manager is divided into following submodule: task memory, task controller, clock generator, WatchDog Timer, task dispatcher, processor command interface, intermodule order host device interface, intermodule order are from equipment interface.
(3.2) task memory is realized.Task memory stores the control block message of each task, inherits priority, the actual priority of task, task blocking resource number, task delay time sheet number, task round timeslice number, task stack pointer lower limit, the task stack pointer upper limit, task stack pointer including task status, task original priority, task.In addition, task memory also includes the tree-shaped priority comparator of the actual priority of task based access control, can select the limit priority task bitmap in particular task bitmap；When input is for ready task bitmap, it is output as the ready task bitmap of limit priority, it is achieved task preemption based on priority is dispatched.
(3.3) realizing clock generator, clock generator is arranged according to timeslice size, sends a tick_sig rising edge information every the time of timeslice size, with the delay data of more new task.After the round timeslice of current task is finished, send dispatch request, to trigger same priority task robin scheduling based on timeslice.
(3.4) WatchDog Timer is realized.House dog count value subtracts one at each tick_sig, sends abnormality processing application interrupt signal when reducing to zero, and house dog count value does not enables when being set to zero.
(3.5) task dispatcher is realized.Task dispatcher receives the ready task bitmap of the limit priority of task memory output, and store tasks round bitmap, to realize task preemption based on priority scheduling and same priority task robin scheduling based on timeslice；Task dispatcher output current task number and limit priority ready task number, and task handover request interrupt signal is sent when current task is not limit priority ready task.
(3.6) task controller is realized.The action of remaining submodule in task controller control task manager.It is realized by finite state machine, can complete the incoming order of processor command, other module, task delayed data that task-scheduling operation, tick_sig trigger adjusts operation.
(3.7) task manager realizes following processor command: task creation order, task delete command, task suspension order, task recovery order, task delay command, task time delay mandatum cassatorium, task priority amendment order, task concede processor command, task round timeslice number setting command, task control block querying command, task manager reset command.
(3.8) task manager realizes following intermodule order: select task wake command, task blocking order based on mutex amount, band time-out time task blocking order based on mutex amount, task wake command based on mutex amount in task blocking order, the task blocking order of band time-out time, task wake command, task blocking bitmap.
4, in hardware-core, it is achieved hardware interrupts manager.It includes following sub-step:
(4.1) hardware interrupts manager is divided into following submodule: interrupt storage, interrupt control unit, asynchronous event maker, processor command interface, intermodule order host device interface, intermodule order are from equipment interface.
(4.2) interrupt storage is realized.Interrupt storage stores the control block message of each asynchronous event, including the task number being blocked in asynchronous event.
(4.3) asynchronous event maker is realized；Asynchronous event maker comprises 32 external interrupt input signals, can be set as rising edge and trigger or trailing edge triggering；Asynchronous event mark can shield, set and removing；Asynchronous event mark can set when outside interrupting input signal meets trigger condition；When there being the task of obstruction in the asynchronous event of set, asynchronous event task wake request can be sent to controller lock module, application respective handling.
(4.4) interrupt control unit is realized.Interrupt control unit controls the action of remaining submodule in interrupt manager.It is realized by finite state machine, can complete the incoming order of processor command, other module, asynchronous event task wake operation.
(4.5) interrupt manager realizes following processor command: the task blocking order of band time-out time in task blocking command, asynchronous event in asynchronous event, asynchronous event mask off command, asynchronous event shield reading order, asynchronous event triggering mode setting command, asynchronous event triggering mode reading order, asynchronous event flag set order, asynchronous event mark clear command, asynchronous event mark reading order, interrupt control block querying command, interrupt manager reset command.
(4.6) interrupt manager realizes following intermodule order: task blocking mandatum cassatorium.
5, in hardware-core, it is achieved hardware counting semaphore manager.It includes following sub-step:
(5.1) hardware counting semaphore manager is divided into following submodule: counting semaphore memorizer, count signal amount controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface.
(5.2) counting semaphore memorizer is realized.Counting semaphore memorizer stores the control block message of each counting semaphore, including semaphore count value, blocked task bitmap.
(5.3) count signal amount controller is realized.Count signal amount controller controls the action of remaining submodule in counting semaphore manager.It is realized by finite state machine, can complete the order that processor command, other module are incoming.
(5.4) counting semaphore manager realizes following processor command: counting semaphore creates the task blocking order of band time-out time on task blocking command, counting semaphore on order, counting semaphore delete command, counting semaphore, counting semaphore release command, counting semaphore control block querying command, counting semaphore manager reset command.
(5.5) counting semaphore manager realizes following intermodule order: task blocking mandatum cassatorium.
6, in hardware-core, it is achieved hardware mutex amount manager.It includes following sub-step:
(6.1) hardware mutex amount manager is divided into following submodule: mutex amount memorizer, task support that relationship storage, mutex amount controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface.
(6.2) mutex amount memorizer is realized.Mutex amount memorizer stores the control block message of each mutex amount, including mutex amount owner's task number, blocked task bitmap.
(6.3) task that realizes supports relationship storage.Task supports storage in relationship storage because mutex amount is occupied blocks the task support relation caused, and the task of the transmission derived supports relation；Task supports that relation refers to, the task support being blocked in certain mutex amount occupies the task of this mutex amount；The task of transmission supports relation, refers to that task B supports task C, then task A also supports task C if task A supports task B；For each task, its task bitmap supported in record, and task inherits the priority of the task of supporting it, to realize the Priority Inheritance Protocol preventing priority from reversing；Support that relation derivation goes out transmission tasks and supports relation by task, support relation if there is symmetrical transmission tasks, then it represents that mutex amount application deadlock, asynchronous process application interrupt signal can be sent.
(6.4) mutex amount controller is realized.Mutex amount controller controls the action of remaining submodule in mutex amount manager.It is realized by finite state machine, can complete the order that processor command, other module are incoming.
(6.5) mutex amount manager realizes following processor command: mutex amount creates the task blocking order of band time-out time in task blocking command, mutex amount in order, mutex amount delete command, mutex amount, mutex amount release command, mutex amount control block querying command, mutex amount manager reset command.
(6.6) mutex amount manager realizes following intermodule order: task blocking mandatum cassatorium.
7, in hardware-core, it is achieved hardware message queue management device.It includes following sub-step:
(7.1) hardware message queue management device is divided into following submodule: message queue memorizer, message queue controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface.
(7.2) message queue memorizer is realized.Message queue memorizer stores the control block message of each message queue, including message queue relief area, message queue read pointer, message queue write pointer, the task blocking bitmap of message queue.
(7.3) message queue controller is realized.Message queue controller controls the action of remaining submodule in message queue manager.It is realized by finite state machine, can complete the order that processor command, other module are incoming.
(7.4) message queue manager realizes following processor command: message queue creates to be read on order, message queue delete command, message queue to write information order, message queue control block querying command, message queue manager reset command on information order, message queue on the reading information order of band time-out time, message queue.
(7.5) message queue manager realizes following intermodule order: task blocking mandatum cassatorium.
8, by comprising multiple uniprocessor hardware-core, it is achieved the operation system function of multiprocessor.It includes following sub-step:
(8.1) uniprocessor hardware-core is packaged；Each uniprocessor hardware-core, including a register interface module, controller lock module, task manager, several interrupt managers, several counting semaphore managers, several mutex amount manager and several message queue manager.
(8.2) according to configuration, one or more uniprocessor hardware-core of instantiation within hardware, each uniprocessor hardware-core has independent parameter configuration, thus realizes Multiprocessor operation system hardware-core.
9, in multiprocessor hardware kernel, it is achieved counting semaphore manager between processor.It includes following sub-step:
(9.1) counting semaphore manager between processor is divided into following submodule: count signal amount controller, processor command interface, intermodule order host device interface between counting semaphore memorizer, processor between processor.
(9.2) counting semaphore memorizer between processor is realized.Counting semaphore memorizer stores the control block message of each counting semaphore, including the limit priority of blocked task on the blocked task bitmap on semaphore count value, each processor, each processor between processor.
(9.3) count signal amount controller between processor is realized.Between processor, count signal amount controller controls the action of remaining submodule in counting semaphore manager between processor.It is realized by a finite state machine, can complete processor command.
(9.4) between processor, counting semaphore manager realizes following processor command: between processor, counting semaphore creates between order, processor between counting semaphore delete command, processor on counting semaphore between task blocking command, processor counting semaphore between counting semaphore release command, processor and controls counting semaphore manager reset command between block querying command, processor.
10, in multiprocessor hardware kernel, it is achieved message queue manager between processor.It includes following sub-step:
(10.1) message queue manager between processor is divided into following submodule: message queue controller, processor command interface, intermodule order host device interface between message queue memorizer, processor between processor.
(10.2) message queue memorizer between processor is realized.Message queue memorizer stores the control block message of each message queue, including the limit priority of blocked task on the blocked task bitmap on message queue relief area, message queue read pointer, message queue write pointer, each processor, each processor between processor.
(10.3) message queue controller between processor is realized.Between processor, message queue controller controls the action of remaining submodule in message queue manager between processor.It is realized by a finite state machine, can complete processor command.
(10.4) between processor, message queue manager realizes following processor command: reads to write message queue between information order, processor between information order, processor on message queue between processor between count message queue establishment order, processor between message queue delete command, processor on message queue and controls message queue manager reset command between block querying command, processor.
11, complete multiprocessor hardware the Realtime Operating System Nucleus is realized.It includes following sub-step:
(11.1) in multiple processor cores, including one or more single processor core, message queue manager between counting semaphore manager and several processors between register interface module, several processors.In each single processor core, including a register interface module, controller lock module, task manager, several interrupt managers, several counting semaphore managers, several mutex amount manager and several message queue manager.
(11.2) in single processor core, occur processor command, asynchronous event task wake up up, task scheduling request, system time sheet ticking event time, the controller lock module in single processor core is sent application, after locking by corresponding controllers complete operation.When processor inter-register interface module receives processor command, need the controller lock module of all processors is sent application, after all locking successfully, operation could be completed by corresponding controllers.
Enumerate the instantiation of the componentization hardware real-time operation system that two present invention realize below.As it is shown in figure 1, instance system realizes on the fpga chip that model is CycloneIVEP4CE115F29C7 of altera corp.Software interface operates on NIOSII soft-core processor, and hardware-core exists in the way of external equipment, mutual by Avalon system bus and processor.As in figure 2 it is shown, instance system realizes on the fpga chip that model is Spartan6XC6SLX16 of Xilinx company.Software interface operates on two Microblaze soft-core processors, and hardware-core exists in the way of external equipment, mutual by two AXI-Stream serial stream buses, an AXI bus and processor.
The componentization hardware real-time operation system that table 1 realizes for the present invention and the Character Comparison of some existing hardware real-time operation system.Wherein SierraKernel is unique commercialization hardware real-time operation system, HartOS is the hardware real-time operation system of increasing income of Syddansk Uni's realization in 2011, and UCOSII real time operating system Hardware is domestic more popular hardware real-time operation system implementation.
Table 1:
From table 1, use benefit of the invention is that: (1) is from systematic function, higher than the performance of pure software real time operating system and fractional hardware real time operating system, and system real time can preferably be ensured；(2) from system resources consumption, owing to using componentization mode, can cutting flexibly, can be than other hardware real-time operation system less hardware resource of consumption；(3) from system reliability, with stack pointer inspection, the reset of house dog time-out, mutex amount Deadlock Detection and strict processor command parameter testing, the reliability of system can be ensured well；(4) from the system expandability and Scalability, owing to using componentization mode, between system function module, the degree of coupling is the lowest, therefore can be extended functional module as required and cutting, is configured flexibly number of resources；(5) from system reusability, owing to using componentization mode, therefore register interface module can be changed neatly so that it is be applicable to different interface between software and hardware modes, there is durability higher；(6) owing to using componentization mode, system configurability and extensibility far above other hardware real-time operation system, it might even be possible to compare favourably with pure software real time operating system；(7) system can be used for multi-processor environment, adapts to industry Future Development needs.
Claims (1)
1. the implementation method of a componentization hardware real-time operation system, it is characterised in that the method comprises the steps:
(1) real time operating system is divided into hardware-core and software interface two parts, and determines software and hardware communication mode；It includes following sub-step:
(1.1) hardware-core being existed as coprocessor or external equipment, when as coprocessor, software and hardware is communicated by the general register of processor, and when as external equipment, software and hardware is communicated by system bus；
(1.2) the Realtime Operating System Nucleus function package is become hardware command, hardware command to include command number, input data, return value, output data by hardware-core；Hardware command is encapsulated as system and calls by software interface further, it is provided that use to application program；
(1.3) in addition to hardware command communicates, hardware-core also provides for two interrupt signals to processor, and one is used for task handover request, and one is used for abnormality processing application；Software interface is responsible for carrying out hardware-core and is sent the process of interruption, when task handover request interrupt signal is brought, carries out task switching, when abnormality processing application interrupt signal arrives, carries out abnormality processing；Abnormality processing application is except software processes, it is also possible to directly trigger processor reset；
(2) in hardware-core, the componentization implementation of each functional module of the Realtime Operating System Nucleus is determined so that it is adjustment, cutting and extension the most neatly；It includes following sub-step:
(2.1) hardware-core uses register interface module as the interface between software interface and the Realtime Operating System Nucleus functional module；Register interface module, by hardware command incoming for software interface, is converted to the processor command interface communication of the corresponding function module；
(2.2) the Realtime Operating System Nucleus functional module is connected in intermodule command interface bus by the intermodule command interface of standard, and the core functions module assignment of each instantiation has an independent address, to carry out intermodule command communication；In bus, the same time has only allowed a main equipment and one to initiate order from equipment, main equipment, perform order from equipment；
(2.3) real time operating system functional module includes following sections structure: memorizer, controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface；Wherein, memorizer is mainly realized by the ram in slice of FPGA；Processor command interface, intermodule order host device interface and intermodule order are communicating for module and outside from equipment interface；All parts action the most under control of the controller in module, controller finite state machine realizes；
(2.4) hardware-core uses a controller lock module to synchronize all the Realtime Operating System Nucleus functional modules, when the request of a processor command, timeslice wake events ticking, asynchronous or task scheduling arrives, request can be sent to controller lock module, the every secondary response of controller lock module one request, the controller of real time operating system functional module can complete to ask operation accordingly according to controller lock state；
(2.5) in a uniprocessor hardware-core, it is achieved task manager, several interrupt managers, several counting semaphore managers, several mutex amount manager and several message queue manager；
(3) in hardware-core, it is achieved hardware task manager；It includes following sub-step:
(3.1) hardware task manager is divided into following submodule: task memory, task controller, clock generator, WatchDog Timer, task dispatcher, processor command interface, intermodule order host device interface, intermodule order are from equipment interface；
(3.2) realize task memory: task memory stores the control block message of each task, inherit priority, the actual priority of task, task blocking resource number, task delay time sheet number, task round timeslice number, task stack pointer lower limit, the task stack pointer upper limit, task stack pointer including task status, task original priority, task；In addition, task memory also includes the tree-shaped priority comparator of the actual priority of task based access control, selects the limit priority task bitmap in particular task bitmap；When input is for ready task bitmap, it is output as the ready task bitmap of limit priority, it is achieved task preemption based on priority is dispatched；
(3.3) realizing clock generator, clock generator is arranged according to timeslice size, sends a tick_sig rising edge signal every the time of timeslice size, with the delay data of more new task；After the round timeslice of current task is finished, send task scheduling request, to trigger same priority task robin scheduling based on timeslice；
(3.4) WatchDog Timer is realized；House dog count value subtracts one at each tick_sig, sends abnormality processing application interrupt signal during house dog count value to zero, and house dog count value does not enables when being set to zero；
(3.5) task dispatcher is realized；Task dispatcher receives the ready task bitmap of the limit priority of task memory output, and store tasks round bitmap, to realize task preemption based on priority scheduling and same priority task robin scheduling based on timeslice；Task dispatcher output current task number and limit priority ready task number, and task handover request interrupt signal is sent when current task is not limit priority ready task；
(3.6) task controller is realized；The action of remaining submodule in task controller control task manager；It is realized by finite state machine, completes the incoming order of processor command, other module, task delayed data that task-scheduling operation, tick_sig trigger adjusts operation；
(3.7) task manager realizes following processor command: task creation order, task delete command, task suspension order, task recovery order, task delay command, task time delay mandatum cassatorium, task priority amendment order, task concede processor command, task round timeslice number setting command, task control block querying command, task manager reset command；
(3.8) task manager realizes following intermodule order: select task wake command, task blocking order based on mutex amount, band time-out time task blocking order based on mutex amount, task wake command based on mutex amount in task blocking order, the task blocking order of band time-out time, task wake command, task blocking bitmap；
(4) in hardware-core, it is achieved hardware interrupts manager；It includes following sub-step:
(4.1) hardware interrupts manager is divided into following submodule: interrupt storage, interrupt control unit, asynchronous event maker, processor command interface, intermodule order host device interface, intermodule order are from equipment interface；
(4.2) interrupt storage is realized；Interrupt storage stores the control block message of each asynchronous event, including the task number being blocked in asynchronous event；
(4.3) asynchronous event maker is realized；Asynchronous event maker comprises 32 external interrupt input signals, is set as that rising edge triggers or trailing edge triggers；Asynchronous event mark can shield, set and removing；Asynchronous event mark can set when outside interrupting input signal meets trigger condition；When there being the task of obstruction in the asynchronous event of set, asynchronous event task wake request can be sent to controller lock module, application respective handling；
(4.4) interrupt control unit is realized；Interrupt control unit controls the action of remaining submodule in interrupt manager；It is realized by finite state machine, completes the incoming order of processor command, other module, asynchronous event task wake operation；
(4.5) interrupt manager realizes following processor command: the task blocking order of band time-out time in task blocking command, asynchronous event in asynchronous event, asynchronous event mask off command, asynchronous event shield reading order, asynchronous event triggering mode setting command, asynchronous event triggering mode reading order, asynchronous event flag set order, asynchronous event mark clear command, asynchronous event mark reading order, interrupt control block querying command, interrupt manager reset command；
(4.6) interrupt manager realizes following intermodule order: task blocking mandatum cassatorium；
(5) in hardware-core, it is achieved hardware counting semaphore manager；It includes following sub-step:
(5.1) hardware counting semaphore manager is divided into following submodule: counting semaphore memorizer, count signal amount controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface；
(5.2) counting semaphore memorizer is realized；Counting semaphore memorizer stores the control block message of each counting semaphore, including semaphore count value, blocked task bitmap；
(5.3) count signal amount controller is realized；Count signal amount controller controls the action of remaining submodule in counting semaphore manager；It is realized by a finite state machine, completes the order that processor command, other module are incoming；
(5.4) counting semaphore manager realizes following processor command: counting semaphore creates the task blocking order of band time-out time on task blocking command, counting semaphore on order, counting semaphore delete command, counting semaphore, counting semaphore release command, counting semaphore control block querying command, counting semaphore manager reset command；
(5.5) counting semaphore manager realizes following intermodule order: task blocking mandatum cassatorium；
(6) in hardware-core, it is achieved hardware mutex amount manager；It includes following sub-step:
(6.1) hardware mutex amount manager is divided into following submodule: mutex amount memorizer, task support that relationship storage, mutex amount controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface；
(6.2) mutex amount memorizer is realized；Mutex amount memorizer stores the control block message of each mutex amount, including mutex amount owner's task number, blocked task bitmap；
(6.3) task that realizes supports relationship storage；Task supports storage in relationship storage because mutex amount is occupied blocks the task support relation caused, and the task of the transmission derived supports relation；Task supports that relation refers to, the task support being blocked in certain mutex amount occupies the task of this mutex amount；The task of transmission supports relation, refers to that task B supports task C, then task A also supports task C if task A supports task B；For each task, its task bitmap supported in record, and task inherits the priority of the task of supporting it, to realize the Priority Inheritance Protocol preventing priority from reversing；Support that relation derivation goes out transmission tasks and supports relation by task, support relation if there is symmetrical transmission tasks, then it represents that mutex amount application deadlock, asynchronous process application interrupt signal can be sent；
(6.4) mutex amount controller is realized；Mutex amount controller controls the action of remaining submodule in mutex amount manager；It is realized by finite state machine, completes the order that processor command, other module are incoming；
(6.5) mutex amount manager realizes following processor command: mutex amount creates the task blocking order of band time-out time in task blocking command, mutex amount in order, mutex amount delete command, mutex amount, mutex amount release command, mutex amount control block querying command, mutex amount manager reset command；
(6.6) mutex amount manager realizes following intermodule order: task blocking mandatum cassatorium；
(7) in hardware-core, it is achieved hardware message queue management device；It includes following sub-step:
(7.1) hardware message queue management device is divided into following submodule: message queue memorizer, message queue controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface；
(7.2) message queue memorizer is realized；Message queue memorizer stores the control block message of each message queue, including message queue relief area, message queue read pointer, message queue write pointer, the task blocking bitmap of message queue；
(7.3) message queue controller is realized；Message queue controller controls the action of remaining submodule in message queue manager；It is realized by finite state machine, completes the order that processor command, other module are incoming；
(7.4) message queue manager realizes following processor command: message queue creates to be read on order, message queue delete command, message queue to write information order, message queue control block querying command, message queue manager reset command on information order, message queue on the reading information order of band time-out time, message queue；
(7.5) message queue manager realizes following intermodule order: task blocking mandatum cassatorium；
(8) by comprising multiple uniprocessor hardware-core, it is achieved the operation system function of multiprocessor；It includes following sub-step:
(8.1) uniprocessor hardware-core is packaged；Each uniprocessor hardware-core, including a register interface module, controller lock module, task manager, several interrupt managers, several counting semaphore managers, several mutex amount manager and several message queue manager；
(8.2) according to configuration, one or more uniprocessor hardware-core of instantiation within hardware, each uniprocessor hardware-core has independent parameter configuration, thus realizes Multiprocessor operation system hardware-core；
(9) in multiprocessor hardware kernel, it is achieved counting semaphore manager between processor；It includes following sub-step:
(9.1) counting semaphore manager between processor is divided into following submodule: count signal amount controller, processor command interface, intermodule order host device interface between counting semaphore memorizer, processor between processor；
(9.2) counting semaphore memorizer between processor is realized；Counting semaphore memorizer stores the control block message of each counting semaphore, including the limit priority of blocked task on the blocked task bitmap on semaphore count value, each processor, each processor between processor；
(9.3) count signal amount controller between processor is realized；Between processor, count signal amount controller controls the action of remaining submodule in counting semaphore manager between processor；It is realized by a finite state machine, completes processor command；
(9.4) between processor, counting semaphore manager realizes following processor command: between processor, counting semaphore creates between order, processor between counting semaphore delete command, processor on counting semaphore between task blocking command, processor counting semaphore between counting semaphore release command, processor and controls counting semaphore manager reset command between block querying command, processor；
(10) in multiprocessor hardware kernel, it is achieved message queue manager between processor；It includes following sub-step:
(10.1) message queue manager between processor is divided into following submodule: message queue controller, processor command interface, intermodule order host device interface between message queue memorizer, processor between processor；
(10.2) message queue memorizer between processor is realized；Message queue memorizer stores the control block message of each message queue, including the limit priority of blocked task on the blocked task bitmap on message queue relief area, message queue read pointer, message queue write pointer, each processor, each processor between processor；
(10.3) message queue controller between processor is realized；Between processor, message queue controller controls the action of remaining submodule in message queue manager between processor；It is realized by a finite state machine, completes processor command；
(10.4) between processor, message queue manager realizes following processor command: reads to write message queue between information order, processor between information order, processor on message queue between processor between count message queue establishment order, processor between message queue delete command, processor on message queue and controls message queue manager reset command between block querying command, processor；
(11) complete multiprocessor hardware the Realtime Operating System Nucleus is realized；It includes following sub-step:
(11.1) in multiple processor cores, including one or more single processor core, message queue manager between counting semaphore manager and several processors between register interface module, several processors；In each single processor core, including a register interface module, controller lock module, task manager, several interrupt managers, several counting semaphore managers, several mutex amount manager and several message queue manager；
(11.2) in single processor core, occur processor command, asynchronous event task wake up up, task scheduling request, system time sheet ticking event time, the controller lock module in single processor core is sent application, after locking by corresponding controllers complete operation；When processor inter-register interface module receives processor command, need the controller lock module of all processors is sent application, after all locking successfully, corresponding controllers complete the operation being applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310396603.3A CN103440171B (en) | 2013-08-25 | 2013-08-25 | A kind of implementation method of componentization hardware real-time operation system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310396603.3A CN103440171B (en) | 2013-08-25 | 2013-08-25 | A kind of implementation method of componentization hardware real-time operation system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103440171A CN103440171A (en) | 2013-12-11 |
| CN103440171B true CN103440171B (en) | 2016-08-03 |
Family
ID=49693861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310396603.3A Expired - Fee Related CN103440171B (en) | 2013-08-25 | 2013-08-25 | A kind of implementation method of componentization hardware real-time operation system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103440171B (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104598208B (en) * | 2015-02-11 | 2016-01-27 | 四川天邑康和通信股份有限公司 | A kind of operating system of single-chip microcomputer implementation method of Effect-based operation queue |
| CN105260331B (en) * | 2015-10-09 | 2018-08-28 | 天津国芯科技有限公司 | A kind of dual bus Memory Controller Hub |
| CN105354381B (en) * | 2015-11-05 | 2018-07-13 | 天津津航计算技术研究所 | FPGA redundance implementation methods based on reconstruct |
| CN105335237B (en) * | 2015-11-09 | 2018-09-21 | 浪潮电子信息产业股份有限公司 | A kind of deadlock prevention technique of operating system |
| CN108292236B (en) * | 2015-11-30 | 2022-11-01 | 华为技术有限公司 | Information processing method and device |
| US10732634B2 (en) * | 2017-07-03 | 2020-08-04 | Baidu Us Llc | Centralized scheduling system using event loop for operating autonomous driving vehicles |
| CN108280519B (en) * | 2018-01-30 | 2020-07-31 | 湖南工学院 | Big data genetic algorithm data modeling processing device |
| CN111596962B (en) * | 2019-02-20 | 2023-05-30 | 中标软件有限公司 | Real-time microkernel system based on high-speed protocol channel and initialization method thereof |
| CN110262905A (en) * | 2019-05-31 | 2019-09-20 | 四川长虹电器股份有限公司 | The method for pushing of the message-oriented middleware of priority query based on building high performance and scalability |
| CN111158875B (en) * | 2019-12-25 | 2023-05-02 | 眸芯科技（上海）有限公司 | Multi-module-based multi-task processing method, device and system |
| CN112511537B (en) * | 2020-11-30 | 2023-01-24 | 深圳国微晶锐技术有限公司 | SCE-MI protocol bridge and simulation system |
| CN112380025A (en) * | 2020-12-03 | 2021-02-19 | 王志平 | Progress synchronization implementation method based on HSC |
| CN112559210B (en) * | 2020-12-16 | 2024-05-07 | 北京仿真中心 | Shared resource read-write mutual exclusion method based on RTX real-time system |
| CN113867988A (en) * | 2021-09-29 | 2021-12-31 | 展讯通信（深圳）有限公司 | Universal remote communication calling architecture and method |
| CN114168365B (en) * | 2021-12-07 | 2023-06-20 | 中国船舶重工集团公司第七0七研究所 | Real-time data recording method based on stm32f450 processor |
| CN114035970B (en) * | 2022-01-10 | 2022-04-22 | 南京云信达科技有限公司 | Data concurrent competition conflict detection analysis method and system |
| CN115061736A (en) * | 2022-05-19 | 2022-09-16 | 北京控制工程研究所 | Dynamic task management method and system based on service registration mechanism |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6957432B2 (en) * | 2000-03-21 | 2005-10-18 | Microsoft Corporation | Real-time scheduler |
| US7386853B2 (en) * | 2001-07-12 | 2008-06-10 | Denso Corporation | Multitasking operating system capable of reducing power consumption and vehicle electronic control unit using same |
| CN100465857C (en) * | 2006-10-12 | 2009-03-04 | 浙江大学 | Simplifying method facing to embedded system low-power consumption real time task scheduling |
| CN100470485C (en) * | 2007-05-09 | 2009-03-18 | 浙江大学 | Method for realizing multiple operation system synergistic working |
-
2013
- 2013-08-25 CN CN201310396603.3A patent/CN103440171B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6957432B2 (en) * | 2000-03-21 | 2005-10-18 | Microsoft Corporation | Real-time scheduler |
| US7386853B2 (en) * | 2001-07-12 | 2008-06-10 | Denso Corporation | Multitasking operating system capable of reducing power consumption and vehicle electronic control unit using same |
| CN100465857C (en) * | 2006-10-12 | 2009-03-04 | 浙江大学 | Simplifying method facing to embedded system low-power consumption real time task scheduling |
| CN100470485C (en) * | 2007-05-09 | 2009-03-18 | 浙江大学 | Method for realizing multiple operation system synergistic working |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103440171A (en) | 2013-12-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103440171B (en) | A kind of implementation method of componentization hardware real-time operation system | |
| EP3185128B1 (en) | Gpu virtualisation | |
| CN105787360B (en) | A kind of Implementation Technology of embedded system memory safe access control | |
| WO2008141063A2 (en) | Interrupt-related circuits, systems, and processes | |
| CN107017014B (en) | Dynamic containerized system memory protection for low energy MCU | |
| US20160004647A1 (en) | Method and circuit arrangement for accessing slave units in a system on chip in a controlled manner | |
| CN106681949B (en) | Direct memory operation implementation method based on consistency acceleration interface | |
| CN102077181A (en) | Method and system for generating and delivering inter-processor interrupts in a multi-core processor and in certain shared-memory multi-processor systems | |
| JPS5841538B2 (en) | Multiprocessor system instructions | |
| WO2012016439A1 (en) | Method, device and equipment for service management | |
| CN103377081A (en) | Implementation method for interrupt mechanism between embedded numerical control system dual-core chip and peripheral | |
| US20180137082A1 (en) | Single-chip multi-processor communication | |
| US20210334228A1 (en) | Managing network interface controller-generated interrupts | |
| Ahmadinia et al. | Task scheduling for heterogeneous reconfigurable computers | |
| JP2018512662A (en) | Microcontroller device with multiple independent microcontrollers | |
| JP2011175625A (en) | System on chip having interrupt proxy function, and interrupt proxy processing method | |
| JPS61265661A (en) | Multiplex processing system | |
| CN110399034A (en) | A kind of power consumption optimization method and terminal of SoC system | |
| Mirhosseini et al. | HyperPlane: A scalable low-latency notification accelerator for software data planes | |
| CN109933549B (en) | Interrupt controller suitable for RISC-V treater | |
| Abellán et al. | A g-line-based network for fast and efficient barrier synchronization in many-core cmps | |
| KR20230164152A (en) | Seamlessly integrated microcontroller chip | |
| CN113946445A (en) | Multithreading module based on ASIC and multithreading control method | |
| CN110276214A (en) | A kind of credible SOC framework of double-core and method based on slave access protection | |
| US7516311B2 (en) | Deterministic microcontroller context arrangement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160803 Termination date: 20190825 |