CN103440171A - Realization method of real-time operating system of component-based hardware - Google Patents
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Abstract
The invention discloses a realization method of a real-time operating system of component-based hardware. The method comprises the following steps of: firstly, dividing the real-time operating system into two parts including a hardware inner core and a software interface; then, realizing the communication of a task manager, an interruption manager, a counting semaphore manager, a mutual exclusion semaphore manager and a message queue manager of the real-time operating system by component-based manner in the hardware inner core; enabling the hardware inner core to be communicated with software by a register interface module; synchronizing all the managers by a controller lock; enabling the mangers to be communicated by standard inter-mould command interface buses; and finally, realizing an inter-processor counting semaphore manager and an inter-processor message queue manager and realizing the hardware inner core of a multiprocessor real-time operating system. According to the realization method, the inner core of the hardware real-time operating system is realized by a component-based manner so that the cuttability and the expandability of the system are improved greatly and the flexibility of the software is realized by the real-time operation of the hardware.
Description
Technical field
The invention belongs to the real time operating system Hardware and realize field, relate to a kind of implementation method of componentization hardware real time operating system.
Background technology
Development along with the embedded system industry, real time operating system RTOS(Real Time Operating System) all be widely applied in fields such as Industry Control, medicine equipment, Aero-Space, automotive electronics, household electrical appliance, and occupied than great share in embedded system.Real time operating system refers to and can within definite time, to external trigger, make in time a type operating system that responds and carry out corresponding task.Why RTOS can be widely used in the computing machine Embedded Application, is because RTOS can become multitask by Task-decomposing, has simplified the design of application systems software.RTOS is guaranteed the real-time of control system, good multitask design, reliability and the security that can improve embedded system.
Along with deepening constantly and refinement of application, the application scenarios of various complexity is also being strengthened gradually to performance and the stability requirement of RTOS.General desktop operating system has more comprehensive consideration aspect reliability, to meet complex application context, avoids deadlock, malicious attack etc.Yet most RTOS simplify processing to the reliability of system in order to guarantee under the performance requirement such as real-time, and the author of application programs proposes higher technical requirement, thereby the potential safety hazard of staying.Traditional RTOS can't meet higher real-time and reliability requirement simultaneously.Adopting the software-hardware synergism means, the RTOS functional module is carried out to cure process and function remodeling, is a kind of effective means of taking into account system real time and reliability.This is also one of focus of current RTOS research.
The nineties in 20th century, abroad someone has proposed the concept of real time operating system Hardware, uses hardware logic electric circuit or sequential circuit to realize task scheduling in traditional real time operating system, interrupt the functions such as processing, resource management.The achievement in research of moulding afterwards starts to occur.Paul Kohout in 2003, by the real-time task manager hardware, carries out the scheduling of Priority-based and timeslice.2008, the Cui Jianhua of School of Information Technology of PLA, the framed structure based on " ppu+FPGA ", designed the hardware RTOS that supports the functions such as task scheduling, interrupt management, timer management.2011, the Anders Blaabjerg Lange of Syddansk Uni has designed and Implemented comparatively complete hardware real time operating system HartOS, HartOS has comprised task manager, interrupt manager, explorer, and uses API Processor to realize communicating by letter between CPU and manager.2012, the Gu Pingping of domestic Harbin University of Science and Technology was used genetic algorithm NSGA-II as hardware/software partitioning algorithms, according to application, need to carry out the part Hardware to UCOS II real time operating system, between hardware resource consumption and performance boost, averages out.
From application point, the evaluation of a real time operating system is embodied in to five aspects: (1) system performance, i.e. system real time and complete the speed of every kernel operations; (2) system resources consumption, i.e. system shared software memory space and amount of hardware resources; (3) system reliability, i.e. system debugging ability and abnormal restoring ability; (4) system expandability and Scalability, the ability that system need to be carried out cutting or expansion according to application; (5) system reusability, system is applicable to the ability of different running environment.But, although advantage is separately arranged, all there is defect in existing most of hardware real time operating system aspect one or more evaluation.Or because too much bus communication causes performance to reduce, or because spending height, system, coupled is difficult to cutting and expansion, or can only on specific hardware, realize, or software operation inspection deficiency is existed to the defect on reliability, or there is larger gap with the software real time operating system on function.
Summary of the invention
The object of the invention is to for the deficiencies in the prior art, a kind of implementation method of componentization hardware real time operating system is provided.
The technical solution adopted for the present invention to solve the technical problems is: a kind of implementation method of componentization hardware real time operating system, and the method comprises the following steps:
(1) real time operating system is divided into to hardware-core and software interface two parts, and definite software and hardware communication mode;
(2) in hardware-core, determine the componentization implementation of each functional module of the Realtime Operating System Nucleus, make its adjustment neatly, cutting and expansion as required;
(3), in hardware-core, realize the hardware task manager;
(4), in hardware-core, realize the hardware interrupts manager;
(5), in hardware-core, realize hardware counting semaphore manager;
(6), in hardware-core, realize hardware mutex amount manager;
(7), in hardware-core, realize the hardware message queue manager;
(8) by comprising a plurality of uniprocessor hardware-core, realize the operation system function of multiprocessor;
(9), in the multiprocessor hardware-core, realize counting semaphore manager between processor;
(10), in the multiprocessor hardware-core, realize message queue manager between processor;
(11) realize complete multiprocessor hardware the Realtime Operating System Nucleus.
The beneficial effect that the present invention has is:
1,, system performance, the present invention is full the Realtime Operating System Nucleus Hardware, has at utmost reduced the software and hardware communication overhead, than the real time operating system of part Hardware, on performance, improves a lot;
2, from system resources consumption, the present invention uses the componentization mode to realize the hardware the Realtime Operating System Nucleus, can carry out as required cutting and adjust size, at utmost reduce unnecessary resource overhead, the storer of while the Realtime Operating System Nucleus functional module, all use the FPGA ram in slice to realize, compare with other hardware real time operating system, at utmost reduced the consumption of hardware logic unit;
3, system reliability, the present invention uses various ways to guarantee system reliability, be included in task manager and add watchdog module, add stack pointer check logic, add Deadlock Detection in mutex amount manager, when hardware command is carried out, carry out various status checkings and parameter testing in task manager, guarantee the reliability of real time operating system with the reliability that takes full advantage of hardware;
4, from the system expandability and Scalability, the present invention uses the componentization mode to realize the hardware the Realtime Operating System Nucleus, and intermodule is by self-defined bus communication, and the degree of coupling is very low, is suitable for expansion and cutting;
5, the system reusability, hardware-core is used hardware logic unit and ram in slice to realize fully, do not need special hardware supported, and the software and hardware communication mode is encapsulated in outside functional module, can replace neatly, do not need special bus support, therefore can reach very high reusing degree.
6, the present invention has realized the task blocking queue of the same priority task scheduling of time-based sheet, all kinds of resource Priority-baseds, the priority inheritance agreement of mutex amount dexterously with a small amount of hardware resource, broken through hardware real time operating system complexity low, be difficult to the problem compared favourably with the software real time operating system;
7, the hardware real time operating system that the present invention uses the componentization mode to realize, can be advantageously used in supporting current industry popular multiprocessor and multi-core processor system gradually, and this is a kind of breakthrough to the existing hardware real time operating system.
The accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms the part of instructions, with embodiments of the invention, jointly for explaining the present invention, is not construed as limiting the invention.
Fig. 1 is the uniprocessor componentization real time operating system Organization Chart on the Altera fpga chip.
Fig. 2 is the multiprocessor componentization real time operating system Organization Chart on the Xilinx fpga chip.
Embodiment
Describe the embodiment of this explanation in detail below with reference to drawings and Examples, to the present invention, how the application technology means solve technical matters whereby, and the implementation procedure of reaching technique effect can fully understand and implement according to this.
The present invention, for realizing the hardware real time operating system of componentization, specifically comprises the steps:
1, real time operating system is divided into to hardware-core and software interface two parts, and definite software and hardware communication mode.It comprises following sub-step:
(1.1) using hardware-core as coprocessor or external unit exist, when as coprocessor, software and hardware communicates by the general-purpose register of processor, when as external unit, software and hardware communicates by system bus.
(1.2) hardware-core becomes hardware command by the Realtime Operating System Nucleus function package, and hardware command comprises command number, input data, rreturn value, output data.Software interface further is encapsulated as system call by hardware command, offers application program and uses.
(1.3) except hardware command communication, hardware-core also provides two look-at-mes to processor, and one for the task handover request, and one for the abnormality processing application; Software interface is responsible for carrying out the processing that hardware-core is sent interruption, when task handover request look-at-me is brought, carries out the task switching, when abnormality processing application look-at-me arrives, carries out abnormality processing; The abnormality processing application is processed except software, can also directly trigger processor reset
2, in hardware-core, determine the componentization implementation of each functional module of the Realtime Operating System Nucleus, make its adjustment neatly, cutting and expansion as required.It comprises following sub-step:
(2.1) hardware-core is used the register interface module as the interface between software interface and the Realtime Operating System Nucleus functional module.The hardware command that the register interface module is imported software interface into, be converted to the processor command interface communication of the corresponding function module.The processor command interface bus signal of the Realtime Operating System Nucleus functional module is as follows:
Cpu_target[7:0], the functional module address that processor command is corresponding;
Cpu_input_wr, the input data write signal;
Cpu_input_data[31:0], the input data, cpu_input_wr be 1 o'clock effective, can write maximum 16 the input data;
Cpu_cmd_data[31:0], the order numbering;
Cpu_cmd_req, request is initiated in order, after input data and order numbering are in place, can initiate command request;
Cpu_cmd_ack, the order complement mark;
Cpu_cmd_ret[7:0], the order rreturn value;
Cpu_cmd_output_num[3:0], order output data amount check, have at most 15 output data;
Cpu_output_rd, the output data reading signal;
Cpu_output_data[31:0], the data data, be to be switched to next output data at 1 o'clock at cpu_output_rd.
(2.2) the Realtime Operating System Nucleus functional module is connected on intermodule command interface bus by the intermodule command interface of standard, and the core functions module assignment of each instantiation has an independently address, to carry out the intermodule command communication; On bus, the same time only allows one a main equipment and one to be arranged from equipment, and main equipment is initiated order, from the equipment fill order.Intermodule command interface bus signals is as follows:
Slave_target[7:0], from device address;
Input_wr, the input data write signal;
Input_data[31:0], the input data, input_wr be 1 o'clock effective, can write maximum 16 the input data;
Cmd_data[31:0], the order numbering;
Cmd_req, request is initiated in order, after input data and order numbering are in place, can initiate command request;
Cmd_ack, the order complement mark;
Cmd_ret[7:0], the order rreturn value;
Cmd_output_num[3:0], order output data amount check, have at most 15 output data;
Output_rd, the output data reading signal;
Output_data[31:0], the data data, be to be switched to next output data at 1 o'clock at output_rd.
(2.3) every class real time operating system functional module includes following a few part-structure: storer, controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface; Wherein, storer is mainly realized by the ram in slice of FPGA; The various command interface is for module and outside communicating by letter; All actions under controller is controlled of all parts in module, controller is realized with finite state machine.
(2.4) hardware-core is used a controller lock module to carry out synchronously all real time operating system functional modules, when a processor command, timeslice ticktock, asynchronous wake events or task scheduling request arrive, can send request to the controller lock module, request of the every secondary response of controller lock module, the controller of each real time operating system functional module can complete corresponding solicit operation according to the controller lock state.
(2.5) every class real time operating system functional module can have several examples as required, and the number of resources in each instantiation module also can configure neatly.There do not is master slave relation between functional module, can add neatly, delete or revise, only communicate by intermodule command interface bus between functional module, keep the low degree of coupling.In a uniprocessor hardware-core, realize a task manager, several interrupt managers, several counting semaphore managers, several mutex amount managers and several message queue manager.
3,, in hardware-core, realize the hardware task manager.It comprises following sub-step:
(3.1) the hardware task manager is divided into to following submodule: task memory, task controller, clock generator, WatchDog Timer, task dispatcher, processor command interface, intermodule order host device interface, intermodule order are from equipment interface.
(3.2) realize task memory.The controll block information of each task of storage in task memory, comprise that task status, task original priority, task succession priority, the actual priority of task, task blocking resource number, task delay time sheet number, task wheel turn timeslice number, task stack pointer lower limit, the task stack pointer upper limit, task stack pointer.In addition, task memory also comprises the tree-shaped priority comparer based on the actual priority of task, can select the limit priority task bitmap in the particular task bitmap; When being input as the ready task bitmap, be output as the ready task bitmap of limit priority, realize the task preemption scheduling of Priority-based.
(3.3) realize clock generator, clock generator arranges according to timeslice size, every the time of timeslice size, sends a tick_sig rising edge information, with the delay data of new task more.After the wheel of current task turns timeslice and is finished, send dispatch request, to trigger the same priority task robin scheduling of time-based sheet.
(3.4) realize WatchDog Timer.The house dog count value subtracts one at each tick_sig, sends abnormality processing application look-at-me while reducing to zero, and the house dog count value does not enable when being set to zero.
(3.5) realize task dispatcher.Task dispatcher receives the ready task bitmap of the limit priority of task memory output, and store tasks wheel transposition figure, with the task preemption scheduling that realizes Priority-based and the same priority task robin scheduling of time-based sheet; Task dispatcher output current task number and limit priority ready task number, and send task handover request look-at-me when current task is not the limit priority ready task.
(3.6) realize task controller.The action of all the other submodules in task controller control task manager.It realizes by finite state machine, can complete the task delayed data adjusting operation that order, task-scheduling operation, tick_sig that processor command, other module import into trigger.
(3.7) task manager is realized following processor command: task creation order, task delete command, task suspension order, task recovery order, task time delay order, task time delay mandatum cassatorium, task priority are revised orders, task is abdicated processor command, the task wheel turns the timeslice number order, task control block (TCB) querying command, task manager reset command are set.
(3.8) task manager is realized following intermodule order: selection task wake command in task blocking order, the task blocking order with time-out time, task wake command, task blocking bitmap, the task blocking order based on the mutex amount, based on the mutex amount with the order of time-out time task blocking, task wake command based on the mutex amount.
4,, in hardware-core, realize the hardware interrupts manager.It comprises following sub-step:
(4.1) the hardware interrupts manager is divided into to following submodule: interrupt storage, interruptable controller, asynchronous event maker, processor command interface, intermodule order host device interface, intermodule order are from equipment interface.
(4.2) realize interrupt storage.In interrupt storage, the controll block information of each asynchronous event of storage, comprise the task number be blocked on asynchronous event.
(4.3) realize the asynchronous event maker; Comprise 32 external interrupt input signals in the asynchronous event maker, can be set as rising edge triggering or negative edge and trigger; The asynchronous event sign can shielding, set and removing; The asynchronous event sign is understood set when externally the interrupting input signal meets trigger condition; When the task of obstruction is arranged on the asynchronous event of set, can send asynchronous event task wake request to the controller lock module, the application respective handling.
(4.4) realize interruptable controller.Interruptable controller is controlled the action of all the other submodules in interrupt manager.It realizes by finite state machine, can complete order, asynchronous event task wake operation that processor command, other module import into.
(4.5) interrupt manager is realized following processor command: on asynchronous event, on task blocking order, asynchronous event, task blocking order, asynchronous event mask off command, the asynchronous event with time-out time shields reading order, the asynchronous event triggering mode arranges order, asynchronous event triggering mode reading order, the order of asynchronous event flag set, asynchronous event sign clear command, asynchronous event sign reading order, interrupt control block querying command, interrupt manager reset command.
(4.6) interrupt manager is realized following intermodule order: the task blocking mandatum cassatorium.
5,, in hardware-core, realize hardware counting semaphore manager.It comprises following sub-step:
(5.1) hardware counting semaphore manager is divided into to following submodule: counting semaphore storer, count signal amount controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface.
(5.2) realize the counting semaphore storer.The controll block information of each counting semaphore of storage in the counting semaphore storer, comprise the semaphore count value, block the task bitmap.
(5.3) realize the count signal amount controller.The count signal amount controller is controlled the action of all the other submodules in the counting semaphore manager.It realizes by finite state machine, can complete the order that processor command, other module import into.
(5.4) the counting semaphore manager is realized following processor command: on task blocking order on counting semaphore establishment order, counting semaphore delete command, counting semaphore, counting semaphore with task blocking order, counting semaphore release command, counting semaphore controll block querying command, the counting semaphore manager reset command of time-out time.
(5.5) the counting semaphore manager is realized following intermodule order: the task blocking mandatum cassatorium.
6,, in hardware-core, realize hardware mutex amount manager.It comprises following sub-step:
(6.1) hardware mutex amount manager is divided into to following submodule: mutex amount storer, task support relational storage device, mutex amount controller, processor command interface, intermodule order host device interface, intermodule order from equipment interface.
(6.2) realize mutex amount storer.The controll block information of each mutex amount of storage in mutex amount storer, comprise mutex amount owner task number, block the task bitmap.
(6.3) realize task support relational storage device.Task is supported storage in the relational storage device and is blocked because the mutex amount is occupied the task support relation caused, and the task of the transmission of deriving is supported relation; Task support relation refers to, is blocked in the task that task support on certain mutex amount occupies this mutex amount; Transmitting of task is supported relation, refers to that task B supports task C if task A supports task B, and task A also supports task C; For each task, its task bitmap supported in record, and task is inherited the priority of the task of supporting it, to realize the priority inheritance agreement that prevents that priority from reversing; By task, support relation derivation to go out transmission tasks and support relation, if exist symmetrical transmission tasks to support relation, mean mutex amount application deadlock, can send asynchronous process application look-at-me.
(6.4) realize the mutex amount controller.The mutex amount controller is controlled the action of all the other submodules in mutex amount manager.It realizes by finite state machine, can complete the order that processor command, other module import into.
(6.5) mutex amount manager is realized following processor command: on task blocking order on mutex amount establishment order, mutex amount delete command, mutex amount, mutex amount with task blocking order, the release command of mutex amount, mutex amount controll block querying command, the mutex amount manager reset command of time-out time.
(6.6) mutex amount manager is realized following intermodule order: the task blocking mandatum cassatorium.
7,, in hardware-core, realize the hardware message queue manager.It comprises following sub-step:
(7.1) the hardware message queue manager is divided into to following submodule: message queue storer, message queue controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface.
(7.2) realize the message queue storer.Store the controll block information of each message queue in the message queue storer, comprise the task blocking bitmap of message queue buffer zone, message queue read pointer, message queue write pointer, message queue.
(7.3) realize the message queue controller.The action of all the other submodules in message queue controller control message queue management device.It realizes by finite state machine, can complete the order that processor command, other module import into.
(7.4) message queue manager realizes following processor command: on message queue establishment order, message queue delete command, message queue, read on information order, message queue to read on information order, message queue to write information order, message queue controll block querying command, message queue manager reset command with time-out time.
(7.5) message queue manager realizes following intermodule order: the task blocking mandatum cassatorium.
8, by comprising a plurality of uniprocessor hardware-core, realize the operation system function of multiprocessor.It comprises following sub-step:
(8.1) the uniprocessor hardware-core is encapsulated; Each uniprocessor hardware-core, comprise a register interface module, a controller lock module, task manager, several interrupt managers, several counting semaphore managers, several mutex amount managers and several message queue manager.
(8.2) according to configuration, one or more uniprocessor hardware-core of instantiation in hardware, each uniprocessor hardware-core has independently parameter configuration, thereby realizes the Multiprocessor operation system hardware-core.
9,, in the multiprocessor hardware-core, realize counting semaphore manager between processor.It comprises following sub-step:
(9.1) counting semaphore manager between processor is divided into to following submodule: count signal amount controller, processor command interface, intermodule order host device interface between counting semaphore storer, processor between processor.
(9.2) realize counting semaphore storer between processor.Between processor, the controll block information of each counting semaphore of storage in the counting semaphore storer, comprise the limit priority that blocks task on obstruction task bitmap on semaphore count value, each processor, each processor.
(9.3) realize count signal amount controller between processor.The action of all the other submodules in the counting semaphore manager between count signal amount controller control processor between processor.It is realized by a finite state machine, can complete processor command.
(9.4) between processor, the counting semaphore manager is realized following processor command: between processor counting semaphore create order, counting semaphore manager reset command between counting semaphore controll block querying command, processor between counting semaphore release command between task blocking order on counting semaphore, processor, processor between counting semaphore delete command, processor between processor.
10,, in the multiprocessor hardware-core, realize message queue manager between processor.It comprises following sub-step:
(10.1) message queue manager between processor is divided into to following submodule: message queue controller, processor command interface, intermodule order host device interface between message queue storer, processor between processor.
(10.2) realize message queue storer between processor.Between processor, the controll block information of each message queue of storage in the message queue storer, comprise the limit priority that blocks task on obstruction task bitmap on message queue buffer zone, message queue read pointer, message queue write pointer, each processor, each processor.
(10.3) realize message queue controller between processor.The action of all the other submodules in message queue manager between message queue controller control processor between processor.It is realized by a finite state machine, can complete processor command.
(10.4) between processor, message queue manager realizes following processor command: between processor, the count message queue creates and orders, reads between information order, processor to write on message queue on message queue between message queue delete command, processor between processor between information order, processor message queue manager reset command between message queue controll block querying command, processor.
11, realize complete multiprocessor hardware the Realtime Operating System Nucleus.It comprises following sub-step:
(11.1), in multiple processor cores, comprise one or more uniprocessor kernels, message queue manager between counting semaphore manager and several processors between register interface module, several processors.In each uniprocessor kernel, comprise a register interface module, a controller lock module, task manager, several interrupt managers, several counting semaphore managers, several mutex amount managers and several message queue manager.
(11.2) in the uniprocessor kernel, occur that processor command, asynchronous event task are waken up, when task scheduling request, system time sheet ticktock event, controller lock module in the uniprocessor kernel is sent to application, after locking by the corresponding controllers complete operation.When processor inter-register interface module receives processor command, need to send application to the controller lock module of all processors, after all locking successfully, could be by the corresponding controllers complete operation.
Below enumerate the instantiation of the componentization hardware real time operating system of two the present invention's realizations.As shown in Figure 1, on the fpga chip that instance system is Cyclone IV EP4CE115F29C7 in the model of altera corp, realize.Software interface operates on NIOS II soft-core processor, and hardware-core exists in the mode of external unit, mutual by Avalon system bus and processor.As shown in Figure 2, on the fpga chip that instance system is Spartan 6 XC6SLX16 in the model of Xilinx company, realize.Software interface operates on two Microblaze soft-core processors, and hardware-core exists in the mode of external unit, mutual by two AXI-Stream series flow buses, AXI bus and processor.
Table 1 is the componentization hardware real time operating system of the present invention's realization and the Character Comparison of some existing hardware real time operating systems.Wherein Sierra Kernel is unique commercialization hardware real time operating system, HartOS is the hardware real time operating system of increasing income of Syddansk Uni's realization in 2011, and UCOS II real time operating system Hardware is domestic more popular hardware real time operating system implementation.
Table 1:
From table 1, use benefit of the present invention to be:, system performance, higher than the unify performance of part Hardware real time operating system of pure software real-time oss, system real time can be ensured better (1); (2), from system resources consumption, owing to adopting the componentization mode, cutting flexibly, can be than other hardware real time operating system consumption hardware resource still less; (3) system reliability, with stack pointer inspection, house dog overtimely reset, mutex amount Deadlock Detection and strict processor command parameter testing, can guarantee well the reliability of system; (4), from the system expandability and Scalability, owing to adopting the componentization mode, between system function module, the degree of coupling is very low, therefore can be expanded and cutting functional module as required, number of resources is configured neatly; (5) the system reusability, owing to adopting the componentization mode, therefore can change neatly the register interface module, make it be applicable to different interface between software and hardware modes, have than the highland reusability; (6) owing to adopting the componentization mode, system configurability and extensibility, far above other hardware real time operating system, even can compare favourably with the pure software real time operating system; (7) system can be used for multi-processor environment, adapts to industry Future Development needs.
Claims (1)
1. the implementation method of a componentization hardware real time operating system, is characterized in that, the method comprises the steps:
(1) real time operating system is divided into to hardware-core and software interface two parts, and definite software and hardware communication mode; It comprises following sub-step:
(1.1) using hardware-core as coprocessor or external unit exist, when as coprocessor, software and hardware communicates by the general-purpose register of processor, when as external unit, software and hardware communicates by system bus;
(1.2) hardware-core becomes hardware command by the Realtime Operating System Nucleus function package, and hardware command comprises command number, input data, rreturn value, output data etc.; Software interface further is encapsulated as system call by hardware command, offers application program and uses;
(1.3) except hardware command communication, hardware-core also provides two look-at-mes to processor, and one for the task handover request, and one for the abnormality processing application; Software interface is responsible for carrying out the processing that hardware-core is sent interruption, when task handover request look-at-me is brought, carries out the task switching, when abnormality processing application look-at-me arrives, carries out abnormality processing; The abnormality processing application is processed except software, can also directly trigger processor reset;
(2) in hardware-core, determine the componentization implementation of each functional module of the Realtime Operating System Nucleus, make its adjustment neatly, cutting and expansions etc. as required; It comprises following sub-step:
(2.1) hardware-core is used the register interface module as the interface between software interface and the Realtime Operating System Nucleus functional module; The hardware command that the register interface module is imported software interface into, be converted to the processor command interface communication of the corresponding function module;
(2.2) the Realtime Operating System Nucleus functional module is connected on intermodule command interface bus by the intermodule command interface of standard, and the core functions module assignment of each instantiation has an independently address, to carry out the intermodule command communication; On bus, the same time only allows one a main equipment and one to be arranged from equipment, and main equipment is initiated order, from the equipment fill order;
(2.3) every class real time operating system functional module includes following a few part-structure: storer, controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface; Wherein, storer is mainly realized by the ram in slice of FPGA; The various command interface is for module and outside communicating by letter; All actions under controller is controlled of all parts in module, controller is realized with finite state machine;
(2.4) hardware-core is used a controller lock module to carry out synchronously all the Realtime Operating System Nucleus functional modules, when a processor command, timeslice ticktock, asynchronous wake events or task scheduling request arrive, can send request to the controller lock module, request of the every secondary response of controller lock module, the controller of each real time operating system functional module can complete corresponding solicit operation according to the controller lock state;
(2.5), in a uniprocessor hardware-core, realize a task manager, several interrupt managers, several counting semaphore managers, several mutex amount managers and several message queue manager;
(3), in hardware-core, realize the hardware task manager; It comprises following sub-step:
(3.1) the hardware task manager is divided into to following submodule: task memory, task controller, clock generator, WatchDog Timer, task dispatcher, processor command interface, intermodule order host device interface, intermodule order are from equipment interface;
(3.2) realize task memory: the controll block information of each task of storage in task memory comprises that task status, task original priority, task succession priority, the actual priority of task, task blocking resource number, task delay time sheet number, task wheel turn timeslice number, task stack pointer lower limit, the task stack pointer upper limit, task stack pointer; In addition, task memory also comprises the tree-shaped priority comparer based on the actual priority of task, can select the limit priority task bitmap in the particular task bitmap; When being input as the ready task bitmap, be output as the ready task bitmap of limit priority, realize the task preemption scheduling of Priority-based;
(3.3) realize clock generator, clock generator arranges according to timeslice size, every the time of timeslice size, sends a tick_sig rising edge signal, with the delay data of new task more; After the wheel of current task turns timeslice and is finished, send the task scheduling request, to trigger the same priority task robin scheduling of time-based sheet;
(3.4) realize WatchDog Timer; The house dog count value subtracts one at each tick_sig, sends abnormality processing application look-at-me to zero the time, and the house dog count value does not enable when being set to zero;
(3.5) realize task dispatcher; Task dispatcher receives the ready task bitmap of the limit priority of task memory output, and store tasks wheel transposition figure, with the task preemption scheduling that realizes Priority-based and the same priority task robin scheduling of time-based sheet; Task dispatcher output current task number and limit priority ready task number, and send task handover request look-at-me when current task is not the limit priority ready task;
(3.6) realize task controller; The action of all the other submodules in task controller control task manager; It realizes by finite state machine, can complete the task delayed data adjusting operation that order, task-scheduling operation, tick_sig that processor command, other module import into trigger;
(3.7) task manager is realized following processor command: task creation order, task delete command, task suspension order, task recovery order, task time delay order, task time delay mandatum cassatorium, task priority are revised orders, task is abdicated processor command, the task wheel turns the timeslice number order, task control block (TCB) querying command, task manager reset command are set;
(3.8) task manager is realized following intermodule order: selection task wake command in task blocking order, the task blocking order with time-out time, task wake command, task blocking bitmap, the task blocking order based on the mutex amount, based on the mutex amount with the order of time-out time task blocking, task wake command based on the mutex amount;
(4), in hardware-core, realize the hardware interrupts manager; It comprises following sub-step:
(4.1) the hardware interrupts manager is divided into to following submodule: interrupt storage, interruptable controller, asynchronous event maker, processor command interface, intermodule order host device interface, intermodule order are from equipment interface;
(4.2) realize interrupt storage; In interrupt storage, the controll block information of each asynchronous event of storage, comprise the task number be blocked on asynchronous event;
(4.3) realize the asynchronous event maker; Comprise 32 external interrupt input signals in the asynchronous event maker, can be set as rising edge triggering or negative edge and trigger; The asynchronous event sign can shielding, set and removing; The asynchronous event sign is understood set when externally the interrupting input signal meets trigger condition; When the task of obstruction is arranged on the asynchronous event of set, can send asynchronous event task wake request to the controller lock module, the application respective handling;
(4.4) realize interruptable controller; Interruptable controller is controlled the action of all the other submodules in interrupt manager; It realizes by finite state machine, can complete order, asynchronous event task wake operation that processor command, other module import into;
(4.5) interrupt manager is realized following processor command: on asynchronous event, on task blocking order, asynchronous event, task blocking order, asynchronous event mask off command, the asynchronous event with time-out time shields reading order, the asynchronous event triggering mode arranges order, asynchronous event triggering mode reading order, the order of asynchronous event flag set, asynchronous event sign clear command, asynchronous event sign reading order, interrupt control block querying command, interrupt manager reset command;
(4.6) interrupt manager is realized following intermodule order: the task blocking mandatum cassatorium;
(5), in hardware-core, realize hardware counting semaphore manager; It comprises following sub-step:
(5.1) hardware counting semaphore manager is divided into to following submodule: counting semaphore storer, count signal amount controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface;
(5.2) realize the counting semaphore storer; The controll block information of each counting semaphore of storage in the counting semaphore storer, comprise the semaphore count value, block the task bitmap;
(5.3) realize the count signal amount controller; The count signal amount controller is controlled the action of all the other submodules in the counting semaphore manager; It is realized by a finite state machine, can complete the order that processor command, other module import into;
(5.4) the counting semaphore manager is realized following processor command: on task blocking order on counting semaphore establishment order, counting semaphore delete command, counting semaphore, counting semaphore with task blocking order, counting semaphore release command, counting semaphore controll block querying command, the counting semaphore manager reset command of time-out time;
(5.5) the counting semaphore manager is realized following intermodule order: the task blocking mandatum cassatorium;
(6), in hardware-core, realize hardware mutex amount manager; It comprises following sub-step:
(6.1) hardware mutex amount manager is divided into to following submodule: mutex amount storer, task support relational storage device, mutex amount controller, processor command interface, intermodule order host device interface, intermodule order from equipment interface;
(6.2) realize mutex amount storer; The controll block information of each mutex amount of storage in mutex amount storer, comprise mutex amount owner task number, block the task bitmap;
(6.3) realize task support relational storage device; Task is supported storage in the relational storage device and is blocked because the mutex amount is occupied the task support relation caused, and the task of the transmission of deriving is supported relation; Task support relation refers to, is blocked in the task that task support on certain mutex amount occupies this mutex amount; Transmitting of task is supported relation, refers to that task B supports task C if task A supports task B, and task A also supports task C; For each task, its task bitmap supported in record, and task is inherited the priority of the task of supporting it, to realize the priority inheritance agreement that prevents that priority from reversing; By task, support relation derivation to go out transmission tasks and support relation, if exist symmetrical transmission tasks to support relation, mean mutex amount application deadlock, can send asynchronous process application look-at-me;
(6.4) realize the mutex amount controller; The mutex amount controller is controlled the action of all the other submodules in mutex amount manager; It realizes by finite state machine, can complete the order that processor command, other module import into;
(6.5) mutex amount manager is realized following processor command: on task blocking order on mutex amount establishment order, mutex amount delete command, mutex amount, mutex amount with task blocking order, the release command of mutex amount, mutex amount controll block querying command, the mutex amount manager reset command of time-out time;
(6.6) mutex amount manager is realized following intermodule order: the task blocking mandatum cassatorium;
(7), in hardware-core, realize the hardware message queue manager; It comprises following sub-step:
(7.1) the hardware message queue manager is divided into to following submodule: message queue storer, message queue controller, processor command interface, intermodule order host device interface, intermodule order are from equipment interface;
(7.2) realize the message queue storer; Store the controll block information of each message queue in the message queue storer, comprise the task blocking bitmap of message queue buffer zone, message queue read pointer, message queue write pointer, message queue;
(7.3) realize the message queue controller; The action of all the other submodules in message queue controller control message queue management device; It realizes by finite state machine, can complete the order that processor command, other module import into;
(7.4) message queue manager realizes following processor command: on message queue establishment order, message queue delete command, message queue, read on information order, message queue to read on information order, message queue to write information order, message queue controll block querying command, message queue manager reset command with time-out time;
(7.5) message queue manager realizes following intermodule order: the task blocking mandatum cassatorium;
(8) by comprising a plurality of uniprocessor hardware-core, realize the operation system function of multiprocessor; It comprises following sub-step:
(8.1) the uniprocessor hardware-core is encapsulated; Each uniprocessor hardware-core, comprise a register interface module, a controller lock module, task manager, several interrupt managers, several counting semaphore managers, several mutex amount managers and several message queue manager;
(8.2) according to configuration, one or more uniprocessor hardware-core of instantiation in hardware, each uniprocessor hardware-core has independently parameter configuration, thereby realizes the Multiprocessor operation system hardware-core;
(9), in the multiprocessor hardware-core, realize counting semaphore manager between processor; It comprises following sub-step:
(9.1) counting semaphore manager between processor is divided into to following submodule: count signal amount controller, processor command interface, intermodule order host device interface between counting semaphore storer, processor between processor;
(9.2) realize counting semaphore storer between processor; Between processor, the controll block information of each counting semaphore of storage in the counting semaphore storer, comprise the limit priority that blocks task on obstruction task bitmap on semaphore count value, each processor, each processor;
(9.3) realize count signal amount controller between processor; The action of all the other submodules in the counting semaphore manager between count signal amount controller control processor between processor; It is realized by a finite state machine, can complete processor command;
(9.4) between processor, the counting semaphore manager is realized following processor command: between processor counting semaphore create order, counting semaphore manager reset command between counting semaphore controll block querying command, processor between counting semaphore release command between task blocking order on counting semaphore, processor, processor between counting semaphore delete command, processor between processor;
(10), in the multiprocessor hardware-core, realize message queue manager between processor; It comprises following sub-step:
(10.1) message queue manager between processor is divided into to following submodule: message queue controller, processor command interface, intermodule order host device interface between message queue storer, processor between processor;
(10.2) realize message queue storer between processor; Between processor, the controll block information of each message queue of storage in the message queue storer, comprise the limit priority that blocks task on obstruction task bitmap on message queue buffer zone, message queue read pointer, message queue write pointer, each processor, each processor;
(10.3) realize message queue controller between processor; The action of all the other submodules in message queue manager between message queue controller control processor between processor; It is realized by a finite state machine, can complete processor command;
(10.4) between processor, message queue manager realizes following processor command: between processor, the count message queue creates and orders, reads between information order, processor to write on message queue on message queue between message queue delete command, processor between processor between information order, processor message queue manager reset command between message queue controll block querying command, processor;
(11) realize complete multiprocessor hardware the Realtime Operating System Nucleus; It comprises following sub-step:
(11.1), in multiple processor cores, comprise one or more uniprocessor kernels, message queue manager between counting semaphore manager and several processors between register interface module, several processors; In each uniprocessor kernel, comprise a register interface module, a controller lock module, task manager, several interrupt managers, several counting semaphore managers, several mutex amount managers and several message queue manager;
(11.2) in the uniprocessor kernel, occur that processor command, asynchronous event task are waken up, when task scheduling request, system time sheet ticktock event, controller lock module in the uniprocessor kernel is sent to application, after locking by the corresponding controllers complete operation; When processor inter-register interface module receives processor command, need to send application to the controller lock module of all processors, after all locking successfully, completed the operation be applied by corresponding controllers.
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