CN103309762B - Unit exception disposal route and device - Google Patents
Unit exception disposal route and device Download PDFInfo
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- CN103309762B CN103309762B CN201310251958.3A CN201310251958A CN103309762B CN 103309762 B CN103309762 B CN 103309762B CN 201310251958 A CN201310251958 A CN 201310251958A CN 103309762 B CN103309762 B CN 103309762B
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Abstract
The present invention proposes unit exception disposal route and device.Method comprises: device discovery self creates anomalous event, wherein, carries the order code of abnormal cause and triggering anomalous event in anomalous event; Equipment judges whether abnormal cause is access illegal address, if, obtain the real instruction triggering anomalous event, judge whether this instruction is read write command, if read write command, obtain from this instruction and trigger the address of anomalous event, judge that whether this address is the legal address of system configuration, if so, next instruction in process internal memory is continued; Otherwise, carry out abnormality processing.The present invention can reduce unit exception and crash.
Description
Technical field
The present invention relates to system exception processing technology field, particularly relate to unit exception disposal route and device.
Background technology
Microprocessor (MIPS, MicroprocessorwithoutInterlockedPipedStages) framework without inner interlocked pipelining-stage is the processor architecture that one takes Jing Ke Cao Neng (RISC, ReducedInstructionSetComputing).Work as equipment, such as multi-core router adopts based on MIPS CPU (central processing unit) (CPU, during linux system CentralProcessingUnit), when the CPU of this router accesses some address, such as there is no the interconnected (PCI of corresponding peripheral component, during certain section of PCI address space PeripheralComponentInterconnection) blocked, can extremely system in case of system halt be caused to be restarted by trigger address.Wherein, this address causing system in case of system halt to be restarted may be legal address, can normally access, but become illegal address after being through some operation, after such as certain pci card being extracted from equipment, the CPU of router does not process in time, causes that CPU is follow-up still can access this PCI address space, thus triggers abnormal.
Usually for the event that the pci card etc. on multi-core router is pulled out, the CPU of router can process, to make not visit again this PCI address space, but due to the existence of processing time difference, some special module, such as timer, still can conduct interviews, these access finally can be prohibited, but its system in case of system halt caused is unnecessary.
The following scheme of usual employing evades illegal address access problem: after address space becomes illegal address, notifies that each CPU does not conduct interviews to this address by arranging some access flag.
There is following shortcoming in the program:
For device for multi-core, because processing pci card etc. by control CPU in interruption is pulled out event usually, if the request being interrupted the access illegal address of interrupting have passed the inspection of access flag, then, after interruption recovers, still can continue to access this illegal address; Or, if data CPU has started the request processing access illegal address before pci card etc. is pulled out, and have passed the inspection of access flag, then can directly start to access this illegal address.
Summary of the invention
The invention provides unit exception disposal route and device, crash to reduce the unit exception caused by access illegal address.
Technical scheme of the present invention is achieved in that
A kind of unit exception disposal route, the method comprises:
Device discovery self creates anomalous event, wherein, carries the order code of abnormal cause and triggering anomalous event in anomalous event;
Equipment judges whether abnormal cause is access illegal address, if, obtain the real instruction triggering anomalous event, judge whether this instruction is read write command, if read write command, obtain from this instruction and trigger the address of anomalous event, judge that whether this address is the legal address of system configuration, if so, next instruction in process internal memory is continued; Otherwise, carry out abnormality processing.
The described real instruction obtaining triggering anomalous event comprises:
Judging whether the order code in anomalous event is jump instruction, if so, from postponing next instruction obtaining this jump instruction groove, determining that this instruction postponed in groove is that the real of anomalous event touches originator; Otherwise, determine that the corresponding instruction of order code of carrying in anomalous event is that the real of anomalous event touches originator.
When determining that the order code in anomalous event is jump instruction, and when the address of determining to trigger anomalous event is the legal address of system configuration, next instruction in described continuation process internal memory comprises:
Calculate redirect return address according to jump instruction, go to the instruction that in internal memory, this redirect return address is corresponding, start to process this instruction.
Described equipment is adopt the equipment based on the linux system of MIPSCPU.
A kind of unit exception treating apparatus, comprising:
Anomalous event sending module: find that place equipment creates anomalous event, carries the order code of abnormal cause and triggering anomalous event, this anomalous event is sent to abnormal judge module in anomalous event;
Abnormal judge module: receive anomalous event, judge whether abnormal cause is access illegal address, if, obtain the real instruction triggering anomalous event, judge whether this instruction is read write command, if read write command, the address of triggering anomalous event is obtained from this instruction, judge that whether this address is the legal address of system configuration, if so, continue next instruction in process internal memory; Otherwise, determine to carry out abnormality processing.
Described abnormal judge module is further used for, when obtaining the real instruction triggering anomalous event, judge whether the order code in anomalous event is jump instruction, if, from postponing next instruction obtaining this jump instruction groove, determine that this instruction postponed in groove is that the real of anomalous event touches originator; Otherwise, determine that the corresponding instruction of order code of carrying in anomalous event is that the real of anomalous event touches originator.
Described abnormal judge module is further used for, when determining that the order code in anomalous event is jump instruction, and when determining that triggering the address of anomalous event is the legal address of system configuration, described next instruction continued in process internal memory comprises: calculate redirect return address according to jump instruction, go to the instruction that in internal memory, this redirect return address is corresponding, start to process this instruction.
Described device is positioned on router.
Described router adopts the linux system based on MIPSCPU.
Visible, the present invention can reduce the unit exception caused by access illegal address and crash, and improves the stability of device systems.
Accompanying drawing explanation
The unit exception process flow figure that Fig. 1 provides for the embodiment of the present invention;
The unit exception process flow figure that Fig. 2 provides for further embodiment of this invention;
The unit exception process flow figure that Fig. 3 provides for another embodiment of the present invention;
The composition schematic diagram of the unit exception treating apparatus that Fig. 4 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and the specific embodiments, the present invention is further described in more detail.
The unit exception process flow figure that Fig. 1 provides for the embodiment of the present invention, as shown in Figure 1, its concrete steps are as follows:
Step 101: device discovery self creates anomalous event, wherein, carries the order code of abnormal cause and triggering anomalous event in anomalous event.
Step 102: equipment judges whether abnormal cause is access illegal address, if so, performs step 103; Otherwise, perform step 106.
Step 103: equipment obtains the real instruction triggering anomalous event, judges whether this instruction is read write command, if so, performs step 104; Otherwise, perform step 106.
Step 104: equipment obtains and triggers the address of anomalous event from read write command, judges that whether this address is the legal address of system configuration, if so, performs step 105; Otherwise, perform step 106.
Step 105: equipment continues next instruction in process internal memory, and this flow process terminates.
Step 106: equipment carries out abnormality processing.
The unit exception process flow figure that Fig. 2 provides for further embodiment of this invention, as shown in Figure 2, its concrete steps are as follows:
Step 201: device discovery self creates anomalous event, carries the order code of abnormal cause and triggering anomalous event in anomalous event.
Step 202: equipment judges whether abnormal cause is access illegal address, if so, performs step 203; Otherwise, perform step 206.
Step 203: equipment, according to the order code in anomalous event, judges whether this instruction is read write command, if so, performs step 204; Otherwise, perform step 206.
Step 204: equipment is read access address from this order code, judges that whether this address is the legal address of system configuration, if so, performs step 205; Otherwise, perform step 206.
The legal address of system configuration can be the permission reference address of system initial configuration.Wherein, the memory address space in equipment can be assigned with in advance, and some address space is configured to allow access, and other is not configured to allow the address space of access to be then whenever do not allow access.When allowing the pci card corresponding to address space of access etc. not in place, stopping continuing this address space of access, and system in case of system halt need not be caused to restart; But the access behavior of any address space for not being configured to permission access being true positive illegal act, all can causing equipment deadlock and restarting.
Step 205: equipment continues next instruction in process internal memory, and this flow process terminates.
Step 206: equipment sends exception handling instruction to the abnormality processing module of self, carry this anomalous event mark in this instruction, abnormality processing module receives this instruction, according to this anomalous event of existing procedure process.
Equipment in the present invention can adopt the linux system based on MIPSCPU, and equipment can be router.
It should be noted that; CPU due to equipment is the instruction in sequential processes internal memory; and when present instruction is jump instruction; the CPU of some type, such as MIPSCPU, first can perform next instruction of jump instruction usually; this next instruction enters and postpones in groove; when postponing the instruction triggers anomalous event in groove, CPU can be defaulted as this anomalous event and remain by the present instruction in internal memory, and namely jump instruction triggers.Under the circumstances, the present invention provides following embodiment:
The unit exception process flow figure that Fig. 3 provides for another embodiment of the present invention, as shown in Figure 3, its concrete steps are as follows:
Step 301: device discovery self creates anomalous event, carries the order code of abnormal cause and triggering anomalous event in anomalous event.
Step 302: equipment judges whether abnormal cause is access illegal address, if so, performs step 303; Otherwise, perform step 309.
Step 303: equipment judges whether the order code of carrying in anomalous event is jump instruction, if so, performs step 304; Otherwise, perform step 305.
Step 304: equipment, from postponing next instruction obtaining this jump instruction groove, is determined that this instruction postponed in groove is that the real of anomalous event touches originator, gone to step 306.
Step 305: the corresponding instruction of the order code in equipment determination anomalous event is that the real of anomalous event touches originator, performs step 306.
Step 306: equipment judges whether the instruction triggering anomalous event is read write command, if so, performs step 307; Otherwise, perform step 309.
Step 307: equipment reads address from read write command, judges that whether this address is the legal address of system configuration, if so, performs step 308; Otherwise, perform step 309.
Step 308: equipment calculates redirect return address according to the information that jump instruction is carried, goes to the instruction that in internal memory, this redirect return address is corresponding, and start to process this instruction, this flow process terminates.
Step 309: equipment sends exception handling instruction to the abnormality processing module of self, carry this anomalous event mark in this instruction, abnormality processing module receives this instruction, according to this anomalous event of existing procedure process.
Below provide application example of the present invention:
Be provided with a pci card to extract from router, perform an instruction in internal memory as CPU, this instruction be for address space corresponding to this pci card read instruction time, because CPU searches less than equipment corresponding to this address space, therefore, can think that this address space is illegal, thus produce anomalous event; Now, CPU carries out following detailed process:
01) first CPU judges whether abnormal cause is access illegal address, is judged as YES, performs step 02.
02) CPU is according to the order code in anomalous event, judges that whether this instruction is for reading instruction or write command, is judged as YES, and performs step 03.
03) CPU reads to read address instruction from this, judge that whether this address is the legal address of system configuration further, CPU finds the corresponding pci card in this address, and this pci card is not in place, then due to: access the permission reference address space that address space corresponding to the pci card that is pulled out is system initial configuration, should not cause system in case of system halt, thus determine not to be illegal act, perform step 04.
04) CPU determines continue normal work, then continue to perform next instruction in internal memory.
As can be seen from the above embodiment of the present invention:
In the present invention, anomalous event one produces, and will carry out illegal address access process, therefore, avoids the follow-up access behavior to illegal address.
The composition schematic diagram of the unit exception treating apparatus that Fig. 4 provides for the embodiment of the present invention, as shown in Figure 4, it mainly comprises: anomalous event sending module 41, abnormal judge module 42 and abnormality processing module 43, wherein:
Anomalous event sending module 41: find that place equipment creates anomalous event, carries the order code of abnormal cause and triggering anomalous event, this anomalous event is sent to abnormal judge module 42 in anomalous event.
Abnormal judge module 42: receive the anomalous event that anomalous event sending module 41 is sent, judge whether abnormal cause is access illegal address, if, obtain the real instruction triggering anomalous event, judge whether this instruction is read write command, if read write command, the address of triggering anomalous event is obtained from this instruction, judge that whether this address is the legal address of system configuration, if so, continue next instruction in process internal memory; Otherwise, send this anomalous event to abnormality processing module 43.
Abnormal judge module 42 is further used for, when obtaining the real instruction triggering anomalous event, judge whether the order code in anomalous event is jump instruction, if, from postponing next instruction obtaining this jump instruction groove, determine that this instruction postponed in groove is that the real of anomalous event touches originator; Otherwise, determine that the corresponding instruction of order code of carrying in anomalous event is that the real of anomalous event touches originator.
Abnormal judge module 42 is further used for, when determining that the order code in anomalous event is jump instruction, and when determining that triggering the address of anomalous event is the legal address of system configuration, described next instruction continued in process internal memory comprises: calculate redirect return address according to jump instruction, go to the instruction that in internal memory, this redirect return address is corresponding, start to process this instruction.
Abnormality processing module 43: receive the anomalous event that abnormal judge module 42 is sent, abnormality processing is carried out to this anomalous event.
In actual applications, Fig. 4 shown device can be positioned on router, and this router can adopt the linux system based on MIPSCPU.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (9)
1. a unit exception disposal route, is characterized in that, the method comprises:
Device discovery self creates anomalous event, wherein, carries the order code of abnormal cause and triggering anomalous event in anomalous event;
Equipment judges whether abnormal cause is access illegal address, if, obtain the real instruction triggering anomalous event, judge whether this instruction is read write command, if read write command, obtain from this instruction and trigger the address of anomalous event, judge that whether the address of this triggering anomalous event is the legal address of system configuration, if so, next instruction in process internal memory is continued; Otherwise, carry out abnormality processing.
2. method according to claim 1, is characterized in that, the described real instruction obtaining triggering anomalous event comprises:
Judging whether the order code in anomalous event is jump instruction, if so, from postponing next instruction obtaining this jump instruction groove, determining that next instruction of this jump instruction postponed in groove is that the real of anomalous event touches originator; Otherwise, determine that the corresponding instruction of order code of carrying in anomalous event is that the real of anomalous event touches originator.
3. method according to claim 2, is characterized in that, when determining that the order code in anomalous event is jump instruction, and when the address of determining to trigger anomalous event is the legal address of system configuration, next instruction in described continuation process internal memory comprises:
Calculate redirect return address according to jump instruction, go to the instruction that in internal memory, this redirect return address is corresponding, start to process this instruction.
4. according to the arbitrary described method of claims 1 to 3, it is characterized in that, described equipment is adopt the equipment based on the linux system of MIPSCPU.
5. a unit exception treating apparatus, is characterized in that, comprising:
Anomalous event sending module: find that place equipment creates anomalous event, carries the order code of abnormal cause and triggering anomalous event, this anomalous event is sent to abnormal judge module in anomalous event;
Abnormal judge module: receive anomalous event, judge whether abnormal cause is access illegal address, if, obtain the real instruction triggering anomalous event, judge whether this instruction is read write command, if read write command, the address of triggering anomalous event is obtained from this instruction, judge that whether the address of this triggering anomalous event is the legal address of system configuration, if so, continue next instruction in process internal memory; Otherwise, determine to carry out abnormality processing.
6. device according to claim 5, it is characterized in that, described abnormal judge module is further used for, when obtaining the real instruction triggering anomalous event, judge whether the order code in anomalous event is jump instruction, if so, from postponing next instruction obtaining this jump instruction groove, determine that next instruction of this jump instruction postponed in groove is that the real of anomalous event touches originator; Otherwise, determine that the corresponding instruction of order code of carrying in anomalous event is that the real of anomalous event touches originator.
7. device according to claim 5, it is characterized in that, described abnormal judge module is further used for, when determining that the order code in anomalous event is jump instruction, and when determining that triggering the address of anomalous event is the legal address of system configuration, described next instruction continued in process internal memory comprises: calculate redirect return address according to jump instruction, go to the instruction that in internal memory, this redirect return address is corresponding, start to process this instruction.
8. device according to claim 5, is characterized in that, described device is positioned on router.
9. device according to claim 8, is characterized in that, described router adopts the linux system based on MIPSCPU.
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| CN105988905A (en) * | 2015-02-12 | 2016-10-05 | 中兴通讯股份有限公司 | Exception processing method and apparatus |
| CN105354104B (en) * | 2015-10-22 | 2019-03-26 | 上海华为技术有限公司 | A kind of device and method positioning illegal address |
| CN107506638B (en) * | 2017-08-09 | 2020-10-16 | 南京大学 | Kernel control flow abnormity detection method based on hardware mechanism |
| CN113424160B (en) * | 2019-03-30 | 2024-01-30 | 华为技术有限公司 | Processing method, processing device and related equipment |
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| TW200402634A (en) * | 2002-08-05 | 2004-02-16 | Osaka Ind Promotion Org | Data processing method, data processing device, computer program and recording medium |
| CN101567810A (en) * | 2008-11-11 | 2009-10-28 | 武汉虹信通信技术有限责任公司 | Method for realizing self-detection of hot-plug board card |
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Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: NEW H3C TECHNOLOGIES Co.,Ltd. Address before: 310053 Hangzhou hi tech Industrial Development Zone, Zhejiang province science and Technology Industrial Park, No. 310 and No. six road, HUAWEI, Hangzhou production base Patentee before: HANGZHOU H3C TECHNOLOGIES Co.,Ltd. |
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Effective date of registration: 20230615 Address after: 310052 11th Floor, 466 Changhe Road, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: H3C INFORMATION TECHNOLOGY Co.,Ltd. Address before: 310052 Changhe Road, Binjiang District, Hangzhou, Zhejiang Province, No. 466 Patentee before: NEW H3C TECHNOLOGIES Co.,Ltd. |