CN105988905A - Exception processing method and apparatus - Google Patents
Exception processing method and apparatus Download PDFInfo
- Publication number
- CN105988905A CN105988905A CN201510076615.7A CN201510076615A CN105988905A CN 105988905 A CN105988905 A CN 105988905A CN 201510076615 A CN201510076615 A CN 201510076615A CN 105988905 A CN105988905 A CN 105988905A
- Authority
- CN
- China
- Prior art keywords
- exception
- address
- pci
- instruction
- abnormal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
Abstract
The invention provides an exception processing method and apparatus. The method comprises the steps of detecting whether an exception occurs in a process of accessing a PCI-E storage memory space or not; if yes, setting a return value corresponding to an exception instruction of causing the exception to be an illegal value; and taking a next address of the exception instruction as a return address of the current exception. With the adoption of the technical scheme provided by the method and apparatus, the problems of process stop caused by occurrence of the exception in the process of accessing a pcie memory address and system crash due to endless loop in related technologies are solved, so that the robustness and survivability of a system are improved.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of abnormality eliminating method and device.
Background technology
Peripheral interconnection standard (Peripheral Component Interconnect Express, referred to as PCI-E) is
A kind of novel bus standard and interface, be the third generation PCI being referred to as " 3GIO " being announced in calendar year 2001 by Intel
Bus.PCI-E belongs to high speed serialization point-to-point binary channels high bandwidth transmission, and the equipment being connected distribution exclusively enjoys bandwidth chahnel,
Share bus bandwidth, mainly support active power management, error reporting, end-to-end reliability transmission, hot plug with
And the function such as service quality (Quality of Service, referred to as QoS).
Defining four kinds of address spaces in PCI-E, they are memory, I/O, configuration and message respectively
Space.In PCI-E architectural framework, accessing does not has to produce exception during memory bank corresponding memory address.For
Different processor platform, slightly can some differences in the processing method to this type of exception.
Central processing unit (PerPerformance Optimization With Enhanced at reduced instruction set computer framework
-Performance Computing, is called for short POWERPC) under processor platform, central processing unit (Central Processing
After Unit, referred to as CPU send the instruction in a read access PCI-E memory space, processor first passes through local
Local address address during access windows will instruct is mapped on PCI-E controller.Then use
Processor address is mapped as the address in PCI-E territory by outbound ATMU windows.The transaction layer of PCI-E controller
PCI-E address after access type according to processor and mapping is constituted one or more TLP.Finally, these TLP
The opposite end of bus can be sent to by the link layer of PCI-E, physical layer, and wait the completion ENMES of opposite end originally
Secondary things.
When processor sends a read access, and in the case of the address of read access does not has memory bank corresponding, PCI-E
Controller can produce an exception because waiting completion message time-out.During in abnormality processing, process function
Can judge that the instruction triggering this exception is family state, or kernel state.If User space, abnormality processing will send
SIGBUS signal is to the process of User space.By process after receiving SIGBUS signal, the processing mode of acquiescence is to terminate
This process.If kernel state, user will be printed current processor environment information, and be exited exception.PCI-E visits
Depositing instruction to be not successfully performed by, after abnormal return, kernel will re-execute this instruction.This access instruction can access not
Have a memory bank corresponding PCI-E address, therefore also can exception throw again, kernel will eventually be caused to enter endless loop shape
State.
In the system supporting PCI-E hot plug, PCI-E device may at any time can power down or extract.Assume at some
The memory space of time processor continuous read access PCI-E device.The unexpected power down of PCI-E device during the visit.
Initiating if this visit is User space process, process will be killed.If accessing is that kernel state is initiated, system will be because of
It is unsuccessfully absorbed in endless loop for accessing specifically, so that complete machine down falls.
For in correlation technique, access and pcie memory address process occurring, process that is abnormal and that cause stops and is
System hangs, because of endless loop, the problem of falling, and not yet proposes effective solution.
Content of the invention
In order to solve above-mentioned technical problem, the invention provides a kind of abnormality eliminating method and device.
According to an aspect of the invention, it is provided a kind of abnormality eliminating method, comprising: test access peripheral interconnects
Whether standard PCI-E storage memory steric course there is exception；If it is, abnormal exceptional instructions will be caused
Corresponding return value is set to illegal value；Using the next address of described exceptional instructions as described current abnormal return
Address.
Preferably, whether test access PCI-E storage memory steric course there is exception, comprising: detect whether
There is situations below: when accessing described PCI-E storage memory space, owing to described PCI-E storage memory is empty
Between there is no corresponding storage entity and the exception that causes, and the operation address to be accessed of described exceptional instructions whether position
In the address realm in described PCI-E storage memory space；Wherein, testing result for being in the case of, determine
Access in described PCI-E storage memory steric course and occur extremely.
Preferably, described operation address is obtained one of in the following manner: judging described current exception as loading load
During the exception that class instruction causes, obtain described operation address from the instruction of described load class；Or post from machine check interrupts state
Storage MCSR reads described operation address.
Preferably, described operation address is obtained from the instruction of described load class, comprising: the lattice instructing according to described load class
Formula type, operation address described in appointment position acquisition corresponding with described Format Type from the instruction of described load class.
Preferably, the return value corresponding to described current abnormal exceptional instructions will be caused to be set to illegal value, comprising:
Corresponding data register writes described illegal value with described exceptional instructions.
Preferably, described exception at least includes one below: read number in abnormal, the bus loading that the instruction of load class causes
Abnormal according to bus.
According to another aspect of the present invention, additionally provide a kind of exception handling device, comprising: detection module, be used for examining
Survey and access in peripheral interconnection standard PCI-E storage memory steric course whether exception occurs；Module is set, uses
It in when occurring abnormal, is set to illegal value by causing the return value corresponding to abnormal exceptional instructions；Determining module, uses
In using the next address of described exceptional instructions as described current abnormal return address.
Preferably, for detecting whether there is situations below: access described PCI-E storage memory in described detection module
During space, the exception that causes owing to described PCI-E storage memory space does not has a corresponding storage entity, Yi Jisuo
Whether the operation address to be accessed stating exceptional instructions is positioned at the address realm in described PCI-E storage memory space；
Wherein, testing result for being in the case of, determine access described PCI-E storage memory steric course occurs different
Often.
Preferably, described device also includes, acquisition module, is used for obtaining described operation address, wherein, described acquisition mould
Block is additionally operable to, when judging the exception that described current exception causes as loading the instruction of load class, obtain from the instruction of described load class
Take described operation address；Or read described operation address from machine check interrupts status register MCSR.
Preferably, described acquisition module, is additionally operable to the Format Type instructing according to described load class, from described load class
Operation address described in appointment position acquisition corresponding with described Format Type in instruction.
By the present invention, use when occurring abnormal, using the next address of exceptional instructions as described current abnormal returning
Go back to address, and the return value of exceptional instructions is set to the technological means of illegal value, solve in correlation technique, access pcie
The process occurring exception in memory address process and causing stops and system hangs the problem of falling, Jin Erti because of endless loop
Robustness and the survivability of system are risen.
Brief description
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, the present invention
Schematic description and description be used for explaining the present invention, be not intended that inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart of abnormality eliminating method according to embodiments of the present invention；
Fig. 2 is the structured flowchart of the exception handling device according to the embodiment of the present invention；
Fig. 3 is another structured flowchart of the exception handling device according to the embodiment of the present invention；
The method that Fig. 4 is the use analysis instruction according to the preferred embodiment of the present invention is processed reads the abnormal place of pcie memory
The flow chart of reason method；
The register that Fig. 5 provides for the use powerpc platform architecture according to the preferred embodiment of the present invention realizes pcie
The abnormality processing of memory.
Detailed description of the invention
Below with reference to accompanying drawing and describe the present invention in detail in conjunction with the embodiments.It should be noted that in the feelings do not conflicted
Under condition, the embodiment in the application and the feature in embodiment can be mutually combined.
Other features and advantages of the present invention will illustrate in the following description, and, partly become from specification
It is clear that or understood by implementing the present invention.The purpose of the present invention and other advantages can be by the explanations write
Structure specifically noted in book, claims and accompanying drawing realizes and obtains.
In order to make those skilled in the art be more fully understood that the present invention program, attached below in conjunction with in the embodiment of the present invention
Figure, is clearly and completely described to the technical scheme in the embodiment of the present invention, it is clear that described embodiment is only
It is a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is common
The every other embodiment that technical staff is obtained under the premise of not making creative work, all should belong to the present invention and protect
The scope protected.
Providing a kind of abnormality eliminating method in the present embodiment, Fig. 1 is abnormality eliminating method according to embodiments of the present invention
Flow chart, as it is shown in figure 1, this flow process comprises the steps:
Whether step S102, occur different in test access peripheral interconnection standard PCI-E storage memory steric course
Often；
Step S104, if it is, will cause the return value corresponding to abnormal exceptional instructions to be set to illegal value；
Step S106, using the next address of above-mentioned exceptional instructions as above-mentioned current abnormal return address.
By each step above-mentioned, use when occurring abnormal, using the next address of exceptional instructions as described currently different
Normal return address, and the return value of exceptional instructions is set to illegal value technological means, solve correlation technique
In, access and pcie memory address process occurring, abnormal and that cause process stops and system because endless loop is hung
Problem, and then improve robustness and the survivability of system.
Alternatively, illegal value can be set in advance, in embodiments of the present invention preferably hexadecimal F.
For whether test access PCI-E storage memory steric course occurs abnormal can be by detecting whether to occur
Situations below: when accessing above-mentioned PCI-E storage memory space, owing to above-mentioned PCI-E storage memory space does not has
The exception having corresponding storage entity and causing, and whether the operation address to be accessed of above-mentioned exceptional instructions be positioned at
State in the address realm in PCI-E storage memory space；Wherein, testing result for being in the case of, determine access
Above-mentioned PCI-E storage memory steric course occur abnormal.
Wherein it is possible to obtain one of in the following manner aforesaid operations address: judging above-mentioned current exception as loading load
During the exception that class instruction causes, obtain aforesaid operations address from the instruction of above-mentioned load class；Or post from machine check interrupts state
Storage MCSR reads aforesaid operations address, owing to the Format Type of load class instruction exists multiple situation, therefore,
During the present invention implements, according to the Format Type of above-mentioned load class instruction, with above-mentioned form class from the instruction of above-mentioned load class
Type corresponding appointment position acquisition aforesaid operations address.
In embodiments of the present invention, above-mentioned exception at least includes one below: it is abnormal, total that loading load class instruction causes
On line, readout data bus is abnormal.
In sum, the technical scheme of the embodiment of the present invention, solves powerpc architecture processor read access without memory bank
Corresponding pcie memory address and the abnormal problem that causes, and then reach not kill User space process, it also is not result in
System hangs, because of endless loop, the method for falling, thus improves robustness and the survivability of system.
Illustrate abnormality eliminating method provided in above-described embodiment below in conjunction with one, but it is real to be not used in the restriction present invention
Execute example:
Step 1) determine the reason that cause abnormal
The reason that first have to judge to cause abnormal in abnormality processing flow process: i.e. processor have accessed does not has memory bank corresponding
The exception that pcie memory address causes.If it is not the case, abnormal proceeded by original flow process.Otherwise,
To be further processed for this exception
Step 2) judge abnormal address whether in pcie memory address realm
After determining abnormal cause, need to obtain the operation address causing exceptional instructions further, and by this address record
Get off.And obtain the memory address realm that in system, all pcie controllers are administered.Finally, it is judged that recorded
Whether exceptional instructions operation address belongs to pcie memory space.If it is, illustrate that this situation meets the present invention and implements
Example condition to be processed.Otherwise, by original abnormality processing flow performing.
Step 3) return value is filled to full F
After both the above situation and condition all meet, the return value of load memory instruction is filled to full F.And will
The abnormal address returning changes address under the instruction of exception throw into, and skips printing or the transmission of trailer record kernel exception
SIGBUS signal, to the operation of consumer process, directly returns.
The technique scheme using the embodiment of the present invention to be provided, simple and effective can prevent read access PCIe from producing
The process causing after exception is killed or system hangs the problem of falling.
It should be noted that for aforesaid each method embodiment, in order to be briefly described, therefore it is all expressed as a series of
Combination of actions, but those skilled in the art should know, the present invention is not limited by described sequence of movement,
Because according to the present invention, some step can use other orders or carry out simultaneously.Secondly, those skilled in the art are also
Should know, embodiment described in this description belongs to preferred embodiment, and involved action and module might not
It is essential to the invention.
Additionally provide a kind of exception handling device in the present embodiment, be used for realizing above-described embodiment and preferred embodiment,
Carried out repeating no more of explanation, below the module relating in this device had been illustrated.As used below,
Term " module " can realize the software of predetermined function and/or the combination of hardware.Although the dress described by following example
Put and preferably realize with software, but hardware, or the realization of the combination of software and hardware is also may and to be contemplated.
Fig. 2 is the structured flowchart of the exception handling device according to the embodiment of the present invention.As in figure 2 it is shown, this device includes:
Detection module 20, in test access peripheral interconnection standard PCI-E storage memory steric course whether
Occur abnormal；
Module 22 is set, is connected with detection module 20, for when occurring abnormal, abnormal exceptional instructions institute will be caused
Corresponding return value is set to illegal value；
Determining module 24, is connected with arranging module 22, for working as the next address of above-mentioned exceptional instructions as above-mentioned
Front abnormal return address.
By the integrated application of above-mentioned modules, use when occurring abnormal, using the next address of exceptional instructions as
Described current abnormal return address, and just cause the return value corresponding to above-mentioned exceptional instructions to be set to the skill of illegal value
Art means, solve in correlation technique, access and occur in pcie memory address process that process that is abnormal and that cause stops
And the problem that system because of endless loop extension, and then improve robustness and the survivability of system.
Fig. 3 is another structured flowchart of the exception handling device according to the embodiment of the present invention, wherein, detection module 20, uses
In detect whether occur situations below: access above-mentioned PCI-E storage memory space when, due to above-mentioned PCI-E storage
Memory space does not has corresponding memory cell and the exception that causes, and the operation to be accessed of above-mentioned exceptional instructions
Whether address is positioned at the address realm in above-mentioned PCI-E storage memory space；Wherein, the feelings being yes in testing result
Under condition, determine in access above-mentioned PCI-E storage memory steric course and occur extremely.
Alternatively, said apparatus also includes, acquisition module 26, is used for obtaining aforesaid operations address, wherein, acquisition module
26 are additionally operable to, when judging the exception that above-mentioned current exception causes as loading the instruction of load class, obtain from the instruction of above-mentioned load class
Take aforesaid operations address；Or from machine check interrupts status register MCSR, read aforesaid operations address.
Further, acquisition module 26, are additionally operable to the Format Type instructing according to above-mentioned load class, from above-mentioned load class
Appointment position acquisition aforesaid operations address corresponding with above-mentioned Format Type in instruction.
In order to be better understood from above-mentioned exception handling procedure, illustrate below in conjunction with preferred embodiment, but be not used in restriction
The protection domain of the embodiment of the present invention.
Describe in further detail below in conjunction with Fig. 4 and use the method for analysis instruction to solve to read the abnormal process of pcie memory
Method:
Step S402, abnormal entrance, the instruction of powerpc framework belongs to reduced instruction set computer, uses unified instruction coded system,
The length of instruction is equal, and the op-code in all instructions is positioned at same position forever.According to this instruction features,
Judgement to abnormal cause can take the mode of analysis instruction op-code to realize.
Step S404, retains structure struct pt_regs during by entering abnormal, extract and cause abnormal instruction
regs->nip.[0:5] bits of instruction is taken out, it is judged that whether this instruction belongs to the instruction of load class.If it is, perform
Process in step S406, otherwise step S410.
In order to obtain the operation address causing abnormal instruction, Load instruction is further analyzed.Can basis
Concrete Load instruction extracts instruction address to be accessed.The form difference that every kind of load instruction is left with, therefore wants root
Extract address according to different instructions.
Step S406, obtains pcie by linux kernel structure variable struct pci_controller hose_head and is covered
The address realm of lid.And whether the address extracted in checking procedure S404 belongs to this scope.If it is, step
Operation in S410, otherwise step S410.
Step S408, the information struct pt_regs remaining when obtaining abnormal, instruct causing abnormal load
Data register regs-> gpr [0] is filled to full F.And the sensing of the abnormal address returning is caused the lower address of exceptional instructions
Regs-> nip=(regs-> nip)+4；.When the program that backs within so again is run, program will not perceive abnormal sending out
Gave birth to, just look like load instruction obtain in pcie memory space value be full F illegal value the same.
Step S410, performs original abnormality processing flow process.
Another kind of implementation method is to obtain according to powerpc core storage and analyze abnormal information.Below in conjunction with Fig. 5
The abnormal process of the read access pcie memory using core register to realize is further described.
Step S502, in abnormal porch, judges abnormal type by obtaining MCSR register.If
MCSR [60]=1, then represent and create " Bus read data bus error " extremely.This type is abnormal；
Step S504, in powerpc framework, when occurring abnormal, MCAR register contain cause abnormal
The operated address of instruction.
Step S506, by reading MCAR (Machine Check Address Register) register, can obtain and draw
Play abnormal instruction operation address to be accessed, it is judged that whether aforesaid operations address is positioned at the address realm that pcie is covered,
If it is, the operation in step S506, otherwise step S508.
Step S508, the information struct pt_regs remaining when obtaining abnormal, instruct causing abnormal load
Data register regs-> gpr [0] is filled to full F.And the sensing of the abnormal address returning is caused the lower address of exceptional instructions
Regs-> nip=(regs-> nip)+4；.When the program that backs within so again is run, program will not perceive abnormal sending out
Gave birth to, just look like load instruction obtain in pcie memory space value be full F illegal value the same.
Step S508, performs original abnormality processing flow process.
In sum, the embodiment of the present invention has reached techniques below effect: solve in correlation technique, accesses pcie
The process occurring exception in memory address process and causing stops and system hangs the problem of falling, Jin Erti because of endless loop
Robustness and the survivability of system are risen.
In another embodiment, additionally providing a kind of software, this software is used for performing above-described embodiment and is preferable to carry out
Technical scheme described in mode.
In another embodiment, additionally providing a kind of storage medium, be stored with in this storage medium above-mentioned software, should
Storage medium includes but is not limited to: CD, floppy disk, hard disk, scratch pad memory etc..
It should be noted that term " first " in description and claims of this specification and above-mentioned accompanying drawing, " second "
Etc. being for distinguishing similar object, without being used for describing specific order or precedence.Should be appreciated that so use
Object can exchange in the appropriate case, in order to embodiments of the invention described herein can be with except here illustrating
Or the order enforcement beyond those describing.Additionally, term " includes " and " having " and their any deformation, it is intended that
Be to cover non-exclusive comprising, for example, contain the process of series of steps or unit, method, system, product or
Equipment is not necessarily limited to those steps or the unit clearly listed, but can include clearly not listing or for these
Other intrinsic steps of process, method, product or equipment or unit.
Obviously, those skilled in the art should be understood that each module of the above-mentioned present invention or each step can be with general
Computing device realizes, they can concentrate in single computing device, or is distributed in multiple computing device and is formed
Network on, alternatively, they can be realized by the executable program code of computing device, it is thus possible to by them
Storage is performed by computing device in the storage device, and in some cases, can hold with the order being different from herein
The shown or described step of row, or they are fabricated to respectively each integrated circuit modules, or by many in them
Individual module or step are fabricated to single integrated circuit module and realize.So, the present invention is not restricted to any specific hardware
Combine with software.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for the technology of this area
For personnel, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, that is made is any
Modification, equivalent, improvement etc., should be included within the scope of the present invention.
Claims (10)
1. an abnormality eliminating method, it is characterised in that include:
Whether test access peripheral interconnection standard PCI-E storage memory steric course there is exception；
If it is, the return value corresponding to abnormal exceptional instructions will be caused to be set to illegal value；
Using the next address of described exceptional instructions as current abnormal return address.
2. method according to claim 1, it is characterised in that test access PCI-E stores memory steric course
In whether there is exception, comprising:
Detect whether to occur situations below: when accessing described PCI-E storage memory space, due to described PCI-E
The exception that storage memory space does not has a corresponding storage entity and causes, and the visiting of described exceptional instructions
Whether the operation address asked is positioned at the address realm in described PCI-E storage memory space；Wherein, in detection
In the case that result is for being, determines in access described PCI-E storage memory steric course and occur extremely.
3. method according to claim 2, it is characterised in that obtain one of in the following manner described operation address:
When judging the exception that described current exception causes as loading the instruction of load class, obtain from the instruction of described load class
Take described operation address；Or
Read described operation address from machine check interrupts status register MCSR.
4. method according to claim 3, it is characterised in that obtain described operation address from the instruction of described load class,
Including:
The Format Type instructing according to described load class is corresponding with described Format Type from the instruction of described load class
Appointment position acquisition described in operation address.
5. method according to claim 1, it is characterised in that will cause corresponding to described current abnormal exceptional instructions
Return value be set to illegal value, comprising:
Write described illegal value in data register corresponding with described exceptional instructions.
6. the method according to any one of claim 1 to 5, it is characterised in that described exception at least includes one below:
Load the exception of readout data bus in abnormal, the bus that the instruction of load class causes.
7. an exception handling device, it is characterised in that include:
Detection module, in test access peripheral interconnection standard PCI-E storage memory steric course be
No generation is abnormal；
Module is set, for when occurring abnormal, being set to causing the return value corresponding to abnormal exceptional instructions
Illegal value；
Determining module, is used for the next address of described exceptional instructions as current abnormal return address.
8. device according to claim 7, it is characterised in that described detection module, for detecting whether below Fa Shenging
Situation: when accessing described PCI-E storage memory space, owing to described PCI-E storage memory space does not has
Corresponding storage entity and the exception that causes, and whether the operation address to be accessed of described exceptional instructions be positioned at
In the address realm in described PCI-E storage memory space；Wherein, testing result for being in the case of, really
Surely access in described PCI-E storage memory steric course and occur extremely.
9. device according to claim 8, it is characterised in that described device also includes, acquisition module, is used for obtaining
Described operation address, wherein, described acquisition module is additionally operable to judging that described current exception refers to as loading load class
During the exception that order causes, obtain described operation address from the instruction of described load class；Or from machine check interrupts state
Register MCSR reads described operation address.
10. device according to claim 9, it is characterised in that described acquisition module, is additionally operable to according to described load
The Format Type of class instruction, from the instruction of described load class described in appointment position acquisition corresponding with described Format Type
Operation address.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510076615.7A CN105988905A (en) | 2015-02-12 | 2015-02-12 | Exception processing method and apparatus |
| PCT/CN2015/086164 WO2016127600A1 (en) | 2015-02-12 | 2015-08-05 | Exception handling method and apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510076615.7A CN105988905A (en) | 2015-02-12 | 2015-02-12 | Exception processing method and apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105988905A true CN105988905A (en) | 2016-10-05 |
Family
ID=56614198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510076615.7A Withdrawn CN105988905A (en) | 2015-02-12 | 2015-02-12 | Exception processing method and apparatus |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105988905A (en) |
| WO (1) | WO2016127600A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110825593A (en) * | 2019-11-11 | 2020-02-21 | 腾讯科技（深圳）有限公司 | Method, device and equipment for detecting abnormal state of process and storage medium |
| CN111682991A (en) * | 2020-05-28 | 2020-09-18 | 杭州迪普科技股份有限公司 | Bus error message processing method and device |
| CN113467981A (en) * | 2020-03-31 | 2021-10-01 | 华为技术有限公司 | Exception handling method and device |
| CN116680208A (en) * | 2022-12-16 | 2023-09-01 | 荣耀终端有限公司 | Abnormality recognition method and electronic device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111124726B (en) * | 2019-12-09 | 2024-01-26 | 上海移远通信技术股份有限公司 | Method and device for detecting abnormality of open modem port |
| CN117573418B (en) * | 2024-01-15 | 2024-04-23 | 北京趋动智能科技有限公司 | Processing method, system, medium and equipment for video memory access exception |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101533370A (en) * | 2009-04-09 | 2009-09-16 | 成都市华为赛门铁克科技有限公司 | Memory abnormal access positioning method and device |
| CN103309762A (en) * | 2013-06-21 | 2013-09-18 | 杭州华三通信技术有限公司 | Equipment exception handling method and device |
| US20140208164A1 (en) * | 2013-01-24 | 2014-07-24 | Ltx-Credence Corporation | Scalable test platform |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4660056B2 (en) * | 2002-08-05 | 2011-03-30 | 株式会社セキュアウェア | Data processing device |
| JP2008146542A (en) * | 2006-12-13 | 2008-06-26 | Fujitsu Ltd | Multiprocessor system, processor device, and exceptional processing method |
| CN101625656B (en) * | 2009-07-28 | 2012-09-19 | 杭州华三通信技术有限公司 | Method and device for processing abnormity of PCI system |
-
2015
- 2015-02-12 CN CN201510076615.7A patent/CN105988905A/en not_active Withdrawn
- 2015-08-05 WO PCT/CN2015/086164 patent/WO2016127600A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101533370A (en) * | 2009-04-09 | 2009-09-16 | 成都市华为赛门铁克科技有限公司 | Memory abnormal access positioning method and device |
| US20140208164A1 (en) * | 2013-01-24 | 2014-07-24 | Ltx-Credence Corporation | Scalable test platform |
| CN103309762A (en) * | 2013-06-21 | 2013-09-18 | 杭州华三通信技术有限公司 | Equipment exception handling method and device |
Non-Patent Citations (1)
| Title |
|---|
| 李爱平: "基于ARM的嵌入式现场总线网关的设置与实现", 《中国优秀硕士学位论文全文数据库（硕士） 信息科技辑 2006年第12期》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110825593A (en) * | 2019-11-11 | 2020-02-21 | 腾讯科技（深圳）有限公司 | Method, device and equipment for detecting abnormal state of process and storage medium |
| CN113467981A (en) * | 2020-03-31 | 2021-10-01 | 华为技术有限公司 | Exception handling method and device |
| CN111682991A (en) * | 2020-05-28 | 2020-09-18 | 杭州迪普科技股份有限公司 | Bus error message processing method and device |
| CN116680208A (en) * | 2022-12-16 | 2023-09-01 | 荣耀终端有限公司 | Abnormality recognition method and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016127600A1 (en) | 2016-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105988905A (en) | Exception processing method and apparatus | |
| US6944796B2 (en) | Method and system to implement a system event log for system manageability | |
| CN102346707B (en) | Server system and operation method thereof | |
| CN101364212B (en) | Method and device for accessing to memory unit | |
| CN104572574B (en) | Ethernet controller IP kernel and method based on gigabit Ethernet vision agreement | |
| CN107111572B (en) | For avoiding the method and circuit of deadlock | |
| US8990451B2 (en) | Controller for direct access to a memory for the direct transfer of data between memories of several peripheral devices, method and computer program enabling the implementation of such a controller | |
| CN101430651A (en) | Access method for peripheral devices in heterogeneous multi-core system | |
| CN104714907B (en) | A kind of pci bus is converted to ISA and APB bus design methods | |
| CN103345439B (en) | A kind of full link monitoring method of health state of information system and device | |
| KR20170043269A (en) | Method for operating universal flash stroage (ufs) device, method for operating ufs host, and method for operating ufs systrem having them | |
| CN104112413B (en) | LED display bad point point detection system | |
| JP4366336B2 (en) | Method for managing trace data in logical partition data processing system, logical partition data processing system for managing trace data, computer program for causing computer to manage trace data, logical partition data Processing system | |
| CN108132910A (en) | System interconnection and the system on chip with system interconnection | |
| CN101232556A (en) | Semiconductor integrated circuit and data processing system | |
| CN101706747A (en) | Method, device and system for processing information of programmable logic | |
| CN106155826A (en) | For detecting and process the method and system of mistake in bus structures | |
| CN114579392A (en) | AXI bus monitor for write transactions | |
| CN107656870A (en) | Using adjustment method and device | |
| CN103853643B (en) | By the apparatus and method of the programmable circuit test memory in Safety-Critical System | |
| CN106161066A (en) | A kind of log collection method and server | |
| US20070233954A1 (en) | System and Method for Interfacing to a Media Card Related Application and Technical Field | |
| CN106330595A (en) | Heartbeat detection method and apparatus of distributed platform | |
| CN109062839A (en) | A kind of method, apparatus and computer readable storage medium detecting HBA card | |
| WO2010050957A1 (en) | Bit inversion for communication interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20161005 |
|
| WW01 | Invention patent application withdrawn after publication |