CN103218337B - Based on wishbone bus realize main and master and slave with from the SOC (system on a chip) communicated and method - Google Patents
Based on wishbone bus realize main and master and slave with from the SOC (system on a chip) communicated and method Download PDFInfo
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Abstract
A kind of based on wishbone bus realize primary module and primary module, from module with from the SOC (system on a chip) of module communication and method, this SOC (system on a chip) is provided with: standard wishbone bus, be connected to primary module that structure in this wishbone bus improves and from module, and the private exchange of setting up is from module and private exchange primary module.SOC (system on a chip) of the present invention by adding corresponding module, then is improved existing module, make a small amount of input of only cost, with low cost, simple to operate, easy, just can realize primary module and primary module, from module and from the communication between module.Wishbone bus resource can be made full use of like this, improve wishbone bus system communicative flexibility, achieve main and master and slave with from communication, make it be applicable to system more widely, take full advantage of the resources advantage of bus, also maintain the standardization of this SOC (system on a chip) simultaneously.
Description
Technical field
The present invention relates to a kind of SOC (system on a chip) based on wishbone bus, particularly a kind of wishbone of use as interconnection, realize main and master and slave with from the SOC (system on a chip) communicated and method, belong to the technical field of on-chip testing system and digital communication.
Background technology
Wishbone bus is a kind of SOC (system on a chip) bus interconnected for SOC (system on a chip) internal module.At present, SOC (system on a chip) uses four kinds of more bus standards to be: the OCP of Avalon and OCP-IP of Wishbone, Altera of AMBA, OpenCores of ARM.Wherein, the advantage that wishbone bus is different from other on-chip bus is as follows: structure is simple, and dirigibility is very strong, and interface is simply compact, is applicable to the system of lightweight specification; Support User Defined signal (as TGD_I/O), completely open and freely, i.e. inscience property right.Based on above advantage, wishbone bus is often used in the design of some lightweight SOC (system on a chip).
Network-on-chip test macro usually adopts SoPC (System on Programmable Chip) technology to realize, have the SOC (system on a chip) of multiple network performance being carried out to test function.Along with the development of semiconductor technology and industry, the product of such test macro or device little by little by original board level system gradually transition be SOC (system on a chip).Building of the SOC (system on a chip) of high-performance, lightweight, be unable to do without high performance on-chip bus, therefore wishbone on-chip bus is also widely used in a test system.
See Fig. 1, introduce one of feature of wishbone on-chip bus: the data transmission procedure of master-slave mode.The interface of its primary module can reading and writing bus, and can only be read and write by bus from the interface of module, and this is the reason that its structure is simple and compact.But, also therefore causes between primary module with primary module or from module and cannot communicate with between module, and this communication process is necessary in test macro often.
The reason of above-mentioned defect is caused to be that it mainly comprises following parts because this test macro based on wishbone bus has special design feature:
Control primary module: its function is be responsible on the one hand carrying out with upper-layer functionality module instruction or test result mutual, is responsible on the other hand assigning instruction to test primary module and reclaiming test result.
Test primary module: be responsible for receiving the test instruction controlling primary module, calling function implements different test processs from module; And calculate and after statistical test result, test result data sent to control primary module.
Function is from module: be responsible for calling of acceptance test primary module, and cooperatively interact, thus implement various concrete, complicated test function.
For network performance testing system: in test process, need control primary module to assign the test instruction with parameter to test primary module, reclaim test result and be also uploaded to host computer.Function also needs to carry out the exchange of packet and the process of procotol between module, mutually must cooperate, just can complete subnetwork performance test function.But, the master-slave mode data-transmission mode that wishbone bus self is fixing, make main control module and main test module, function all can not carry out data transmission from module and between functional module, this just greatly limit the realization of many network test functions.
The solution of prior art is: directly between primary module and/or between module, add data transmission interface, walk around bus transfer data, the control circuit of this SOC (system on a chip) is so not only made to become disorderly and unsystematic, destroy the standardization of this SOC (system on a chip), the bus advantage of this SOC (system on a chip) cannot be utilized again.And, often still can not meet the demand of user.Therefore, how to solve this difficult problem, just become the problem that scientific and technical personnel in the industry pay close attention to.
Summary of the invention
In view of this, the object of this invention is to provide and a kind ofly transformation is optimized to wishbone bus system thus the main and master and slave SOC (system on a chip) based on wishbone bus with communicating between module and method can be realized, invention increases the communicative flexibility of wishbone bus system, achieve main and master and slave with from communication, also maintain the standardization of this SOC (system on a chip) simultaneously and take full advantage of the resources advantage of bus.
In order to achieve the above object, the invention provides and a kind ofly realize primary module and primary module based on wishbone bus, from module and the SOC (system on a chip) from module communication, be provided with standard wishbone bus; It is characterized in that: this SOC (system on a chip) except to connect described wishbone bus each primary module original and except improving from module, also set up following two modules:
Private exchange is from module, be responsible for when primary module communicates with primary module, the communication data of control information that what temporary source primary module sent comprise, valid data and end signal, and confirm object primary module respectively according to the object primary module address in control information and communication data word length and this communication data is stored in object primary module storage space corresponding in the memory unit; And when the communication data that storage unit has multiple object primary module needs to send, by interruption
applicationthe arbitration of unit and priority supreme good primary module is produced interrupt application; After communication data is read by object primary module, just empty the storage space that this object primary module is corresponding, write for subsequent communications data; Be provided with: control, store, interrupt application and interface totally four unit;
Private exchange primary module, be responsible for when from module and from module communication, reception source is from the interruption application of module, and multiple interruption application is arbitrated, response priority the highest from module: first read and buffer memory source from the control information of the communication data module, to read whole communication data by the communication data word length in control information, and determine to forward target from module's address by object; After the reading completing communication data, write the communication data of buffer memory to object from module; Be provided with: control, buffer memory, interrupting receive and interface is totally four unit;
Described primary module and be increase separately the condition judgment module sent with receiving data respectively from the improvement of module, so that this primary module and can send communication data according to the protocol rule of setting separately respectively from module; And the protocol rule of the communication data received according to setting is resolved, to obtain valid data wherein.
In order to achieve the above object, the invention provides and a kind ofly adopt SOC (system on a chip) of the present invention to realize the method communicated between primary module with primary module, it is characterized in that: described method comprises following operation steps:
(1) after application to the bus right to use, source primary module first sends the communication data of query type to private exchange from module, then reads Query Result, judges whether private exchange object primary module corresponding stored space from module is empty; If be not empty, then perform subsequent step (2); Otherwise redirect performs step (3);
(2) this section of storage space is reset to sky by sending replacement type communication data by source primary module, or waits for that private exchange is after module general wherein data retransmission, becomes sky automatically; Just terminate the method operating process;
(3) source primary module sends communication data to private exchange from module; Private exchange, after module received communication data, is resolved the control information wherein first received by its control module, and after all communication datas being stored in storage space corresponding to object primary module according to control information, the source primary module release bus right to use;
(4) when private exchange will send from the communication data that the storage unit module monitors buffer memory, object primary module address is sent to interruption application unit, by interruption application unit, priority arbitration is carried out to object primary module, and send interruption application to priority supreme good primary module;
(5) the object primary module application bus right to use of this interruption application is received; Apply for successfully, first send the communication data pre-reading type to private exchange from module, and himself address is informed that private exchange is from module, so that next cycle reads the data in himself corresponding stored space; Or first send query type communication data, inquire about in its storage space the communication data whether having and need to read, transmission pre-reads type communication data and informs that private exchange is after module again, direct reading private exchange from the data in module corresponding stored space, and completes the reception of whole communication data according to the communication data word length in the control information first received;
(6) after object primary module receives all communication datas, it is resolved and extracted valid data; Meanwhile, private exchange cancels interruption application signal automatically from module, empties corresponding stored space; Terminate the communication process of this primary module and primary module.
In order to achieve the above object, invention further provides and a kind ofly adopt SOC (system on a chip) of the present invention to realize the method communicated with between module from module, it is characterized in that: described method comprises following operation steps:
(1), after source gets out communication data from module according to protocol rule, send to private exchange primary module and interrupt application;
(2) private exchange primary module interrupting receive unit receive the active interruption application from module, and carry out decision-making according to priority, first receive the communication data of the highest source of priority from module, its control module is according to the communication data word length in the control information first received, control interface unit completes the reception of whole communication data, and is written to buffer unit;
(3) private exchange primary module keeps the bus right to use, or when application is to the bus right to use again upon discharge, the communication data buffer unit sends to object from module according to object in control information from module's address and communication data word length by its control module;
(4) after object receives whole communication data from module, according to protocol rule, communication data is resolved, extract valid data wherein, just complete this from module and the communication process from module.
The present invention's advantage is compared with prior art: in the SOC (system on a chip) of similar test macro, because standard wishbone bus can only carry out primary module and the inconvenience to some extent from the communication between module.The solution of prior art between each equipment needing communication, adds self-defining interface carry out data transmission, but, do like this and system can be made to become numerous and diverse, destroy the standardization of system.SOC (system on a chip) of the present invention is by adding corresponding module, again existing module expanded, namely set up a small amount of logical circuit and respective resources, thus make that only cost is a small amount of to drop into, and simple to operate, easy, just can realize primary module and primary module, from module and from the communication between module.Wishbone bus resource can be made full use of like this, greatly improve system communication dirigibility, make it be more applicable for test macro, maintain the standardization of bus system simultaneously.
Accompanying drawing explanation
Fig. 1 is the structure composition schematic diagram of the existing standard SOC (system on a chip) based on wishbone bus.
Fig. 2 be the present invention is based on wishbone bus realize primary module and primary module, from module with form schematic diagram from the structure of the SOC (system on a chip) of module communication.
Fig. 3 is the private exchange primary module of SOC (system on a chip) of the present invention and the structure composition schematic diagram from module.
Fig. 4 the present invention is based on the operation steps process flow diagram that wishbone bus realizes once communicating between primary module with primary module.
Fig. 5 the present invention is based on wishbone bus to realize from module and the operation steps process flow diagram once communicated between module.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail.
See Fig. 2, introduce and the present invention is based on wishbone bus and realize primary module and primary module, from module and form from the structure of the SOC (system on a chip) of module communication.Each primary module that it comprises wishbone bus, the structure that is connected with this wishbone bus is improved and from module, and following two modules of setting up:
(1) private exchange is from module: be responsible for when primary module communicates with primary module, the communication data of control information that what temporary source primary module order sent comprise, valid data and end signal (control information wherein comprises source module address and object module's address, communication data byte length, communication type and reservation field for subsequent use), and confirm object primary module respectively according to the object primary module address in control information and communication data word length and this communication data is stored in object primary module storage space corresponding in the memory unit; And when the communication data that storage unit has multiple object primary module needs to send, by interruption
applicationthe arbitration of unit and priority supreme good primary module is produced interrupt application; After communication data is read by object primary module, just empty the storage space that this object primary module is corresponding, write for subsequent communications data; Be provided with: control, store, interrupt application and interface totally four unit.Structure composition and its function following (shown in Figure 3) of these four unit:
Control module: when sending communication data for source primary module, the control information first sent is resolved, to receive whole communication data according to object primary module address and communication data word length, and is stored to corresponding storage space; After object primary module has read all communication datas, be just end signal by the content assignment in storage unit corresponding to the first address of this storage space, to show that this storage space is for the free time, can be used in writing communication data next time.
Storage unit: the communication data sent for buffer memory source primary module, and be that each object primary module marks independent fixing storage space separately respectively; And whether be cached with the communication data do not sent in each storage space of Real-Time Monitoring; If have, then object primary module address corresponding for this communication data is sent to interruption application unit.The mode of this cell stores communication data has two kinds:
The first is that sectional type stores: for each primary module distributes one section of fixed storage space, will the communication data of different primary module be sent to stored in respective additional space according to the object primary module address in control signal;
The second is that queue-type stores: by all communication datas needing to forward according to reading and writing order buffer in first-in first-out FIFO storehouse, but the object primary module address need recorded in the control information of every group communication data, for generation of interruption application, until all data are sent out complete in FIFO storehouse.
Interrupt application unit: the object primary module address needing transport communication data being responsible for receiving storage unit transmission, and carry out arbitrating, producing and interrupt application signal according to the priority of these primary modules, the primary module generation interruption application signal that the same time is only the highest to priority.
Interface unit: be responsible for wishbone bus end to communication data chronologically rule read and write, the communication data of reception sent to control module simultaneously, be stored in storage space corresponding to object primary module; Or the communication data of reception control unit, reads for by primary module.
(2) private exchange primary module, be responsible for when from module and from module communication, reception source is from the interruption application of module, and multiple interruption application is arbitrated, response priority the highest from module: first read and buffer memory source from the control information of the communication data module, to read whole communication data by the communication data word length in control information, and determine to forward target from module's address by object; After the reading completing communication data, write the communication data of buffer memory to object from module.This private exchange primary module read-write communication data has two kinds of patterns:
The first is after occupying the bus right to use, first reads and Cache Communication data, and forces to keep the bus right to use, completes and is read from buffer unit by communication data, then be transmitted to object from module in this bus holding time;
The second is after occupying the bus right to use, first reads and Cache Communication data, does not force afterwards to keep the bus right to use; When this or next time obtaining the bus right to use, then communication data is read from buffer unit, and be transmitted to object from module.This module is provided with: control, buffer memory, interrupting receive and interface is totally four unit.Structure composition and its function following (shown in Figure 3) of these four unit:
Interrupting receive unit: be responsible for receiving the interruption application of each source from module, and execution priority arbitration, the source the highest to priority responds from the application of module, reads the communication data of this source from module to make control module;
Control module: when communication data is read from module's address in the source being responsible for sending by interrupting receive unit, the control information of first reading is resolved, to complete the reading of residue communication data according to communication data word length, and be stored in buffer unit; Again after the whole communication data of reading, according to the forwarding target that object is determined from module's address, send to object from module by interface unit the communication data in buffer unit;
Buffer unit: be responsible under the control of the control unit, the source that buffer memory is read by interface unit is from the communication data module;
Interface unit: be responsible for wishbone bus end to communication data chronologically rule send or receive, the communication data of reception is sent to control module, or the communication data of reception control unit simultaneously, then is transmitted to object from module.
(3) primary module improved in SOC (system on a chip) of the present invention and improvement be increase the condition judgment module sent with receiving data separately respectively from module so that this primary module and communication data can be sent according to the protocol rule of setting separately respectively from module; And the protocol rule of the communication data received according to setting is resolved, to obtain valid data wherein.
See Fig. 4, introduce SOC (system on a chip) of the present invention and realize communication means between primary module and primary module, concrete operation step:
Step 1, after application to the bus right to use, source primary module first sends the communication data of query type to private exchange from module, then reads Query Result, judges whether private exchange object primary module corresponding stored space from module is empty; If be not empty, then perform subsequent step 2; Otherwise redirect performs step 3.
Step 2, this section of storage space is reset to sky by sending replacement type communication data by source primary module, or waits for that private exchange is after module general wherein data retransmission, becomes sky automatically; Just terminate the method operating process.
Step 3, source primary module sends communication data to private exchange from module; Private exchange, after module received communication data, is resolved the control information wherein first received by its control module, and after all communication datas being stored in storage space corresponding to object primary module according to control information, the source primary module release bus right to use.
Step 4, when private exchange will send from the communication data that the storage unit module monitors buffer memory, object primary module address is sent to interruption application unit, by interruption application unit, priority arbitration is carried out to object primary module, and send interruption application to priority supreme good primary module.
Step 5, receives the object primary module application bus right to use of this interruption application; Apply for successfully, first send the communication data pre-reading type to private exchange from module, and himself address is informed that private exchange is from module, so that next cycle reads the data in himself corresponding stored space; Or first send query type communication data, inquire about in its storage space the communication data whether having and need to read, transmission pre-reads type communication data and informs that private exchange is after module again, direct reading private exchange from the data in module corresponding stored space, and completes the reception of whole communication data according to the communication data word length in the control information first received.
Step 6, after object primary module receives all communication datas, resolves and extracted valid data it; Meanwhile, private exchange cancels interruption application signal automatically from module, empties corresponding stored space; Terminate the communication process of this primary module and primary module.
See Fig. 5, introduce SOC (system on a chip) of the present invention and realize from module and the concrete operation step from communication means between module:
Step 1, after source gets out communication data from module according to protocol rule, sends to private exchange primary module and interrupts application.
Step 2, the interrupting receive unit of private exchange primary module receive the active interruption application from module, and carry out decision-making according to priority, first receive the communication data of the highest source of priority from module, its control module is according to the communication data word length in the control information first received, control interface unit completes the reception of whole communication data, and is written to buffer unit.
Step 3, private exchange primary module keeps the bus right to use, or when application is to the bus right to use again upon discharge, the communication data buffer unit sends to object from module according to object in control information from module's address and communication data word length by its control module.
Step 4, after object receives whole communication data from module, resolves communication data according to protocol rule, extracts valid data wherein, just completes this from module and the communication process from module.
Inventions have been and repeatedly implement test, below the situation of brief description embodiment:
When the present invention emulates enforcement, adopt the reason of SoPC (System on Programable Chip) hardware embodiments to be: the primary module of original system or from module be realize main and master and slave with need to add from communication function send, transmitting-receiving that receive state machine controls communication data, to meet the rule of communication protocol, SoPC can give full play to its programmable features, like a cork by former primary module with upgrade to from module amendment can carry out leading with master and slave with from the circuit structure communicated.And as main module of adding: the master/slave module of private exchange, also can utilize its programmable dirigibility, is added in this chip system effectively, neatly, reduce design complexities.The operation steps of embodiment is as described below:
Step 1: former SoPC SOC (system on a chip) is led and upgrades with the primary module of main communication: send at it, receiving element adds observation circuit and state machine respectively, when this communication of discovery carries out entering set condition when primary module communicates with primary module, send in this set condition, receiving circuit can send data according to communication protocol regular weaves of the present invention and parsing receives data, and only agreement process is carried out to the content of transceiving data, and without the need to changing the read-write interface of bus, also on former master with do not affect from the transceiving data of pattern.
Step 2: to former SoPC SOC (system on a chip) carry out from from upgrading from module of communicating: send at it, receiving element add observation circuit and state machine respectively, when this communication of discovery carries out from module and enters set condition from during module communication, send in this set condition, receiving circuit can send data according to communication protocol regular weaves of the present invention and parsing receives data, and only agreement process is carried out to the content of transceiving data, and without the need to changing the read-write interface of bus, also on former master with do not affect from pattern transceiving data.
Step 3: by the private exchange that built from module, be mounted to bus from module interface.This private exchange can adopt the mode of two kinds of storage data of the present invention from module, the function all can complete the storage of data, removing and monitor.
Step 4: the private exchange primary module built is mounted on the primary module interface of bus.Preferably adopt the continued operation of reading+writing, use same bus to take the mode of phase, to improve bus work efficiency, ensure the complete transmitting-receiving of data.
Step 5: complete primary module and the upgrading from module, and add private exchange primary module and private exchange after module to bus, also need to modify to interrupt system, setting priority etc., the structure completing each side from the interconnected angle of entire system just can realize primary module and primary module, from module and the communication process from module after improving.
Adopt above implementation step, just SOC (system on a chip) of the present invention is implemented in original system, and realizes correlation function by the inventive method.The test findings of embodiment is successful, achieves goal of the invention.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (8)
1. realize primary module and primary module based on wishbone bus, from module and the SOC (system on a chip) from module communication, be provided with standard wishbone bus; It is characterized in that: this SOC (system on a chip) except to connect described wishbone bus each primary module original and except improving from module, also set up following two modules:
Private exchange is from module, be responsible for when primary module communicates with primary module, the communication data of control information that what temporary source primary module sent comprise, valid data and end signal, and confirm object primary module respectively according to the object primary module address in control information and communication data word length and this communication data is stored in object primary module storage space corresponding in the memory unit; And when the communication data that storage unit has multiple object primary module needs to send, by the arbitration interrupting application unit, interruption application is produced to priority supreme good primary module; After communication data is read by object primary module, just empty the storage space that this object primary module is corresponding, write for subsequent communications data; Be provided with: control, store, interrupt application and interface totally four unit;
Private exchange primary module, be responsible for when from module and from module communication, reception source is from the interruption application of module, and multiple interruption application is arbitrated, response priority the highest from module: first read and buffer memory source from the control information of the communication data module, to read whole communication data by the communication data word length in control information, and determine to forward target from module's address by object; After the reading completing communication data, write the communication data of buffer memory to object from module; Be provided with: control, buffer memory, interrupting receive and interface is totally four unit;
Described primary module and be increase separately the condition judgment module sent with receiving data respectively from the improvement of module, so that this primary module and can send communication data according to the protocol rule of setting separately respectively from module; And the protocol rule of the communication data received according to setting is resolved, to obtain valid data wherein.
2. SOC (system on a chip) according to claim 1, it is characterized in that: described communication data is made up of the control information sequentially sent, valid data and end signal, wherein, control information comprises source module address and object module's address, communication data byte length, communication type and reservation field for subsequent use.
3. SOC (system on a chip) according to claim 1, is characterized in that: described private exchange is as follows from the Elementary Function of four module:
Control module, when sending communication data for source primary module, resolves the control information first sent, to receive whole communication data according to object primary module address and communication data word length, and is stored to corresponding storage space; After object primary module has read all communication datas, be just end signal by the content assignment in storage unit corresponding to the first address of this storage space, to show that this storage space is for the free time, can be used in writing communication data next time;
Storage unit for the communication data that buffer memory source primary module sends, and is that each object primary module marks independent fixing storage space separately respectively; And whether be cached with the communication data do not sent in each storage space of Real-Time Monitoring; If have, then object primary module address corresponding for this communication data is sent to interruption application unit;
Interrupt application unit, be responsible for the object primary module address needing transport communication data receiving storage unit transmission, and carry out arbitrating, producing and interrupt application signal according to the priority of these primary modules, the primary module generation interruption application signal that the same time is only the highest to priority;
Interface unit, be responsible for wishbone bus end to communication data chronologically rule read and write, the communication data of reception sent to control module simultaneously, be stored in storage space corresponding to object primary module; Or the communication data of reception control unit, reads for by primary module.
4. SOC (system on a chip) according to claim 1, is characterized in that: four Elementary Functions in described private exchange primary module are as follows:
Interrupting receive unit, is responsible for receiving the interruption application of each source from module, and execution priority arbitration, the source the highest to priority responds from the application of module, reads the communication data of this source from module to make control module;
Control module, when communication data is read from module's address in the source being responsible for sending by interrupting receive unit, resolves the control information of first reading, to complete the reading of residue communication data according to communication data word length, and is stored in buffer unit; Again after the whole communication data of reading, according to the forwarding target that object is determined from module's address, send to object from module by interface unit the communication data in buffer unit;
Buffer unit, be responsible under the control of the control unit, the source that buffer memory is read by interface unit is from the communication data module;
Interface unit, be responsible for wishbone bus end to communication data chronologically rule send or receive, the communication data of reception is sent to control module, or the communication data of reception control unit simultaneously, then is transmitted to object from module.
5. SOC (system on a chip) according to claim 1, is characterized in that: described private exchange has two kinds from the mode of the cell stores communication data module:
The first is that sectional type stores: for each primary module distributes one section of fixed storage space, will the communication data of different primary module be sent to stored in respective additional space according to the object primary module address in control signal;
The second is that queue-type stores: by all communication datas needing to forward according to reading and writing order buffer in first-in first-out FIFO storehouse, but the object primary module address need recorded in the control information of every group communication data, for generation of interruption application, until all data are sent out complete in FIFO storehouse.
6. SOC (system on a chip) according to claim 1, is characterized in that: described private exchange primary module read-write communication data has two kinds of patterns:
The first is after occupying the bus right to use, first reads and Cache Communication data, and forces to keep the bus right to use, completes and is read from buffer unit by communication data, then be transmitted to object from module in this bus holding time;
The second is after occupying the bus right to use, first reads and Cache Communication data, does not force afterwards to keep the bus right to use; When this or next time obtaining the bus right to use, then communication data is read from buffer unit, and be transmitted to object from module.
7. adopt SOC (system on a chip) according to claim 1 to realize the method communicated between primary module with primary module, it is characterized in that: described method comprises following operation steps:
(1) after application to the bus right to use, source primary module first sends the communication data of query type to private exchange from module, then reads Query Result, judges whether private exchange object primary module corresponding stored space from module is empty; If be not empty, then perform subsequent step (2); Otherwise redirect performs step (3);
(2) this section of storage space is reset to sky by sending replacement type communication data by source primary module, or waits for that private exchange is after module general wherein data retransmission, becomes sky automatically; Just terminate the method operating process;
(3) source primary module sends communication data to private exchange from module; Private exchange, after module received communication data, is resolved the control information wherein first received by its control module, and after all communication datas being stored in storage space corresponding to object primary module according to control information, the source primary module release bus right to use;
(4) when private exchange will send from the communication data that the storage unit module monitors buffer memory, object primary module address is sent to interruption application unit, by interruption application unit, priority arbitration is carried out to object primary module, and send interruption application to priority supreme good primary module;
(5) the object primary module application bus right to use of this interruption application is received; Apply for successfully, first send the communication data pre-reading type to private exchange from module, and himself address is informed that private exchange is from module, so that next cycle reads the data in himself corresponding stored space; Or first send query type communication data, inquire about in its storage space the communication data whether having and need to read, transmission pre-reads type communication data and informs that private exchange is after module again, direct reading private exchange from the data in module corresponding stored space, and completes the reception of whole communication data according to the communication data word length in the control information first received;
(6) after object primary module receives all communication datas, it is resolved and extracted valid data; Meanwhile, private exchange cancels interruption application signal automatically from module, empties corresponding stored space; Terminate the communication process of this primary module and primary module.
8. adopt SOC (system on a chip) according to claim 1 to realize the method communicated with between module from module, it is characterized in that: described method comprises following operation steps:
(1), after source gets out communication data from module according to protocol rule, send to private exchange primary module and interrupt application;
(2) private exchange primary module interrupting receive unit receive the active interruption application from module, and carry out decision-making according to priority, first receive the communication data of the highest source of priority from module, its control module is according to the communication data word length in the control information first received, control interface unit completes the reception of whole communication data, and is written to buffer unit;
(3) private exchange primary module keeps the bus right to use, or when application is to the bus right to use again upon discharge, the communication data buffer unit sends to object from module according to object in control information from module's address and communication data word length by its control module;
(4) after object receives whole communication data from module, according to protocol rule, communication data is resolved, extract valid data wherein, just complete this from module and the communication process from module.
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| CN104836710B (en) * | 2015-02-10 | 2018-06-05 | 数据通信科学技术研究所 | A kind of method and apparatus based on the communication of distributed system one master and multiple slaves |
| CN104980497B (en) * | 2015-05-18 | 2018-02-27 | 东南大学 | ESP encapsulation process devices based on Wishbone buses |
| CN105069227A (en) * | 2015-08-03 | 2015-11-18 | 浪潮集团有限公司 | Method for establishing functional verification platform on the basis of Wishbone bus design |
| CN109164976B (en) * | 2016-12-21 | 2021-12-31 | 北京忆恒创源科技股份有限公司 | Optimizing storage device performance using write caching |
| CN106845004A (en) * | 2017-02-15 | 2017-06-13 | 济南浪潮高新科技投资发展有限公司 | It is a kind of that system and method is built based on script for functional verification platform |
| CN107562549B (en) * | 2017-08-21 | 2019-12-03 | 西安电子科技大学 | Isomery many-core ASIP framework based on on-chip bus and shared drive |
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