CN103198856B - A kind of DDR controller and request scheduling method - Google Patents
A kind of DDR controller and request scheduling method Download PDFInfo
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- CN103198856B CN103198856B CN201310096014.3A CN201310096014A CN103198856B CN 103198856 B CN103198856 B CN 103198856B CN 201310096014 A CN201310096014 A CN 201310096014A CN 103198856 B CN103198856 B CN 103198856B
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Abstract
The present invention relates to a kind of DDR controller and request scheduling method, this controller comprises: AHB interface adaptation module (10), some client's request sending module (11), customer interface module (12), Port Scheduling module (13), BANK scheduler module (14), explanation module (15), PUB_PHY adaptation module (16), DDR2/3PHY module (17), DDR2/3 device (18), interface data cache module (19), data processing module (20), microcomputer mouth configuration module (21), Clock management module (22).DDR controller of the present invention and request scheduling method, be applied to storage and the forwarding of data in high-speed communication system transmission chip design, to compare traditional controller, adopt the request scheduling based on DRAM architectural characteristic, greatly reduce the delay of request, improve the utilization factor of data bus during transmission, under identical configuration, larger bus bandwidth can be obtained.
Description
Technical field
The present invention relates to digital integrated circuit DDR Controller gain variations field, is a kind of DDR controller and request scheduling method specifically.Described DDR refers to DDR2/3(DDR2 or DDR3).
Background technology
Along with developing rapidly of computer system, the restriction of modem computer systems more and more acceptor's memory performance.The performance of processor is increasing with the speed of annual 60%, and primary memory chip bandwidth is only increasing with the speed of annual 10%.In speed, primary memory and processor maintain the gap of about order of magnitude always.For the cost enabling main memory bandwidth matched-field processors performance spend is increasing, Computer System Design person must go the performance gap reduced between processor and primary memory as possible.
The request scheduling method of DDR2/3 controller is exactly the technology of the associative operation of main memory accesses being carried out to rational management, shortens the memory access time by this scheduling, thus reaches the object improving main memory bandwidth.
Summary of the invention
For the defect existed in prior art, the object of the present invention is to provide a kind of DDR controller and request scheduling method, be applied to storage and the forwarding of data in high-speed communication system transmission chip design, to compare traditional controller, adopt the request scheduling based on DRAM architectural characteristic, greatly reduce the delay of request, improve the utilization factor of data bus during transmission, under identical configuration, larger bus bandwidth can be obtained.
For reaching above object, the technical scheme that the present invention takes is:
A kind of DDR controller, is characterized in that, comprising: AHB interface adaptation module 10, some client's request sending module 11, customer interface module 12, Port Scheduling module 13, BANK scheduler module 14, explanation module 15, PUB_PHY adaptation module 16, DDR2/3PHY module 17, DDR2/3 device 18, interface data cache module 19, data processing module 20, microcomputer mouth configuration module 21, Clock management module 22;
AHB interface adaptation module 10 completes the privately owned interface request on ahb bus being transformed into DDR Controller gain variations, and the request after conversion is outputted to customer interface module 12;
Client's request sending module 11 completes the privately owned interface that client's request is fitted to DDR Controller gain variations, and the request after conversion is outputted to customer interface module 12;
Customer interface module 12 completes application client request absorption and exchanges data, customer address is to the mapping of DDR address, read-write requests address assignment and recovery, and there is allocation address error detection protective capability, reading and writing request ordinal response function, the mutual handoff functionality of client clock territory and DDR3C core key-course clock zone;
Port Scheduling module 13, it completes dispatches according to the execution sequence of priority to request of the request of different port configuration, will ask according to port priority Sequential output to BANK scheduler module 14;
BANK scheduler module 14 completes the adjustment carrying out request order according to the BANK address of asking and read-write type, export to downstream explanation module 15, object the request of identical BANK address is scatter as much as possible, the request of identical read-write type is got up continuously, thus makes the interpreted command efficiency of downstream explanation module higher;
Explanation module 15, mainly complete the refreshing of maintenance DRAM, command scheduling is carried out to the read-write requests of business, according to DDR2/3 agreement, the client's reading and writing request after arbitration is interpreted as DRAM order, completes the segmentation of requested service, complete DDR self-refresh mode and battery saving mode function;
PUB_PHY adaptation module 16 mainly completes the DRAM order of controller output and the adaptation of reading and writing data and different manufacturers DDR-PHY; Its initialization realizing DRAM and the function of DRAM being tested by microcomputer mouth;
DDR2/3PHY module 17 completes the connection between DDR controller and DDR2/3 device 18, carries out the conversion of electric signal, writing level calibration, read data collection and reads the work such as data-bias correction;
What interface data cache module 19 cache interface was sent reads and writes data;
Data processing module 20 comprises read data processing module 201 and writes data processing module 202 two parts, at the digital independent/ablation process of read/write interface buffering, based on the row action after each segmentation, produce the read/write information of egress buffer, calculation command is to the whole path delay of data;
Microcomputer mouth configuration module 21 carrys out the various parameter configuration of Configuration Control Unit needs use, to meet different application demand by microcomputer mouth;
The clock source that Clock management module 22 provides design to want.
On the basis of technique scheme, described client's request sending module 11 is according to customer requirement support read-write unification port, separately write port or independent read port.
On the basis of technique scheme, customer interface module 12 has self-checking function, can send a series of read-write requests with verification character when not having client to ask.
On the basis of technique scheme, Port Scheduling module 13 is as arbitration scheduler module, and it adopts the method for polling dispatching under equal priority running into, and ensures that the delay of high priority port request is shorter, obtains larger bus bandwidth.
On the basis of technique scheme, each module of described DDR controller realizes with hardware FPGA form completely.
A request scheduling method for DDR controller, is characterized in that, comprises the following steps:
Step 1: user sends the read-write requests of data to customer interface module 12 by client's request sending module 11, the read-write requests of described data at least comprise request type, address, length, No. ID, customer interface module 12 temporarily will be asked stored in the buffer memory in module, after waiting for that downstream port scheduler module 13 provides response ack signal, order sends request to Port Scheduling module 13;
Wherein:
Data path writes direction, writing data stored in writing in buffer memory according to the page address in solicited message stored in customer interface module 12, will write data again and sending when waiting for that follow-up explanation module 15 explains this request;
Data path reads direction, and after receiving the read pulse of explanation module 15, according to reading enable signal by the data temporary storage of reading back to reading in buffer memory, the order come according to client's read request ejects read data successively;
Step 2: the request that customer interface module 12 sends is dispatched according to the port numbers of request and BANK address in Port Scheduling module 13 and BANK scheduler module 14;
Step 3: the request order after scheduling enters in the request waiting list in explanation module 15, according to the timing requirements specified in the agreement of DDR, request is construed to the instruction of DDR identification;
Step 4: the DDR instruction that explanation module 15 sends, adjusts the phase relation between instruction and data through PUB_PHY adaptation module 16, then enters in PHY module 17 and carries out level conversion and output to DDR device 18.
On the basis of technique scheme, after having asked, inner in customer interface module 12, the address of client needs the order order release according to request input at every turn.
On the basis of technique scheme, the concrete scheduling process of Port Scheduling module 13 and BANK scheduler module 14 is as follows:
First, ask to carry out preliminary scheduling according to the priority of request port in Port Scheduling module 13, high priority is preferential, uses Roundrobin polling algorithm to arbitrate under same priority;
Then, be divided in different queues according to the BANK address of asking and read-write type by request, BANK scheduler module 14 can carry out interleaving scheduling between the request of different queues, at utmost ensures discontinuous request of calling same BANK; Meanwhile, BANK scheduler module 14 also can ensure that read-write requests " binding " exports, and namely ensures that in a period of time, DDR data bus transmission direction is consistent, reduces unnecessary read-write switching time; In addition, BANK scheduler module 14 also has overtime protection mechanism, ensures that the problem that there will not be the request of certain type always to can not get responding occurs.
On the basis of technique scheme, described customer interface module 12 comprises following functions submodule: read data buffer memory 119, read request are turned round sequence 120, read response queue 121, are read BUFF page pointer 122, customer address to the buffer memory page address maps 125, solicited message buffer queue 124, write BUFF page pointer 126, write request turns round sequence 127, write response queue 128, write data buffer storage 129;
The workflow of customer interface module 12 is as follows:
For the process of write request, client is after receiving write response cli_waq_ack, write request, customer information and data are sent to customer interface module 12, address information in customer information is converted to the discernible page address page_addr of customer interface through customer address to address maps 125 submodule of the buffer memory page, and stored in solicited message buffer queue 124 together with other solicited messages; Writing data cli_wd writes in data buffer storage 129 according to the buffer memory page address page_addr after mapping stored in writing data buffer storage; The BUFF page pointer 126 of writing simultaneously recording the write request number of buffer memory in customer interface adds 1; Then, when the request waiting list waiting in the Port Scheduling module 13 in downstream is discontented with, just request and information is ejected by queue order order; After the explanation module 15 in downstream completes the explanation of certain write request, the request of getting this request msg can be sent to customer interface module 12 by writing data processing module 202; Because downstream module can carry out certain scheduling to request execution order, therefore writing the write response that data processing module 202 returns is out of order release; In order to the problem preventing client from occurring address conflict, customer interface module 12 can by the write response of out of order release stored in write response queue 128, and the order finally entered according to actual write request is turned round sequence 127 Sequential output by write request successively and write into instruction and id information;
For the process of read request, solicited message stored in and address maps principle with the process of write request; After explanation module 15 completes the explanation of read request, after waiting for certain delay by read data according to reading the relevant position of BUFF page pointer 122 stored in read data buffer memory 119, enter etc. the response returned in response queue 121 of continuing, turning round sequence 120 in read request turns round after sequence becomes to ask the order that enters, and then order sends read data and id information to client.
DDR controller of the present invention and request scheduling method, dispatching method has high-level efficiency, Controller gain variations and the implement device of DDR2/3 device can be supported flexibly, in effective solution current digital transmission chip, data pass through the lower bottleneck problem of DDR device storing and forwarding efficiency, and the problem of implementation of hardware implementing memory access dispatching algorithm.
Accompanying drawing explanation
The present invention has following accompanying drawing:
The structural representation of Fig. 1: high speed DDR2/3 controller.
Fig. 2: customer interface module workflow diagram.
Fig. 3: the structural representation of request arbitration.
Fig. 4: the workflow diagram of request arbitration.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
As shown in Figure 1, DDR controller of the present invention (DDR3C controller) is containing user interface and DDR device physics layer (PHY) in a kind of structure, the control device of the DDR2/3 of functionally compatible general data request and the request of AHB class, and it comprises:
AHB interface adaptation module (AHB_APT) 10, some client's request sending module (CLI_HOST) 11, customer interface module (CLI_INF) 12, Port Scheduling module (PORT_SCH) 13, BANK scheduler module (BANK_SCH) 14, explanation module (DDR3CTR) 15, PUB_PHY adaptation module 16, DDR2/3PHY module 17, DDR2/3 device 18, interface data cache module 19, data processing module (W/RDCC) 20, microcomputer mouth configuration module (UPI_DDR3C) 21, Clock management module (CLK_MANAGE) 22;
AHB interface adaptation module 10 completes the privately owned interface request on ahb bus being transformed into DDR Controller gain variations, and the request after conversion is outputted to customer interface module 12;
Client's request sending module 11 completes the privately owned interface that client's request is fitted to DDR Controller gain variations, and the request after conversion is outputted to customer interface module 12; Described client's request sending module 11 is according to customer requirement support read-write unification port, separately write port or independent read port; In embodiment illustrated in fig. 1, be provided with the positive integer of N number of client's request sending module 11, N value for being more than or equal to 1;
Customer interface module 12 completes application client request absorption and exchanges data, customer address is to the mapping of DDR address, read-write requests address assignment and recovery, and there is allocation address error detection protective capability, reading and writing request ordinal response function, the mutual handoff functionality of client clock territory and DDR3C core key-course clock zone; In addition, this module also has self-checking function, can send a series of read-write requests with verification character, being convenient to user and debugging design when not having client to ask;
Port Scheduling module 13, also can be described as arbitration scheduler module, and it completes dispatches according to the execution sequence of priority to request of the request of different port configuration, will ask according to port priority Sequential output to BANK scheduler module 14; Adopt the method for polling dispatching under equal priority, ensure that the delay of high priority port request is shorter, obtain larger bus bandwidth;
BANK scheduler module 14 completes the adjustment carrying out request order according to the BANK address of asking and read-write type, export to downstream explanation module 15, object the request of identical BANK address is scatter as much as possible, the request of identical read-write type is got up continuously, thus makes the interpreted command efficiency of downstream explanation module higher;
Explanation module 15, also read-write requests explanation module is called, mainly complete the refreshing of maintenance DRAM, command scheduling is carried out to the read-write requests of business, according to DDR2/3 agreement, the client's reading and writing request after arbitration is interpreted as DRAM order, complete the segmentation of requested service, complete the function such as DDR self-refresh mode and battery saving mode (low power dissipation design);
PUB_PHY adaptation module 16 mainly completes the DRAM order of controller output and the adaptation of reading and writing data and different manufacturers DDR-PHY; In addition, the initialization of DRAM and the function of being tested DRAM by microcomputer mouth are also realized at this; For different producers or DDR2/3 type, this module needs adjustment;
DDR2/3PHY module 17 completes the connection between DDR controller and DDR2/3 device 18, carries out the conversion of electric signal, writing level calibration, read data collection and reads the work such as data-bias correction;
What interface data cache module 19 cache interface was sent reads and writes data;
Data processing module 20 comprises read data processing module 201(RDCC) and write data processing module 202(WDCC) two parts, at the digital independent/ablation process of read/write interface buffering, based on the row action after each segmentation, produce the read/write information of egress buffer, calculation command is to the whole path delay of data;
Microcomputer mouth configuration module 21 carrys out the various parameter configuration of Configuration Control Unit needs use by microcomputer mouth, and object makes the present invention can meet different application demand;
The clock source that Clock management module 22 provides design to want.
The design of DDR2/3 controller of the present invention realizes with hardware FPGA form completely.By the easy configuration that microcomputer mouth (UPI) carries out about DDR parameter and controller characteristic to controller, just can realize by hardware interface to DDR2/3 device storage forwarding data.For needing the system of carrying out mass data storage forwarding in high-speed communication, using the present invention's design, under the hardware costs that can bear (the less complexity of hardware area is not high), higher data bus utilization (data transfer bandwidth) can be obtained.In addition, the present invention supports that the CPU of ahb bus class asks, and ensures that the request of AHB class is responded faster by arbitration algorithm.
It has following characteristic and advantage:
1, compatible DDR2/3 agreement while;
2, industrywide standard DDRPHYInterface2.1 is supported;
3, the project organization of low area, low client request delay;
4, support AMBAAXI/AHB and service class request, port can flexible configuration simultaneously;
5, request scheduling method (based on client's request and DRAM characteristic) ensures high bandwidth utilization and low delay efficiently;
6, support low power dissipation design, reduce system power dissipation;
7, adopt controller and the DRAM clock frequency ratio of 1:2, reduce design part sequential;
8, there is self-checking function, can the working condition of test controller and DDR device when not connecing external interface.
For above-mentioned DDR controller, the present invention gives the request scheduling method of this DDR controller, comprises the following steps:
Step 1: user comprises two class requests by this module of client request sending module 11(: common customer port request and the request of AHB interface class) read-write requests (comprising request type, address, length, ID etc.) of data is sent to customer interface module 12, customer interface module 12 temporarily will be asked stored in the buffer memory in module, after waiting for that downstream port scheduler module 13 provides response ack signal, order sends request to Port Scheduling module 13;
Data path writes direction, writing data stored in writing in buffer memory according to the page address in solicited message stored in customer interface module 12, will write data again and sending when waiting for that follow-up explanation module 15 explains this request;
Data path reads direction, and after receiving the read pulse of explanation module 15, according to reading enable signal by the data temporary storage of reading back to reading in buffer memory, the order come according to client's read request ejects read data successively;
Because the request entering customer interface module 12 needs the out of order scheduling through downstream port scheduler module 13 and BANK scheduler module 14, therefore in explanation module 15, likely occur that the request of arriving also does not perform above, the conflict situations of identical address is is just read and write in request below.In order to avoid the situation that this request address conflicts, after having asked, inner in customer interface module 12, the address of client needs the order order release according to request input at every turn;
Step 2: the request that customer interface module 12 sends can be dispatched to a certain extent according to the port numbers of request and BANK address in Port Scheduling module 13 and BANK scheduler module 14.The effect of scheduling: one is the high priority ensureing low delay port request, and two is the explanation efficiency improving downstream explanation module, thus obtains the high-throughput on DDR data bus.
The concrete scheduling process of Port Scheduling module 13 and BANK scheduler module 14 is as follows:
First, ask to carry out preliminary scheduling according to the priority of request port in Port Scheduling module 13, high priority is preferential, uses Roundrobin polling algorithm to arbitrate under same priority;
Then, according to the BANK address of request and read-write type, request is divided in different queues that (DDR is totally 8 BANK, each BANK is divided into reading and writing two queues, totally 16 queues), BANK scheduler module 14 can carry out interleaving scheduling between the request of different queues, at utmost ensures discontinuous request of calling same BANK; Meanwhile, BANK scheduler module 14 also can ensure that read-write requests " binding " exports, and namely ensures that in a period of time, DDR data bus transmission direction is consistent, reduces unnecessary read-write switching time; In addition, BANK scheduler module 14 also has overtime protection mechanism, ensures that the problem that there will not be the request of certain type always to can not get responding occurs;
Step 3: the request order after scheduling enters in the request waiting list in explanation module 15, according to the timing requirements specified in the agreement of DDR, request is construed to the instruction of DDR identification; In specific explanations process, on the one hand, explanation module 15 is understood serial interpretation and is performed the read-write motion of waiting list head of the queue request, on the other hand, if module detects in queue the demand (such as charging or activation) having other requests to need to prepare in advance, then can in the interval performing row action, plug hole performs the charging or activation action of asking in queue; In addition, the self refresh operation under the explanation module refresh operation that also needed DDR to specify and battery saving mode;
Step 4: the DDR instruction that explanation module 15 sends, adjusts the phase relation between instruction and data through PUB_PHY adaptation module 16, then enters in PHY module 17 and carries out level conversion and output to DDR device 18; PUB_PHY adaptation module 16 interface can be fitted on different phy interfaces flexibly by simple process, facilitates general; In order to reduce the timing requirements of whole design, the present invention designs and adopts control core layer to use low-frequency clock, in the method for PUB_PHY module frequency multiplication to DDR high frequency clock, the data of the i.e. order of explanation module parallel output two paths under low-frequency clock, address and double bit wide, are merged into a path after using frequency doubling clock to sample and export to DDR in PUB_PHY modules; Sequential relationship concrete between interface meets industrywide standard DDRPHYInterface2.1.
Be illustrated in figure 2 the workflow diagram of the customer interface module 12 of DDR2/3 Controller gain variations of the present invention, wherein the concrete enforcement of customer interface module 12 comprises following functions submodule: read data buffer memory 119, read request are turned round sequence 120, read response queue 121, are read BUFF page pointer 122, customer address to the buffer memory page address maps 125, solicited message buffer queue 124, write BUFF page pointer 126, write request turns round sequence 127, write response queue 128, write data buffer storage 129.
The customer interface module 12 of the DDR2/3 Controller gain variations of the embodiment of the present invention go for reading and writing unification customer interface, independently read interface, independently write interface, AHB class customer interface (front end need increase the adapter circuit module of ahb bus).Under different application scenarioss, the type of option interface can be carried out by configuration.The workflow of customer interface module 12 is as follows:
1) for the process of write request, client is after receiving write response cli_waq_ack, write request, customer information (comprising address, length, ID, mask etc.) and data are sent to customer interface module 12, address information in customer information is converted to the discernible page address page_addr of customer interface through customer address to address maps 125 submodule of the buffer memory page, and forms stored in solicited message buffer queue 124(asynchronous FIFO together with other solicited messages) in; Writing data cli_wd writes in data buffer storage 129 according to the buffer memory page address page_addr after mapping stored in writing data buffer storage; The BUFF page pointer 126 of writing simultaneously recording the write request number of buffer memory in customer interface adds 1; Then, when the request waiting list waiting in the Port Scheduling module 13 in downstream is discontented with (back-pressure ack signal is effective), just request and information is ejected by queue order order; After the explanation module 15 in downstream completes the explanation of certain write request, can by writing data processing module 202(WDCC, the submodule of data processing module 20 in Fig. 1) request of getting this request msg is sent to customer interface module 12; Because downstream module (Port Scheduling module 13, BANK scheduler module 14) can carry out certain scheduling to request execution order, therefore writing the write response that data processing module 202 returns is out of order release; Occur that in order to prevent client the problem of address conflict is (such as because after request scheduling, certain DDR address is just read before also not write), customer interface module 12 can by the write response of out of order release stored in write response queue (asynchronous FIFO) 128, and the order finally entered according to actual write request is turned round sequence 127 Sequential output by write request successively and write into instruction and id information;
2) for the process of read request, solicited message stored in and address maps principle with the process of write request; After explanation module 15 completes the explanation of read request, after waiting for certain delay by read data according to reading the relevant position of BUFF page pointer 122 stored in read data buffer memory 119, enter etc. the response returned in response queue 121 of continuing, turning round sequence 120 in read request turns round after sequence becomes to ask the order that enters, and then order sends read data and id information to client.
What be illustrated in figure 3 DDR2/3 Controller gain variations of the present invention asks the Port Scheduling module 13 of arbitration function and the structured flowchart of BANK scheduler module 14 for realizing, and namely asks the concrete enforcement of arbitration function to comprise following functions module: Port Scheduling module 13, BANK scheduler module 14.The request of each port walks abreast entry port scheduler module 13, according to priority, continuously between request identical BANK address the dispatching principle such as request separation, request binding execution that read-write type is consistent under Serial output.
Be illustrated in figure 4 the specific works flow process figure of request scheduling (request arbitration) function of DDR2/3 Controller gain variations of the present invention.Due to the three-dimensional storage organization (DDR address is divided into Bank block address) of the uniqueness of DDR device, Row (row address) and Column (column address) three part), the performance height of its access data depends on the pattern (execution order of namely ordering between each business) of performed order.Finding by analyzing, out of order scheduling being carried out to the principle that request performs according to the request binding that identical BANK address discretize, read-write type are consistent, the performance (bandwidth, time delay etc.) of storer can be improved significantly.
The DDR2/3 Controller gain variations of the embodiment of the present invention carries out request scheduling according to dispatching principle above, its workflow is as follows: whole scheduling is divided into two stages, Port Scheduling (namely port arbitration is once arbitrated) and BANK scheduling (BANK arbitrates, i.e. secondary arbitration).First, the request of each customer interface module 12 walks abreast entry port scheduler module 13, request is carried out dividing into groups by the Request Priority that Port Scheduling module 13 can configure according to each interface, and (step 100 designs supporting interface can configure 1-8 kinds of priority, 1 priority is the highest), then respectively organize priority request and enter the corresponding wheel of this group scheduling Roundrobin(Round-RobinScheduling) poller module (referred to as RR module) interior (step 101), after waiting for that downstream procedures 102 ejects a request, start the poll of respective priority RR module, select the request that the next one of this priority is to be output.RR model choice under often kind of priority etc. request to be output, can according to fixing priority orders (1 → 8) (step 102), Serial output enters BANK scheduler module 14.BANK scheduler module 14 can according to the BANK address of request, input request is divided into 8 BANK administrative unit BMU(steps 103), in (the read-write unification of the inner port type according to port arrangement of each BANK administrative unit, write separately, read separately) will ask stored in three queues (step 104), then in each BANK administrative unit queue, the request of head of the queue enters respectively according to read-write type and reads or writes in RR module (step 105), request is selected to export (step 106) according to the selection signal that request type selection mode machine provides from reading or writing in RR module, request (step 109) after final Serial output scheduling.The selection of read-write type request is determined (step 107) by a request type selection mode machine, and this state machine can adjust according to the request BANK address of the maximum execution time of the read-write requests of microcomputer mouth configuration and the current output fed back the type exporting and ask.In addition, in order to ensure the dispersiveness of the request BANK address from BANK scheduler module 14 Serial output, the BANK address of the request of current output can be recorded, and feeding back to the porch of read and write RR module, the request that (Configuration Values) shields such BANK address within a period of time enters in read and write RR module (step 108) again.Through the request stream that above-mentioned two benches is dispatched, there is the BANK address discretize of request, read-write type binding, and taken into account the feature of the priority of client port, greatly heighten the efficiency that downstream explanation module carries out command interpretation, improve the forwarding performance of whole controller.
The embodiment of the invention described above is implemented according to premised on the control method of technical solution of the present invention, gives detailed embodiment and concrete operating process, but protection scope of the present invention comprises and is not limited to this embodiment.
The content be not described in detail in this instructions belongs to the known prior art of professional and technical personnel in the field.
Claims (9)
1. a DDR controller, it is characterized in that, comprise: AHB interface adaptation module (10), some client's request sending module (11), customer interface module (12), Port Scheduling module (13), BANK scheduler module (14), explanation module (15), PUB_PHY adaptation module (16), DDR2/3PHY module (17), DDR2/3 device (18), interface data cache module (19), data processing module (20), microcomputer mouth configuration module (21), Clock management module (22);
AHB interface adaptation module (10) completes the privately owned interface request on ahb bus being transformed into DDR Controller gain variations, and the request after conversion is outputted to customer interface module (12);
Client's request sending module (11) completes the privately owned interface that client's request is fitted to DDR Controller gain variations, and the request after conversion is outputted to customer interface module (12);
Customer interface module (12) completes application client request absorption and exchanges data, customer address is to the mapping of DDR address, read-write requests address assignment and recovery, and there is allocation address error detection protective capability, reading and writing request ordinal response function, the mutual handoff functionality of client clock territory and DDR core key-course clock zone;
Port Scheduling module (13), it completes dispatches according to the execution sequence of priority to request of the request of customer interface module (12) different port configuration, will ask according to port priority Sequential output to BANK scheduler module (14);
BANK scheduler module (14) completes the adjustment carrying out request order according to the BANK address of asking and read-write type, export to downstream explanation module (15), object the request of identical BANK address is scatter as much as possible, the request of identical read-write type is got up continuously, thus makes the interpreted command efficiency of downstream explanation module higher;
Explanation module (15), mainly complete the refreshing of maintenance DRAM, command scheduling is carried out to the read-write requests of business, according to DDR2/3 agreement, the client's reading and writing request after arbitration is interpreted as DRAM order, complete the segmentation of requested service, complete DDR self-refresh mode and battery saving mode function, the DDR order that explanation module (15) sends adjusts the phase relation between instruction and data through PUB_PHY adaptation module (16), then enters in DDR2/3PHY module (17) to carry out level conversion and output to DDR device (18);
PUB_PHY adaptation module (16) mainly completes the DRAM order of controller output and the adaptation of reading and writing data and different manufacturers DDR-PHY; Its initialization realizing DRAM and the function of DRAM being tested by microcomputer mouth;
DDR2/3PHY module (17) completes the connection between DDR controller and DDR2/3 device (18), carries out the conversion of electric signal, writing level calibration, read data collection and reads data-bias correction work;
What interface data cache module (19) cache interface was sent reads and writes data;
Data processing module (20) comprises read data processing module (201) and writes data processing module (202) two parts, at the digital independent/ablation process of read/write interface buffering, based on the row action after each segmentation, produce the read/write information of egress buffer, calculation command is to the whole path delay of data; After the explanation module (15) in downstream completes the explanation of certain write request, the request of getting these write request data can be sent by writing data processing module (202) to customer interface module (12); For the process of read request, solicited message stored in and address maps principle with the process of write request;
Microcomputer mouth configuration module (21) carrys out the various parameter configuration of Configuration Control Unit needs use, to meet different application demand by microcomputer mouth;
The clock source that Clock management module (22) provides design to want.
2. DDR controller as claimed in claim 1, is characterized in that: described client's request sending module (11) is according to customer requirement support read-write unification port, separately write port or independent read port.
3. DDR controller as claimed in claim 1, is characterized in that: customer interface module (12) has self-checking function, can send a series of read-write requests with verification character when not having client to ask.
4. DDR controller as claimed in claim 1, it is characterized in that: Port Scheduling module (13) is as arbitration scheduler module, it adopts the method for polling dispatching under equal priority running into, ensure that the delay of high priority port request is shorter, obtain larger bus bandwidth.
5. DDR controller as claimed in claim 1, is characterized in that: each module of described DDR controller realizes with hardware FPGA form completely.
6. the request scheduling method of a kind of DDR controller as described in claim 1-5 any one, is characterized in that, comprise the following steps:
Step 1: user sends the read-write requests of data by client's request sending module (11) to customer interface module (12), the read-write requests of described data at least comprise request type, address, length, No. ID, customer interface module (12) temporarily will be asked stored in the buffer memory in module, after waiting for that downstream port scheduler module (13) provides response ack signal, order sends request to Port Scheduling module (13);
Wherein:
Data path writes direction, writing data stored in writing in buffer memory according to the page address in solicited message stored in customer interface module (12), will write data again and sending when waiting for that follow-up explanation module (15) explains this request;
Data path reads direction, and after receiving the read pulse of explanation module (15), according to reading enable signal by the data temporary storage of reading back to reading in buffer memory, the order arrived according to client's read request ejects read data successively;
Step 2: the request that customer interface module (12) sends is dispatched according to the port numbers of request and BANK address in Port Scheduling module (13) and BANK scheduler module (14);
Step 3: the request order after scheduling enters in the request waiting list in explanation module (15), according to the timing requirements specified in the agreement of DDR, request is construed to the instruction of DDR identification;
Step 4: the DDR instruction that explanation module (15) sends, adjust the phase relation between instruction and data through PUB_PHY adaptation module (16), then enter in DDR2/3PHY module (17) and carry out level conversion and output to DDR2/3 device (18).
7. method as claimed in claim 6, is characterized in that: after having asked at every turn, inner in customer interface module (12), and the address of client needs the order order release according to request input.
8. method as claimed in claim 6, it is characterized in that, the concrete scheduling process of Port Scheduling module (13) and BANK scheduler module (14) is as follows:
First, ask to carry out preliminary scheduling according to the priority of request port in Port Scheduling module (13), high priority is preferential, uses wheel to make scheduling Roundrobin polling algorithm arbitrate under same priority;
Then, be divided in different queues according to the BANK address of asking and read-write type by request, BANK scheduler module (14) can carry out interleaving scheduling between the request of different queues, at utmost ensures discontinuous request of calling same BANK; Meanwhile, BANK scheduler module (14) also can ensure that read-write requests " binding " exports, and namely ensures that in a period of time, DDR data bus transmission direction is consistent, reduces unnecessary read-write switching time; In addition, BANK scheduler module (14) also has overtime protection mechanism, ensures that the problem that there will not be the request of certain type always to can not get responding occurs.
9. method as claimed in claim 6, it is characterized in that, described customer interface module (12) comprises following functions submodule: read data buffer memory (119), read request are turned round sequence (120), read response queue (121), are read BUFF page pointer (122), customer address to the buffer memory page address maps (125), solicited message buffer queue (124), write BUFF page pointer (126), write request turns round sequence (127), write response queue (128), write data buffer storage (129);
The workflow of customer interface module (12) is as follows:
For the process of write request, client is after receiving write response cli_waq_ack, write request, customer information and data are sent to customer interface module (12), address information in customer information is converted to customer interface discernible buffer memory page address page_addr through customer address to address maps (125) submodule of the buffer memory page, and stored in solicited message buffer queue (124) together with other solicited messages; Write data cli_wd according to the buffer memory page address page_addr after mapping stored in writing in data buffer storage (129); The BUFF page pointer (126) of writing simultaneously recording the write request number of buffer memory in customer interface adds 1; Then, when the request waiting list waiting in the Port Scheduling module (13) in downstream is discontented with, just request and information is ejected by queue order order; After the explanation module (15) in downstream completes the explanation of certain write request, the request of getting request msg can be sent by writing data processing module (202) to customer interface module (12); Because downstream module Port Scheduling module (13), BANK scheduler module (14) can carry out certain scheduling to request execution order, therefore writing the write response that data processing module (202) returns is out of order release; In order to the problem preventing client from occurring address conflict, customer interface module (12) can by the write response of out of order release stored in write response queue (128), and the order finally entered according to actual write request is turned round sequence (127) Sequential output by write request successively and write into instruction and id information;
For the process of read request, solicited message stored in and address maps principle with the process of write request; After explanation module (15) completes the explanation of read request, after waiting for certain delay by read data according to reading the relevant position of BUFF page pointer (122) stored in read data buffer memory (119), enter etc. the response returned in response queue of continuing (121), turning round sequence (120) in read request turns round after sequence becomes to ask the order that enters, and then order sends read data and id information to client.
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