CN103178996B - Distributed packet-switching chip model verification system and method - Google Patents
Distributed packet-switching chip model verification system and method Download PDFInfo
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Abstract
The invention discloses distributed packet-switching chip model verification system and method and relates to the field of designing packet processing chips. The system comprises a core control module, a command line interface module, an SDK (software development kit) proxy interface module, a virtual network test meter module, a virtual chip configuration module and a C model package module. The core control module is a server program module. The command line interface module, the SDK proxy interface module, the virtual network test meter instrument, the virtual chip configuration module and the C model package module are client program modules. The system is a C/S/C (client/server/client) structured distributed system supporting three application scenarios, namely, system function model verification, software-hardware cooperated simulation verification and prototype verification. Modules required for different application scenarios are different. Verification closure time of the functions of the system at different levels can be shortened greatly, development efficiency is increased, and debugging cost is lowered.
Description
Technical field
The present invention relates to packet processing chip design field, particularly relate to a kind of distributed packet switching chip modelling verification system and verification method.
Background technology
Along with the IP(Internet Protocol of global communication technology, Internet protocol) change process deepens continuously, and the application demand of packet switching chip is increasing, and the agreement that packet switch is relevant also increases thereupon, thus makes the exploitation of this type of chip increasingly sophisticated.
In actual chip development process, common chip checking flow process is as follows:
(1) system functional model Qualify Phase: system adopts high-level language (such as C language) to carry out the modeling of systemic-function, namely the method for Procedure modeling is utilized first to simulate out by the bag processing capacity of chip, carry out the realization of hardware description language rank after having tested again as benchmark, this process can be tested referred to as C model;
(2) the circuit simulation verification stage: adopt hardware description language for the C model function passed through after tested, complete RTL(Register Transport Level Method at Register Transfer Level) modular design, and build simulation test platform and carry out emulation testing;
(3) soft or hard collaborative simulation verification (Co-simulation) stage: carry out emulation testing by being combined by the RTL code of emulation testing and the code of chip drives software;
(4) the prototype verification stage: the RTL above by checking is comprehensively become actual real circuits, adopt specific FPGA(Field-Programmable Gate Array, field programmable gate array) obtain physics realization, and test in prototype verification plate and network test instrument formation prototype verification environment, usual chip development in this in stage just by SDK(SystemDevelopment Kit, system development tool bag) and hardware system together carry out the test of system level.
The method adopted due to above-mentioned 4 stages is different, generally needs to design separately a set of hardware for each stage or software realizes respectively, and test case cannot be multiplexing, causes whole process exception complicated.Each packet switching chip needs to support thousands of disparate networks agreements, therefore need on different stage, do a large amount of tests respectively and finally could complete checking, whole convergence process there will be repeatedly a large amount of, the functional verification of chip to be measured is tediously long at the checking convergence time of different stage, causes development progress delayed.
Summary of the invention
The invention provides a kind of distributed packet switching chip modelling verification system and verification method, distributed system architecture is adopted to carry out normalized to the proof procedure of different abstraction level, significantly can shorten the checking convergence time of chip to be measured at different stage, improve development efficiency, reduce debugging cost.
Distributed packet switching chip modelling verification system provided by the invention, comprise kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model package module, wherein, kernel control module belongs to serve end program module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model package module belong to client program module, this verification system belongs to the distributed system of client-server end-client C/S/C structure, support 3 kinds of application scenarioss: system functional model is verified simultaneously, soft or hard collaborative simulation verification, prototype verification, under different application scenarioss, required module is different,
Kernel control module, for: the message transmitted between the command line interface module that management is attached thereto, SDK proxy interface module, virtual network test instrumentation module, complete the forwarding of proprietary message between global configuration file and program module, copy, broadcast, classify, preserve, add up, simultaneously the connection of maintain message passage;
Command line interface module, for: read by the global configuration file of customization, the program module needed for current application scene is started according to the application scenarios configuration parameter read, after the connection initialization of C/S/C, for chip development, personnel provide command line interface, complete customization and the editor of test case;
SDK proxy interface module, for: receive the packet switching chip configuration to be measured that kernel control module is sent, call SDK software according to packet switching chip configuration to be measured, drive the model/prototype of packet switching chip to be measured normally to run;
Virtual network test instrumentation module, for: network test instrument that is virtually reality like reality, the packet switching chip test and excitation configuration messages to be measured forwarded according to kernel control module and response check configuration messages, complete the transmission of packet, reception, School Affairs statistics;
Virtual chip configuration module, under being only used in system functional model checking application scenarios, for preserving, upgrading, inquire about register configuration and the bag processing protocol list item of packet switching chip to be measured;
C model package module, for: read the packet switching chip configuration to be measured in virtual chip configuration module, receive the test and excitation that test module is sent, give encapsulation packet switching chip model treatment therein by packet switching chip configuration to be measured and test and excitation, the result after this packet switching chip model treatment is sent to test module; C model package module is only enabled under system functional model checking application scenarios, and packet switching chip model is connected in this distributed system.
On the basis of technique scheme, described global configuration file comprises application scenarios, types of models, service end process configuration information and some client process configuration informations, application scenarios is set to the one in system functional model checking, soft or hard collaborative simulation verification, prototype verification, for controlling the enable and operational mode of required program module in different application scenarioss; Types of models is configured to different identification according to the model of the disparate modules of chip to be measured, and under being only used in system functional model checking application scenarios, C model package module is according to the file destination of C model corresponding to model identification dynamic link; Service end process configuration information comprises IP address, port numbers, process type and device number, client process configuration information comprises process type and device number, IP address and port numbers connect for the web socket created between server module and client program module, the message channel of construction procedures intermodule; Process type is configured to different process identification (PID)s, for distinguishing different module types; In non-networking test, kernel control module will carry out corresponding operation according to process type; The chip to be measured that device number is tested for distinguishing program module, in networking test, the device number of each chip existence anduniquess to be measured, in networking test, kernel control module will carry out corresponding operation according to device number, process type, in non-networking test, device number is ignored by system.
On the basis of technique scheme, between described program module, proprietary message comprises 6 message fields: device number, source process type, target process type, coomand mode, message number, message content, wherein, device number is for distinguishing the chip to be measured of program module test, in networking test, the device number of each chip existence anduniquess to be measured, in networking test, kernel control module will carry out corresponding operation according to device number, process type, in non-networking test, device number is ignored by system; Source process type and target process type carry out source and target for what represent a message, and being convenient to kernel control module will forward according to process type, simultaneously for together calculating global message number with message number; Coomand mode is for representing the basic return state of a message; Message number is for distinguishing message different in same class program module, and kernel control module operates according to global message number; Message content is concrete message content corresponding to each message number.
On the basis of technique scheme, described coomand mode comprises and correctly returns, orders mistake and command timeout three state.
On the basis of technique scheme, described concrete message content comprises sub-message, character string information and protocol massages.
On the basis of technique scheme, the message number of each class method inside modules is independent numbering, for whole distributed system, and the overall start message numbering+message number of global message number=target process type.
On the basis of technique scheme, the debug command that the order of described test case support comprises chip configuration order to be measured, the stimulation arrangement order of virtual network test instrumentation, response expect to check regular configuration order and this distributed system.
On the basis of technique scheme, described kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model package module are distributed on same machines or different machines.
On the basis of technique scheme, described kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model package module are distributed in same operation system or different operating system.
Based on above-mentioned distributed packet switching chip modelling verification system, the embodiment of the present invention also provides a kind of distributed packet switching chip model verification method, comprises the following steps:
S1, system functional model checking scene under:
Step 101, system initialization: the application scenarios arranging global configuration is system functional model checking, configure types of models and the device number of chip to be measured, configuration kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, the process identification (PID) of virtual chip configuration module and C model package module and device number, first start kernel control module, then client program module is started, client program module is according to the IP address in global configuration, port numbers creates the message channel between kernel control module automatically, each module distribution is on one or more machine,
Step 102, test command or script typing: the various orders that user's typing command line interface module can identify, script, order, script file are converted into command messages and are sent to kernel control module by command line interface module, and command messages comprises chip configuration order to be measured, stimulation arrangement order, the regular configuration order of response expectation inspection;
Step 103, test command forward: kernel control module is according to the object process type in the command messages received and device number, by chip configuration transferring order to be measured to SDK proxy interface module, stimulation arrangement order, response are expected to check that regular configuration order is forwarded to virtual network test instrumentation module;
Step 104, chip configuration command process to be measured: SDK proxy interface module converts the chip configuration order to be measured received to concrete chip configuration, the register in write/reading virtual chip configuration module and list item data, read for C model package module;
Step 105, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order received, produce corresponding various protocol packet data, and send to C model package module, record the excitation bag data that these generate, for follow-up expectation bag data genaration is prepared simultaneously;
Step 106, response are expected to check regular configuration order process: virtual network test instrumentation module expects to check the excitation bag data of record in regular configuration order and step 105 according to the response received, calculate the respond packet data expecting to obtain, and record, prepare for automatically comparing between follow-up real response bag and the respond packet of expectation;
The bag process of step 107, C model package module: the data structure that the various excitation bag data transaction received become chip model to be measured to identify by C model wrapper, call the function of chip model to be measured, meet with a response the data structure of wrapping, convert the respond packet message format that virtual network test instrumentation module needs to, send to virtual network test instrumentation module;
Step 108, compare real response bag and Expected Response bag: the Expected Response bag that virtual network test instrumentation module records before the real response received being wrapped in compares, obtain final result, and result is preserved in the mode of file, consult for tester;
S2, under soft or hard collaborative simulation verification scene:
Step 201, system initialization: the application scenarios arranging global configuration is soft or hard collaborative simulation verification, configure types of models and the device number of chip to be measured, the process identification (PID) of configuration kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module and device number, first start kernel control module, then client program module is started, client program module creates the message channel between kernel control module automatically according to the IP address in global configuration, port numbers, and each module distribution is on one or more machine;
Step 202, test command or script typing, identical with step 102: the various orders that user's typing command line interface module can identify, script, order, script file are converted into command messages and are sent to kernel control module by command line interface module, and command messages comprises chip configuration order to be measured, stimulation arrangement order, the regular configuration order of response expectation inspection;
Step 203, test command forward, identical with step 103: kernel control module is according to the object process type in the command messages received and device number, by chip configuration transferring order to be measured to SDK proxy interface module, stimulation arrangement order, response are expected to check that regular configuration order is forwarded to virtual network test instrumentation module;
Step 204, chip configuration command process to be measured: SDK proxy interface module converts the chip configuration order to be measured received to concrete chip configuration, the Direct Programming interface DPI provided by RTL simulator calls register and the list item configuration feature of simulation test platform, completes and carries out read-write operation to the register in RTL and list item configuration; If former RTL simulation test platform does not develop corresponding register and list item configuration DPI, then add register and the next adaptive native system of list item configuration DPI;
Step 205, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order received, produce corresponding various protocol packet data, the pumping signal being called simulation test platform by DPI drives function, excitation bag data are driven on the interface signal of RTL module to be measured, record the excitation bag data that these generate, for follow-up expectation bag data genaration is prepared simultaneously; If former RTL simulation test platform is not developed corresponding pumping signal and driven DPI, then add pumping signal and drive DPI to carry out adaptive native system;
Step 206, response are expected to check regular configuration order process: virtual network test instrumentation module is expected according to the response received to check the excitation bag data recorded in regular configuration order and previous step process, calculate the respond packet data expecting to obtain, by DPI by expect respond packet stored in the simulation test platform of RTL, prepare for automatically comparing between follow-up real response bag and the respond packet of expectation; If former RTL simulation test platform does not develop corresponding Expected Response bag store DPI, then add Expected Response bag and store the next adaptive native system of DPI;
Step 207, RTL emulate: the simulation test platform of RTL obtains excitation bag data from its DPI interface, is driven on the input interface signal of RTL module, after RTL resume module completes, from the output interface signal of RTL module, obtains actual respond packet data;
Step 208, the simulation test platform inside of comparing real response bag and Expected Response bag: RTL compare the data of real response bag and Expected Response bag, obtain final result, and result are preserved in the mode of file, consult for tester;
S3, under prototype verification scene:
Step 301, system initialization: the application scenarios arranging global configuration is prototype verification, configure types of models and the device number of chip to be measured, configuration kernel control module, command line interface module, SDK proxy interface module, the process identification (PID) of virtual network test instrumentation module and device number, first start kernel control module, then client program module is started, client program module is according to the IP address in global configuration, port numbers creates the message channel between kernel control module automatically, SDK proxy interface block configuration starts in the embedded system of prototype verification plate, all the other modules are distributed on one or more machine,
Step 302, test command or script typing, identical with step 202: the various orders that user's typing command line interface module can identify, script, order, script file are converted into command messages and are sent to kernel control module by command line interface module, and command messages comprises chip configuration order to be measured, stimulation arrangement order, the regular configuration order of response expectation inspection;
Step 303, test command forward, identical with step 203: kernel control module is according to the object process type in the command messages received and device number, by chip configuration transferring order to be measured to SDK proxy interface module, stimulation arrangement order, response are expected to check that regular configuration order is forwarded to virtual network test instrumentation module;
Step 304, chip configuration command process to be measured: SDK proxy interface module converts the chip configuration order to be measured received to concrete chip configuration, call register and the list item configuration feature of SDK, complete and read-write operation is carried out to the register in FPGA to be measured and list item;
Step 305, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order received, produce corresponding various protocol packet data, by calling the Packet Generation function of live network test instrumentation, above the network interface that bag is directly delivered to prototype verification plate to be measured, record the excitation bag data that these generate, for follow-up expectation bag data genaration is prepared simultaneously;
Step 306, response are expected to check regular configuration order process: virtual network test instrumentation module is expected according to the response received to check the excitation bag data recorded in regular configuration order and previous step process, calculate the respond packet data expecting to obtain, and record, the bag simultaneously opening live network test instrumentation captures function, prepares for automatically comparing between follow-up real response bag and the respond packet of expectation;
Step 307, FPGA complete bag process: the physics realization FPGA of chip to be measured obtains excitation bag data by the network interface of prototype verification plate, process the rear network interface of respond packet data to prototype verification plate sending reality, simultaneously instrument receives respond packet, by the bag that the receives buffer memory stored in its inside;
Step 308, compare real response bag and Expected Response bag, after virtual network test instrumentation module distributes all excitation bags, the bag calling live network test instrumentation captures buffer memory read functions, obtain actual respond packet data, compare with the Expected Response bag recorded before, obtain final result, and result is preserved in the mode of file, consult for tester.
Compared with prior art, advantage of the present invention is as follows:
(1) the present invention is applicable to the whole process of packet switching chip checking, especially Front End Authentication, effect highly significant, all testing cases can be completed during initial stage system model checking, follow-up soft or hard collaborative simulation stage and prototype verification stage still can continue to use before test case, when not revising original test case, only need revise a small amount of global configuration parameter, just seamless switching can be realized, full automaticly complete all tests, significantly can shorten the checking convergence time of chip to be measured at different stage, improve development efficiency.
(2) the present invention can utilize multiple program module parallel running be distributed on different machines, and overall operational efficiency is improved.
(3) SDK is directly embedded in distributed system in chip development by the present invention in early days, verify in advance, like this, usually the initial stage being operated in chip development needing prototype verification plate by the time can carry out after completing just completes together with other work, and SDK is reused in the prototype verification in later stage, SDK is now by checking, thus can improve the efficiency of system testing in prototype verification, reduce debugging cost.
(4) often there is the networking test of multi-chip in the chip testing of packet switch class, traditional verification system and method are difficult to support usually, and distributed system architecture of the present invention can support that the networking of multiple chip to be measured is tested easily.
(5) distributed system architecture of the present invention defines proprietary communication information mechanism, by adding message conversion program, the message content of native system is converted into the operation (simulator of such as hardware description language that other various software/hardware systems can accept, network test instrument command interface), message conversion program and kernel control module can carry out message communicating, thus complete interconnected.Because the system of usual 3rd side has the socket of oneself, because the unified message format for communications of this distributed system definition, so only can complete interconnected with completing the instruction interface that message can identify to the 3rd method, system, the mode of inner processing messages is still constant.If not distributed system architecture, there is no this message mechanism, and the interconnected of other system will be difficult to, and just can complete together with the software library that can only provide with other system is compiled in native system.
Accompanying drawing explanation
Fig. 1 is the structural representation of distributed packet switching chip modelling verification system in the embodiment of the present invention.
Fig. 2 is the structural representation of system global configuration in the embodiment of the present invention.
Fig. 3 is the structural representation of inter-process messages in the embodiment of the present invention.
Fig. 4 is the flow chart of system functional model checking in the embodiment of the present invention.
Fig. 5 is the flow chart of soft or hard collaborative simulation verification in the embodiment of the present invention.
Fig. 6 is the flow chart of embodiment of the present invention mesarcs checking.
Embodiment
Below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.
Shown in Figure 1, the embodiment of the present invention provides a kind of distributed packet switching chip modelling verification system, comprise kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model package module, wherein, kernel control module belongs to serve end program module, and command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model package module belong to client program module.This verification system belongs to C/S/C(Client-Server-Client client-server end-client) distributed system of structure, support 3 kinds of application scenarioss: system functional model checking, soft or hard collaborative simulation verification, prototype verification, program module required under different application scenarioss is different simultaneously.
Kernel control module, belong to the serve end program of whole distributed system, for: the message transmitted between the command line interface module that management is attached thereto, SDK proxy interface module, virtual network test instrumentation module, complete the forwarding of the proprietary message format (hereinafter further illustrating) of the embodiment of the present invention, copy, broadcast, classify, preserve, add up, simultaneously the connection of maintain message passage.
Command line interface module, for: read by the proprietary global configuration file (hereinafter will further illustrate) of the embodiment of the present invention of customization, the program module needed for current application scene is started according to the application scenarios configuration parameter read, after the connection initialization of C/S/C, for chip development, personnel provide command line interface, complete customization and the editor of test case.The order of test case support comprises chip configuration order to be measured, and the stimulation arrangement order of virtual network test instrumentation, response are expected to check regular configuration order, and the debug command etc. of this distributed system.Test case, the mode can keyed in order line sends into command line interface, also can be that a script file finished writing in advance (comprising the text of many orders) sends into command interface, the proprietary message format that all orders are transformed into the embodiment of the present invention by this module sends to kernel control module, and receive order operation result message from kernel control module, extract operation result in message and be presented in order line.In addition, all command interaction records of this module all will be recorded in journal file, convenient debugging and analytical test result.
SDK proxy interface module, for: receive the packet switching chip configuration to be measured that kernel control module is sent, call SDK software according to packet switching chip configuration to be measured, drive the model/prototype of packet switching chip to be measured normally to run; Its operational mode can change according to the difference of application scenarios configuration parameter in global configuration.(hereinafter can further illustrate).
Virtual network test instrumentation module, for: network test instrument that is virtually reality like reality, the packet switching chip test and excitation configuration messages to be measured forwarded according to kernel control module and response check configuration messages, complete the transmission of packet, reception, School Affairs statistics; Its operational mode can change according to the difference of application scenarios configuration parameter in global configuration.
Virtual chip configuration module, for: register configuration and the bag processing protocol list item of preserving, upgrade, inquire about packet switching chip to be measured.Virtual chip configuration module is only enabled under system functional model checking application scenarios, and for soft or hard collaborative simulation verification and these 2 kinds of application scenarioss of prototype verification, the side circuit of function respectively in RTL module and in FPGA of this module completes.
C model package module, for: read the packet switching chip configuration to be measured in virtual chip configuration module, receive the test and excitation that test module is sent, give encapsulation packet switching chip model treatment therein by packet switching chip configuration to be measured and test and excitation, the result after this packet switching chip model treatment is sent to test module.In packet switching chip model treatment process, the packet switching chip configuration to be measured in virtual chip configuration module may be revised.C model package module is only enabled under system functional model checking application scenarios, packet switching chip model is enable to be connected in this distributed system, for soft or hard collaborative simulation verification and these 2 kinds of application scenarioss of prototype verification, the way of realization of packet switching chip to be measured is respectively the side circuit in RTL code and FPGA.
Above-mentioned 6 program modules can run on different machines as independently process, above different operating system, finally form whole distributed validation system.
In order to complete the interconnected of whole distributed validation system and intercommunication control, the embodiment of the present invention has formulated proprietary message format between proprietary global configuration file form and program module.
Shown in Figure 2, global configuration file comprises application scenarios, types of models, service end process configuration information and some client process configuration informations, application scenarios is set to the one in system functional model checking, soft or hard collaborative simulation verification, prototype verification, for controlling the enable and operational mode of required program module in above-mentioned 6 program modules in different application scenarioss; Proof procedure is completing step by step, may be that module to be measured is one by one verified in the present system at the beginning, and then module spliced to be measured is connected into as complete chip to be measured, each module/chip correspondence in system functional model checking becomes a C model, therefore needs selection to be which model.Types of models is configured to different identification according to the model of the disparate modules of chip to be measured, and under being only used in system functional model checking application scenarios, C model package module is according to the file destination of C model corresponding to model identification dynamic link; Service end process configuration information comprises IP address, port numbers, process type and device number, client process configuration information comprises process type and device number, IP address and port numbers connect for the web socket (Socket) created between server module and client program module, the message channel of construction procedures intermodule; Process type is configured to different process identification (PID)s, for distinguishing above-mentioned 6 kinds of different program module types, here arranging is arrange mark to each program module started that needs, and it is from that such core controller could differentiate message for which program module, needs to be forwarded to which program module.In non-networking test, kernel control module will carry out corresponding operation according to process type; Device number is for distinguishing the chip to be measured of program module test, in networking test, the device number of each chip existence anduniquess to be measured, in networking test, kernel control module will carry out corresponding operation according to device number, process type, in non-networking test, this device number will be ignored by system.
Under different application scenarioss, the program module type that global configuration item starts as required, inserts above-mentioned configuration one by one, and the configuration not needing its module type of program module started to be correlated with should not be inserted (hereinafter further specified).
Shown in Figure 3, between program module, proprietary message comprises 6 message fields: device number, source process type, target process type, coomand mode, message number, message content, wherein, the chip to be measured that device number is tested for distinguishing program module, in networking test, the device number of each chip existence anduniquess to be measured, in networking test, kernel control module will carry out corresponding operation according to device number, process type, in non-networking test, this device number will be ignored by system; Source process type and target process type carry out source and target for what represent a message, and being convenient to kernel control module will forward according to process type, simultaneously for together calculating global message number with message number; Coomand mode, for representing the basic return state of a message, comprises and correctly returns, orders mistake and command timeout three state; Message number is for distinguishing message different in same class program module, the message number of each class method inside modules is independent numbering, for whole distributed system, the overall start message numbering+message number of global message number=target process type, kernel control module operates according to global message number; Message content is concrete message content corresponding to each message number, the data of any byte can be deposited in theory, concrete message content comprises sub-message (such as order comprises multiple parameter), character string information and protocol massages (as all kinds of bag data) etc., according to the multiple different messages that the function of each module needs and processes, concrete message content is relevant with the concrete function of chip to be measured, between the program module in the embodiment of the present invention, proprietary message format is as a kind of general message format, goes for various packet switch type chip to be measured.
Based on above-mentioned distributed packet switching chip modelling verification system (comprising global configuration and program module message mechanism), the embodiment of the present invention provides a kind of distributed packet switching chip model verification method, 3 kinds of application scenarioss can be supported: system functional model checking, soft or hard collaborative simulation verification, prototype verification, be described in detail below simultaneously.
The distributed packet switching chip model verification method that the embodiment of the present invention provides, comprises the following steps:
S1, shown in Figure 4, under system functional model checking scene:
Step 101, system initialization: the application scenarios arranging global configuration is system functional model checking, configure types of models and the device number of chip to be measured, configuration kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, the process identification (PID) of virtual chip configuration module and C model package module and device number, first start serve end program module, i.e. kernel control module, then client program module is started, client program module is according to the IP address in global configuration, port numbers creates the message channel between kernel control module automatically, the position that modules starts place is not limit, can on a machine, also can be distributed on multiple stage machine,
Step 102, test command or script typing: the various orders that user's typing command line interface module can identify, script, order, script file are converted into command messages and are sent to kernel control module by command line interface module, and command messages comprises chip configuration order to be measured, stimulation arrangement order, the regular configuration order of response expectation inspection;
Step 103, test command forward: kernel control module is according to the object process type in the command messages received and device number, by chip configuration transferring order to be measured to SDK proxy interface module, stimulation arrangement order, response are expected to check that regular configuration order is forwarded to virtual network test instrumentation module;
Step 104, chip configuration command process to be measured: SDK proxy interface module converts the chip configuration order to be measured received to concrete chip configuration, the register in write/reading virtual chip configuration module and list item data, read for C model package module;
Step 105, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order received, produce corresponding various protocol packet data, and send to C model package module, record the excitation bag data that these generate, for follow-up expectation bag data genaration is prepared simultaneously;
Step 106, response are expected to check regular configuration order process: virtual network test instrumentation module expects to check the excitation bag data of record in regular configuration order and step 105 according to the response received, calculate the respond packet data expecting to obtain, and record, prepare for automatically comparing between follow-up real response bag and the respond packet of expectation;
The bag process of step 107, C model package module: the data structure that the various excitation bag data transaction received become chip model to be measured to identify by C model wrapper, call the function of chip model to be measured, meet with a response the data structure of wrapping, convert the respond packet message format that virtual network test instrumentation module needs to, send to virtual network test instrumentation module;
Step 108, compare real response bag and Expected Response bag: the Expected Response bag that virtual network test instrumentation module records before the real response received being wrapped in compares, obtain final result, and result is preserved in the mode of file, consult for tester.
S2, shown in Figure 5, under soft or hard collaborative simulation verification scene:
Step 201, system initialization: the application scenarios arranging global configuration is soft or hard collaborative simulation verification, configure types of models and the device number of chip to be measured, configuration kernel control module, command line interface module, SDK proxy interface module, the process identification (PID) of virtual network test instrumentation module and device number, first start serve end program module, i.e. kernel control module, then client program module is started, client program module is according to the IP address in global configuration, port numbers creates the message channel between kernel control module automatically, the position that modules starts place is not limit, can on a machine, also can be distributed on multiple stage machine,
Global configuration under soft or hard collaborative simulation verification scene and system functional model verify that the global configuration under scene contrasts, difference is application scenarios to change to soft or hard collaborative simulation verification, remove process identification (PID) and the device number of virtual chip configuration module and C model package module, all the other initialization operations are consistent with under system functional model checking scene;
Step 202, test command or script typing, identical with step 102: the various orders that user's typing command line interface module can identify, script, order, script file are converted into command messages and are sent to kernel control module by command line interface module, and command messages comprises chip configuration order to be measured, stimulation arrangement order, the regular configuration order of response expectation inspection;
Step 203, test command forward, identical with step 103: kernel control module is according to the object process type in the command messages received and device number, by chip configuration transferring order to be measured to SDK proxy interface module, stimulation arrangement order, response are expected to check that regular configuration order is forwarded to virtual network test instrumentation module;
Step 204, chip configuration command process to be measured: SDK proxy interface module converts the chip configuration order to be measured received to concrete chip configuration, the DPI(Direct Programming Interface provided by RTL simulator, Direct Programming interface) call register and the list item configuration feature of simulation test platform, complete and read-write operation is carried out to the register in RTL and list item configuration; If former RTL simulation test platform does not develop corresponding register and list item configuration DPI, then must add register and the next adaptive native system of list item configuration DPI;
Step 205, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order received, produce corresponding various protocol packet data, the pumping signal being called simulation test platform by DPI drives function, excitation bag data are driven on the interface signal of RTL module to be measured, record the excitation bag data that these generate, for follow-up expectation bag data genaration is prepared simultaneously; If former RTL simulation test platform is not developed corresponding pumping signal and driven DPI, then must add pumping signal and drive DPI to carry out adaptive native system;
Step 206, response are expected to check regular configuration order process: virtual network test instrumentation module is expected according to the response received to check the excitation bag data recorded in regular configuration order and previous step process, calculate the respond packet data expecting to obtain, by DPI by expect respond packet stored in the simulation test platform of RTL, prepare for automatically comparing between follow-up real response bag and the respond packet of expectation; If former RTL simulation test platform does not develop corresponding Expected Response bag store DPI, then must add Expected Response bag and store the next adaptive native system of DPI;
Step 207, RTL emulate: the simulation test platform of RTL obtains excitation bag data from its DPI interface, be driven on the input interface signal of RTL module, after RTL resume module completes, from the output interface signal of RTL module, obtain actual respond packet data;
Step 208, the simulation test platform inside of comparing real response bag and Expected Response bag: RTL compare the data of real response bag and Expected Response bag, obtain final result, and result are preserved in the mode of file, consult for tester.
S3, shown in Figure 6, under prototype verification scene:
Step 301, system initialization: the application scenarios arranging global configuration is prototype verification, configure types of models and the device number of chip to be measured, configuration kernel control module, command line interface module, SDK proxy interface module, the process identification (PID) of virtual network test instrumentation module and device number, first start serve end program module, i.e. kernel control module, then client program module is started, client program module is according to the IP address in global configuration, port numbers creates the message channel between kernel control module automatically, SDK proxy interface block configuration starts in the embedded system of prototype verification plate, the position that all the other modules start place is not limit, can on a machine, also can be distributed on multiple stage machine,
Global configuration under global configuration under prototype verification scene and soft or hard collaborative simulation verification scene is basically identical, it is prototype verification that difference is application scenarios configuration change, SDK proxy interface module must be configured in the embedded system of prototype verification plate and start simultaneously, and the enable position of all the other modules does not limit;
Step 302, test command or script typing, identical with step 202: the various orders that user's typing command line interface module can identify, script, order, script file are converted into command messages and are sent to kernel control module by command line interface module, and command messages comprises chip configuration order to be measured, stimulation arrangement order, the regular configuration order of response expectation inspection;
Step 303, test command forward, identical with step 203: kernel control module is according to the object process type in the command messages received and device number, by chip configuration transferring order to be measured to SDK proxy interface module, stimulation arrangement order, response are expected to check that regular configuration order is forwarded to virtual network test instrumentation module;
Step 304, chip configuration command process to be measured: SDK proxy interface module converts the chip configuration order to be measured received to concrete chip configuration, call register and the list item configuration feature of SDK, complete and read-write operation is carried out to the register in FPGA to be measured and list item;
Step 305, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order received, produce corresponding various protocol packet data, by calling the Packet Generation function of live network test instrumentation, above the network interface that bag is directly delivered to prototype verification plate to be measured, record the excitation bag data that these generate, for follow-up expectation bag data genaration is prepared simultaneously;
Step 306, response are expected to check regular configuration order process: virtual network test instrumentation module is expected according to the response received to check the excitation bag data recorded in regular configuration order and previous step process, calculate the respond packet data expecting to obtain, and record, the bag simultaneously opening live network test instrumentation captures function, prepares for automatically comparing between follow-up real response bag and the respond packet of expectation;
Step 307, FPGA complete bag process: the physics realization of FPGA(chip to be measured) obtain excitation bag data by the network interface of prototype verification plate, process the rear network interface of respond packet data to prototype verification plate sending reality, simultaneously instrument receives respond packet, and its bag captures function can by the bag that the receives buffer memory stored in its inside;
Step 308, compare real response bag and Expected Response bag, after virtual network test instrumentation module distributes all excitation bags, the bag calling live network test instrumentation captures buffer memory read functions, thus obtain actual respond packet data, the Expected Response bag before recorded compares, obtain final result, and result is preserved in the mode of file, consult for tester.
Those skilled in the art can carry out various modifications and variations to the embodiment of the present invention, if these amendments and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then these revise and modification also within protection scope of the present invention.
The prior art that the content do not described in detail in specification is known to the skilled person.
Claims (10)
1. a distributed packet switching chip modelling verification system, it is characterized in that: comprise kernel control module, command line interface module, system development tool bag SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model package module, wherein, kernel control module belongs to serve end program module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model package module belong to client program module, this verification system belongs to the distributed system of client-server end-client C/S/C structure, support 3 kinds of application scenarioss: system functional model is verified simultaneously, soft or hard collaborative simulation verification, prototype verification, under different application scenarioss, required module is different,
Kernel control module, for: the message transmitted between the command line interface module that management is attached thereto, SDK proxy interface module, virtual network test instrumentation module, complete the forwarding of proprietary message between global configuration file and program module, copy, broadcast, classify, preserve, add up, simultaneously the connection of maintain message passage;
Command line interface module, for: read by the global configuration file of customization, the program module needed for current application scene is started according to the application scenarios configuration parameter read, after the connection initialization of C/S/C, for chip development, personnel provide command line interface, complete customization and the editor of test case;
SDK proxy interface module, for: receive the packet switching chip configuration to be measured that kernel control module is sent, call SDK software according to packet switching chip configuration to be measured, drive the model/prototype of packet switching chip to be measured normally to run;
Virtual network test instrumentation module, for: network test instrument that is virtually reality like reality, the packet switching chip test and excitation configuration messages to be measured forwarded according to kernel control module and response check configuration messages, complete the transmission of packet, reception, School Affairs statistics;
Virtual chip configuration module, under being only used in system functional model checking application scenarios, for preserving, upgrading, inquire about register configuration and the bag processing protocol list item of packet switching chip to be measured;
C model package module, for: read the packet switching chip configuration to be measured in virtual chip configuration module, receive the test and excitation that test module is sent, give encapsulation packet switching chip model treatment therein by packet switching chip configuration to be measured and test and excitation, the result after this packet switching chip model treatment is sent to test module; C model package module is only enabled under system functional model checking application scenarios, and packet switching chip model is connected in this distributed system.
2. distributed packet switching chip modelling verification system as claimed in claim 1, it is characterized in that: described global configuration file comprises application scenarios, types of models, service end process configuration information and some client process configuration informations, application scenarios is set to the one in system functional model checking, soft or hard collaborative simulation verification, prototype verification, for controlling the enable and operational mode of required program module in different application scenarioss; Types of models is configured to different identification according to the model of the disparate modules of chip to be measured, and under being only used in system functional model checking application scenarios, C model package module is according to the file destination of C model corresponding to model identification dynamic link; Service end process configuration information comprises IP address, port numbers, process type and device number, client process configuration information comprises process type and device number, IP address and port numbers connect for the web socket created between server module and client program module, the message channel of construction procedures intermodule; Process type is configured to different process identification (PID)s, for distinguishing different module types; In non-networking test, kernel control module will carry out corresponding operation according to process type; The chip to be measured that device number is tested for distinguishing program module, in networking test, the device number of each chip existence anduniquess to be measured, in networking test, kernel control module will carry out corresponding operation according to device number, process type, in non-networking test, device number is ignored by system.
3. distributed packet switching chip modelling verification system as claimed in claim 1, it is characterized in that: between described program module, proprietary message comprises 6 message fields: device number, source process type, target process type, coomand mode, message number, message content, wherein, device number is for distinguishing the chip to be measured of program module test, in networking test, the device number of each chip existence anduniquess to be measured, in networking test, kernel control module will according to device number, process type carries out corresponding operation, in non-networking test, device number is ignored by system, source process type and target process type carry out source and target for what represent a message, and being convenient to kernel control module will forward according to process type, simultaneously for together calculating global message number with message number, coomand mode is for representing the basic return state of a message, message number is for distinguishing message different in same class program module, and kernel control module operates according to global message number, message content is concrete message content corresponding to each message number.
4. distributed packet switching chip modelling verification system as claimed in claim 3, is characterized in that: described coomand mode comprises and correctly returns, orders mistake and command timeout three state.
5. distributed packet switching chip modelling verification system as claimed in claim 3, is characterized in that: described concrete message content comprises sub-message, character string information and protocol massages.
6. distributed packet switching chip modelling verification system as claimed in claim 3, it is characterized in that: the message number of each class method inside modules is independent numbering, for whole distributed system, the overall start message numbering+message number of global message number=target process type.
7. the distributed packet switching chip modelling verification system according to any one of claim 1 to 6, is characterized in that: the debug command that the order of described test case support comprises chip configuration order to be measured, the stimulation arrangement order of virtual network test instrumentation, response expect to check regular configuration order and this distributed system.
8. the distributed packet switching chip modelling verification system according to any one of claim 1 to 6, is characterized in that: described kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model package module are distributed on same machines or different machines.
9. the distributed packet switching chip modelling verification system according to any one of claim 1 to 6, is characterized in that: described kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module, virtual chip configuration module and C model package module are distributed in same operation system or different operating system.
10., based on a distributed packet switching chip model verification method for the distributed packet switching chip modelling verification system according to any one of claim 1 to 9, comprise the following steps:
S1, system functional model checking scene under:
Step 101, system initialization: the application scenarios arranging global configuration is system functional model checking, configure types of models and the device number of chip to be measured, configuration kernel control module, command line interface module, system development tool bag SDK proxy interface module, virtual network test instrumentation module, the process identification (PID) of virtual chip configuration module and C model package module and device number, first start kernel control module, then client program module is started, client program module is according to the IP address in global configuration, port numbers creates the message channel between kernel control module automatically, each module distribution is on one or more machine,
Step 102, test command or script typing: the various orders that user's typing command line interface module can identify, script, order, script file are converted into command messages and are sent to kernel control module by command line interface module, and command messages comprises chip configuration order to be measured, stimulation arrangement order, the regular configuration order of response expectation inspection;
Step 103, test command forward: kernel control module is according to the object process type in the command messages received and device number, by chip configuration transferring order to be measured to SDK proxy interface module, stimulation arrangement order, response are expected to check that regular configuration order is forwarded to virtual network test instrumentation module;
Step 104, chip configuration command process to be measured: SDK proxy interface module converts the chip configuration order to be measured received to concrete chip configuration, the register in write/reading virtual chip configuration module and list item data, read for C model package module;
Step 105, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order received, produce corresponding various protocol packet data, and send to C model package module, record the excitation bag data that these generate, for follow-up expectation bag data genaration is prepared simultaneously;
Step 106, response are expected to check regular configuration order process: virtual network test instrumentation module expects to check the excitation bag data of record in regular configuration order and step 105 according to the response received, calculate the respond packet data expecting to obtain, and record, prepare for automatically comparing between follow-up real response bag and the respond packet of expectation;
The bag process of step 107, C model package module: the data structure that the various excitation bag data transaction received become chip model to be measured to identify by C model wrapper, call the function of chip model to be measured, meet with a response the data structure of wrapping, convert the respond packet message format that virtual network test instrumentation module needs to, send to virtual network test instrumentation module;
Step 108, compare real response bag and Expected Response bag: the Expected Response bag that virtual network test instrumentation module records before the real response received being wrapped in compares, obtain final result, and result is preserved in the mode of file, consult for tester;
S2, under soft or hard collaborative simulation verification scene:
Step 201, system initialization: the application scenarios arranging global configuration is soft or hard collaborative simulation verification, configure types of models and the device number of chip to be measured, the process identification (PID) of configuration kernel control module, command line interface module, SDK proxy interface module, virtual network test instrumentation module and device number, first start kernel control module, then client program module is started, client program module creates the message channel between kernel control module automatically according to the IP address in global configuration, port numbers, and each module distribution is on one or more machine;
Step 202, test command or script typing, identical with step 102: the various orders that user's typing command line interface module can identify, script, order, script file are converted into command messages and are sent to kernel control module by command line interface module, and command messages comprises chip configuration order to be measured, stimulation arrangement order, the regular configuration order of response expectation inspection;
Step 203, test command forward, identical with step 103: kernel control module is according to the object process type in the command messages received and device number, by chip configuration transferring order to be measured to SDK proxy interface module, stimulation arrangement order, response are expected to check that regular configuration order is forwarded to virtual network test instrumentation module;
Step 204, chip configuration command process to be measured: SDK proxy interface module converts the chip configuration order to be measured received to concrete chip configuration, the Direct Programming interface DPI provided by Method at Register Transfer Level RTL simulator calls register and the list item configuration feature of simulation test platform, completes and carries out read-write operation to the register in RTL and list item configuration; If former RTL simulation test platform does not develop corresponding register and list item configuration DPI, then add register and the next adaptive native system of list item configuration DPI;
Step 205, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order received, produce corresponding various protocol packet data, the pumping signal being called simulation test platform by DPI drives function, excitation bag data are driven on the interface signal of RTL module to be measured, record the excitation bag data that these generate, for follow-up expectation bag data genaration is prepared simultaneously; If former RTL simulation test platform is not developed corresponding pumping signal and driven DPI, then add pumping signal and drive DPI to carry out adaptive native system;
Step 206, response are expected to check regular configuration order process: virtual network test instrumentation module is expected according to the response received to check the excitation bag data recorded in regular configuration order and previous step process, calculate the respond packet data expecting to obtain, by DPI by expect respond packet stored in the simulation test platform of RTL, prepare for automatically comparing between follow-up real response bag and the respond packet of expectation; If former RTL simulation test platform does not develop corresponding Expected Response bag store DPI, then add Expected Response bag and store the next adaptive native system of DPI;
Step 207, RTL emulate: the simulation test platform of RTL obtains excitation bag data from its DPI interface, is driven on the input interface signal of RTL module, after RTL resume module completes, from the output interface signal of RTL module, obtains actual respond packet data;
Step 208, the simulation test platform inside of comparing real response bag and Expected Response bag: RTL compare the data of real response bag and Expected Response bag, obtain final result, and result are preserved in the mode of file, consult for tester;
S3, under prototype verification scene:
Step 301, system initialization: the application scenarios arranging global configuration is prototype verification, configure types of models and the device number of chip to be measured, configuration kernel control module, command line interface module, SDK proxy interface module, the process identification (PID) of virtual network test instrumentation module and device number, first start kernel control module, then client program module is started, client program module is according to the IP address in global configuration, port numbers creates the message channel between kernel control module automatically, SDK proxy interface block configuration starts in the embedded system of prototype verification plate, all the other modules are distributed on one or more machine,
Step 302, test command or script typing, identical with step 202: the various orders that user's typing command line interface module can identify, script, order, script file are converted into command messages and are sent to kernel control module by command line interface module, and command messages comprises chip configuration order to be measured, stimulation arrangement order, the regular configuration order of response expectation inspection;
Step 303, test command forward, identical with step 203: kernel control module is according to the object process type in the command messages received and device number, by chip configuration transferring order to be measured to SDK proxy interface module, stimulation arrangement order, response are expected to check that regular configuration order is forwarded to virtual network test instrumentation module;
Step 304, chip configuration command process to be measured: SDK proxy interface module converts the chip configuration order to be measured received to concrete chip configuration, call register and the list item configuration feature of SDK, complete and read-write operation is carried out to the register in FPGA to be measured and list item;
Step 305, stimulation arrangement command process: virtual network test instrumentation module is according to the stimulation arrangement order received, produce corresponding various protocol packet data, by calling the Packet Generation function of live network test instrumentation, above the network interface that bag is directly delivered to prototype verification plate to be measured, record the excitation bag data that these generate, for follow-up expectation bag data genaration is prepared simultaneously;
Step 306, response are expected to check regular configuration order process: virtual network test instrumentation module is expected according to the response received to check the excitation bag data recorded in regular configuration order and previous step process, calculate the respond packet data expecting to obtain, and record, the bag simultaneously opening live network test instrumentation captures function, prepares for automatically comparing between follow-up real response bag and the respond packet of expectation;
Step 307, FPGA complete bag process: the physics realization FPGA of chip to be measured obtains excitation bag data by the network interface of prototype verification plate, process the rear network interface of respond packet data to prototype verification plate sending reality, simultaneously instrument receives respond packet, by the bag that the receives buffer memory stored in its inside;
Step 308, compare real response bag and Expected Response bag, after virtual network test instrumentation module distributes all excitation bags, the bag calling live network test instrumentation captures buffer memory read functions, obtain actual respond packet data, compare with the Expected Response bag recorded before, obtain final result, and result is preserved in the mode of file, consult for tester.
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Effective date of registration: 20170606 Address after: 430074, Hubei Wuhan East Lake Development Zone, Kanto Industrial Park, beacon Road, optical communications building, industrial building, two floor Patentee after: Wuhan flying Microelectronics Technology Co., Ltd. Address before: China Science and Technology Park Dongxin road East Lake Development Zone 430074 Hubei Province, Wuhan City, No. 5 Patentee before: Fenghuo Communication Science &. Technology Co., Ltd. |
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Effective date of registration: 20170808 Address after: 430000 East Lake high tech Development Zone, Hubei Province, No. 6, No., high and new technology development zone, No. four Co-patentee after: Wuhan flying Microelectronics Technology Co., Ltd. Patentee after: Fenghuo Communication Science &. Technology Co., Ltd. Address before: 430074, Hubei Wuhan East Lake Development Zone, Kanto Industrial Park, beacon Road, optical communications building, industrial building, two floor Patentee before: Wuhan flying Microelectronics Technology Co., Ltd. |
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Effective date of registration: 20210722 Address after: 430074 second floor, optical communication building, Fenghuo Road, Guandong Industrial Park, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: WUHAN FISILINK MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 430000 No. 6, High-tech Fourth Road, Donghu High-tech Development Zone, Wuhan City, Hubei Province Patentee before: FIBERHOME TELECOMMUNICATION TECHNOLOGIES Co.,Ltd. Patentee before: WUHAN FISILINK MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
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Effective date of registration: 20220602 Address after: 430000 Room 403, 4th floor, Optics Valley Science and technology building, No. 770, Gaoxin Avenue, Wuhan East Lake New Technology Development Zone, Wuhan City, Hubei Province kjdsa2022006 (Wuhan area of the free trade zone) Patentee after: Wuhan binary semiconductor Co.,Ltd. Address before: 430074 second floor, optical communication building, Fenghuo Road, Guandong Industrial Park, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: WUHAN FISILINK MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
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