CN111859834B - UVM-based verification platform development method, system, terminal and storage medium - Google Patents
UVM-based verification platform development method, system, terminal and storage medium Download PDFInfo
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Abstract
The invention provides a verification platform development method, a verification platform development system, a verification platform development terminal and a verification platform development storage medium based on UVM, wherein the verification platform development method comprises the following steps: predefining a new verification component and a verification IP of the verification platform to obtain an integrated parameter; compiling a flow script by a code generator according to the integrated parameters; and the simulator calls the compiling flow script to complete the compiling and verifying simulation work of the verifying platform. The invention can realize the integration of new components and verification IP into the verification environment generated by the code generator through the analysis of the predefined related configuration parameters, thereby expanding into a new verification platform.
Description
Technical Field
The invention belongs to the technical field of verification methods, and particularly relates to a verification platform development method, a verification platform development system, a verification platform development terminal and a storage medium based on UVM.
Background
With the rapid development of integrated circuits, the chip industry is becoming popular, and the chip verification work used most in IC development is becoming more and more important. As a new generation of verification methodology, UVM ("universal verification methodology") is widely used in large-scale IC design verification and FPGA test verification, and with the continuous increase of design scale, the workload of building a verification platform based on UVM is also increasing, and development, management, maintenance, reuse, and the like of a verification component and VIP used on the basis of the verification platform are also more and more important and complex. Meanwhile, because SV (System Verilog, hardware design and verification language) and UVM are complex and flexible, the same function is often realized in multiple modes, the decision difficulty of verification testers in building a UVM platform is indirectly increased, and the decision difficulty is higher for beginners who are not familiar with SV and UVM methodologies.
At present, all large EDA manufacturers and enterprises develop corresponding verification platform automation tools, namely code generators, in the development process, after a verification engineer masters the UVM verification structure characteristics of the corresponding verification tools, a complete verification environment can be provided directly and rapidly through the verification platform automation tools, the time for constructing and debugging the verification environment is saved, the overall verification efficiency is improved from a higher level, and chip verification tasks are completed as early as possible. The current common verification platform code generator is a Doulos UVM code generator-Easier UVM generator, the code generator can be used as input through a series of template files, embedded files (user-defined codes) and design files to be tested, a verification environment can analyze configuration information contained in the input files according to a set verification directory structure, a set of complete verification platform and simulation flow can be generated as required, and a verification engineer can start functional simulation verification only by executing simulation scripts of a corresponding simulator under a simulation path. The code generator fills the corresponding verification components in a fragmented small program segment embedding mode respectively, and codes in corresponding files can be automatically synchronized into the corresponding generated code modules as long as relevant paths are set. The tool not only can directly call each EDA simulator through the simulator script to realize simulation, but also can directly support the realization of online simulation through an online simulation website edaplyground, and is greatly convenient for UVM learning and researchers. Meanwhile, the generator is based on the open source design of Perl, a user can modify and update the generator according to the requirement, and the development flexibility of the verification platform is greatly improved for project development.
However, such code generators also face a significant problem: nowadays, various items of various sizes usually involve some IP address bus integration related modules, corresponding verification IP addresses are introduced into the modules and verification related to the modules, and since a simple UVM code generator can only be developed through a fixed verification framework, the tool cannot meet the requirements if an existing verification IP sub-verification system is integrated into a project verification environment.
Disclosure of Invention
In view of the above deficiencies in the prior art, the present invention provides a method, a system, a terminal and a storage medium for developing a verification platform based on UVM, so as to solve the above technical problems.
In a first aspect, the present invention provides a verification platform development method based on UVM, including:
predefining a new verification component and a verification IP of the verification platform to obtain an integrated parameter;
compiling a flow script by a code generator according to the integrated parameters;
and the simulator calls the compiling flow script to complete the compiling and verifying simulation work of the verifying platform.
Further, the predefining new verification components of the verification platform and verification IPs thereof includes:
importing a new verification component and a definition packet of a verification IP thereof and compiling;
interface classes in the instantiation definition package are connected to the design to be tested;
instantiating and transferring a top-level structure in the definition package;
instantiating a sequence library of new components;
performing coordination synchronization on the sequencers and the sequence library of the new component in all verification environments;
and creating a test case according to the use scene of the design to be tested.
Further, the method further comprises: predefined integration parameters are stored in a common template file.
Further, the code generator compiles a flow script according to the integration parameters, including:
the code generator analyzes the predefined integration parameters to automatically generate a register model and a corresponding functional test sequence, so that a new component and a verification IP are integrated into a verification environment generated by the code generator;
and compiling the flow script of the development method through the register model.
Further, instantiating the interface class in the definition package and connecting to the design to be tested includes:
instantiating the interface class in the interface definition packet in a verification environment and completing the transmission of the interface class;
and finishing the signal connection between the interface class and the design to be tested in the pin list file.
Further, the coordinating and synchronizing the sequencers and the new component sequence libraries in all verification environments comprises:
performing one-to-one linkage on all the virtual sequencers of the top-level structure, all the verification components and the sub sequencers of the verification IP thereof;
performing one-to-one linking of each sub-sequencer handle in the virtual sequencer and an underlying verification component sequencer entity object;
and performing one-to-one association on all verification components and the sequence library and the top-level sequence of the verification IP.
Further, the defining includes: a top level definition package and an interface definition package.
In a second aspect, the present invention provides a verification platform development system based on UVM, including:
the predefined unit is configured for predefining a new verification component of the verification platform and a verification IP thereof to obtain an integrated parameter;
the script compiling unit is configured for compiling the flow script according to the integrated parameters by the code generator;
and the compiling simulation unit is configured for calling the compiling flow script by the simulator to finish the compiling and verifying simulation work of the verifying platform.
The new face provides a terminal, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is configured to call and run the computer program from the memory, so that the terminal performs the method of the terminal described above.
In a fourth aspect, a computer-readable storage medium is provided, having stored therein instructions, which when executed on a computer, cause the computer to perform the method of the above aspects.
The invention has the beneficial effects that,
according to the verification platform development method, system, terminal and storage medium based on UVM, the new component and the verification IP can be integrated into the verification environment generated by the code generator through the analysis of the predefined related configuration parameters; the flexible configuration and calling of the whole verification platform, the required integrated verification component and the verification IP are realized through developing the universal template; a new simulation flow script generated based on a Make tool is developed, and flexible simulation flow automation is realized; the invention realizes the development and integration of the verification component based on the platform, and by the novel automatic generation tool, a verifier can completely set up a complex UVM platform structure without the need of the structure, and the integration and configuration of the verification component are completed by the parameters provided by the invention; the correspondingly generated verification platform can directly drive the DUT to start the functional verification simulation without any change; further, the verification engineer can verify the component through the random switch of the configuration of the novel verification platform parameters, the verification platform is flexibly controlled by the novel verification component and the verification IP, so that the UVM verification platform can be automatically, quickly and efficiently built, the original workload of new component integration work is saved by more than 80%, and the verification work efficiency is greatly improved.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
FIG. 2 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
FIG. 4 is a schematic flow diagram of a verification platform automation creation process of one embodiment of the invention.
Fig. 5 is a schematic diagram of an automated verification platform framework according to an embodiment of the invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following explains key terms appearing in the present invention.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The execution subject in fig. 1 may be a verification platform development system based on UVM.
As shown in fig. 1, the method 100 includes:
and step 130, the simulator calls the compiling flow script to complete the compiling and verifying simulation work of the verifying platform.
Optionally, as an embodiment of the present invention, the predefining a new verification component of the verification platform and a verification IP thereof includes:
importing a new verification component and a definition packet of a verification IP thereof and compiling;
interface classes in the instantiation definition package are connected to the design to be tested;
instantiating and transmitting a top layer structure in a definition package;
instantiating a sequence library of new components;
performing coordination synchronization on the sequencers and the sequence library of the new component in all verification environments;
and creating a test case according to the use scene of the design to be tested.
Optionally, as an embodiment of the present invention, the method further includes: predefined integration parameters are stored in a generic template file.
Optionally, as an embodiment of the present invention, the compiling the flow script according to the integration parameter by the code generator includes:
the code generator analyzes the predefined integration parameters to automatically generate a register model and a corresponding functional test sequence, so as to integrate the new components and the verification IP into a verification environment generated by the code generator;
and compiling the flow script of the development method through the register model.
Optionally, as an embodiment of the present invention, instantiating the interface class in the definition package and connecting to the design to be tested includes:
instantiating the interface class in the interface definition packet in a verification environment, and completing the transmission of the interface class;
and finishing the signal connection between the interface class and the design to be tested in the pin list file.
Optionally, as an embodiment of the present invention, the coordinating and synchronizing the sequencers and the sequence library of the new component in all verification environments includes:
performing one-to-one linkage on all the virtual sequencers of the top-level structure and all the verification components and the sub sequencers of the verification IP thereof;
performing one-to-one linking of each sub-sequencer handle in the virtual sequencer and an underlying verification component sequencer entity object;
and performing one-to-one association on all verification components and the sequence library and the top-level sequence of the verification IP.
Optionally, as an embodiment of the present invention, the defining includes: a top-level definition package and an interface definition package.
In order to facilitate understanding of the present invention, the principle of the verification platform development method based on UVM according to the present invention is combined with the process of performing integrated development on the verification platform in the embodiment, so as to further describe the verification platform development method based on UVM according to the present invention.
For a built hierarchical verification platform, if a new verification component and a verification IP are to be extended and integrated, the following factors are generally considered: compiling definition packages for new components and validation IPs; instantiating and connecting a verification IP interface class; randomizing the configuration of the whole verification component; verifying the instantiation of the top layer on a new component, factory registration and the like; instantiating and calling a sequence library of new components; a series of operations such as the coordination and synchronization of the sequencer and the sequence table in all verification environments; for a series of operations, the integration, configuration and calling of a new assembly are realized by extracting and analyzing corresponding key information and by a parameter transmission method, so that the whole verification platform is built quickly and flexibly.
1. The process is predefined. Specifically, the definition process of predefining a new verification component of the verification platform and a verification IP thereof includes:
(1) Importing a verification package: and importing the verification component package and the verification IP package into a verification environment. A verification component package generally comprises a whole verification component top layer package and an interface package, when a package file and an interface file are specified, a verification platform can analyze, compile and link the whole package verification framework from top to bottom, and the connection with other verification components and a to-be-tested design interface is realized through interface types. The present embodiment obtains new components and verifies IP paths through "common _ uvc _ list", and obtains file definitions of verification component framework top layer packets and interface classes through paths specified by "common _ uvc _ pkg" and "common _ uvc _ if", and examples of relevant implementation codes are as follows:
common_uvc_list = /nfs/park/bus1_dir
common_uvc_pkg = bus1_uvm_pkg.sv
common_uvc_if = bus1_uvm_if.sv
(2) Interface transmission: instantiating the interface classes of the verification component and the verification IP on the top layer of the verification environment, and completing the transmission of the interface classes; in the embodiment, the code generator is realized by extracting the simple definition of the embedded program block in the top-level file; an example of relevant implementation code is as follows:
bus1_uvm_if bus1_uvm_if_0();
uvm_config_db#(virtual bus1_uvm_if)::set(uvm_root::get(),”*”,”vif”,bus1_uvm_if_0);
(3) Interface connection: completing the connection of the interface signals and the related signals of the design to be tested in the pin list file so as to realize the driving and the detection of the verification component on the design to be tested; an example of relevant implementation code is as follows:
# DUT input/output UVC interface signal
Bus1_rx bus1_uvm_if_0.tx
Bus1_tx bus1_uvm_if_0.rx
Bus1_enable bus1_uvm_if_0.enable
(4) Top layer definition: for the integration of a new component and a verification IP, a top-level structure (sub _ top) of the verification component needs to be created and instantiated in a top-level environment class (top _ env) according to project requirements, for example, the component environment class (env) is instantiated as a component top-level structure, or an instantiation agent (agent) is instantiated as a component top-level structure, and the creation, instantiation and transfer also need to be completed if a configuration class exists correspondingly; the implementation is completed by a "common _ uvc _ inst" parameter in the embodiment; an example of relevant implementation code is as follows:
common_uvc_inst = bus1_uvm_env
common_uvc_inst = bus1_uvm_config
(5) Sequence bridging 1: the sequence (sequence) of all verification components must complete the transmission of transaction items by mounting in the sequencer (sequence r), so that all verification components and the sub-sequencers of verification IP need to be linked in the virtual sequencer at the top verification level so as to complete the bridging of the bottom-level sequencer, and meanwhile, the connection phase (connect _ phase) at the top verification level needs to make the one-to-one connection of each sub-sequencer handle in the virtual sequencer and the entity object of the bottom-level verification component sequencer; the realization method can be completed by a parameter of 'seqr _ add _ name'; an example of relevant implementation code is as follows:
seqr_add_name = bus1_uvm_sequencer
sequence bridging 2: the sequencer is linked between the top layer and the bottom layer, and all verification components and a sequence library of verification IP need to be associated with a top layer virtual sequence to realize deployment; in the embodiment, base sequences of all components are created into a top-level virtual sequence (top virtual sequence) one by one through a parameter of 'seq _ add _ name', then the docking with a corresponding verification component virtual sequencer is realized, and the sequence randomization is further completed; an example of relevant implementation code is as follows:
seq_add_name = bus1_uvm_base_seq
(6) Top layer driving: in the above, integration and configuration of all verification components and verification IPs are implemented, and we need to create corresponding test cases according to the usage scenarios of the design to be tested to call each verification component sequence and complete excitation transfer through the top-level environment of the verification platform. Since various project verification scenes are varied, the development of test cases and different configuration and calling of verification component sequences are different, and a verifier needs to carefully read a project specification to develop all the test cases;
in this embodiment, since the base sequence (base sequence) of all the bottom components has been instantiated in the top virtual sequence; therefore, for the development of the top-level sequence library, if a verifier wants to redefine the top-level sequence of the corresponding verification function point, the development of the top-level sequence library can be completed only by performing extension (extend) on the top-level basic sequence and then rewriting (overwrite) the basic sequence of different verification component sequences in the creation phase (build _ phase) of the sequence; meanwhile, the developed top-level sequence is required to be integrated and called on a verification platform through a 'top _ seq _ inc' parameter; the same test cases of different test points need to be expanded from a top-level basic test (base _ test), the development of the top-level sequences is the same, and a verifier only needs to integrate and start the corresponding top-level sequences in the test cases through rewriting of the basic test; an example of relevant implementation code is as follows:
top_seq_inc = top_bus1_tx_seq
top_test_inc = top_bus1_tx_test
in addition, in the embodiment, all parameter information implemented for the integration and development of new components and verification IP is defined in a common template file, and a new code generator parses all information one by one, and then automatically generates all contents required by the verification environment. Therefore, the function realization of the original tool is not influenced, the invention can be perfectly compatible, and the compatibility is ensured.
The automatic creation flow of the corresponding verification platform implemented by the method 100 is shown in fig. 4, and a typical verification platform framework generated based on the method is shown in fig. 5.
In fig. 4, the "VIP/UVC parameter instruction" and the "VIP/UVC integrated code segment" in the "input file" column are the parameter input and code segment configuration corresponding to the present embodiment; the third party verification IP/verification component is an imported third party verification module. The "simulation directory", "verification platform top layer", "test case" and "embedded code directory" in the "output file" column are optimized and updated for the original generating module in the present embodiment and new module and code segment generation introduced for implementing the method.
In fig. 5, the top-level verification environment includes two verification components, a "bus1 environment" is a bus verification component generated by an interface template file, a "vip1 environment" is an integrated new (third-party verification) module component, a "monitor" of a vip1 master agent, a "monitor" of a vip1 slave agent, and a vip1 interface communicatively connected to the two, which are original new (third-party verification) sub-component classes. All the sub-configuration classes in the two verification components analyze the relevant configuration parameters through the top-level configuration class to realize the configuration calling of the component classes in the whole verification environment; all the sub-component classes in the bus verification assembly realize configuration through corresponding parameters in the interface template file, and all the sub-component classes in the new (third party verification) module assembly realize configuration through a common template file; wherein all dashed boxes in FIG. 5 indicate that the component class exists but need not be invoked in conjunction with project requirements; all verification components are in butt joint with the interface of the design to be tested through the analysis of the interface parameters; the test case coordinates deployment of each bottom verification component sequence through top-level sequence rewriting, then is distributed to the sub-sequencers of each sub-component through the top-level sequencers, and finally is sent to each component driver.
The "top register model", "reference model", "scoreboard" and "detector" in the top environment of fig. 5 are functional implementations of the issue stage of this embodiment. The part is implemented by the following specific processes: a verifier extracts register information through a register description language based on the description of the relevant contents of a register in a design specification, then automatically generates a register model and a corresponding function test sequence by combining the analysis of corresponding register parameters in a general template file, further realizes the information transmission and comparison among components through the register model, a verification platform reference model and a score board, and finally completes the automation of the detection function of a verification platform.
As shown in fig. 2, the system 200 includes:
a predefining unit 210 configured to predefine a new verification component of the verification platform and a verification IP thereof to obtain an integration parameter;
a script compiling unit 220 configured to compile a flow script according to the integration parameters by the code generator;
and the compiling simulation unit 230 is configured to invoke the compiling flow script by the simulator to complete the compiling and verifying simulation work of the verification platform.
Fig. 3 is a schematic structural diagram of a terminal system 300 according to an embodiment of the present invention, where the terminal system 300 may be configured to execute a verification platform development method based on UVM according to an embodiment of the present invention.
The terminal system 300 may include: a processor 310, a memory 320, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.
The memory 320 may be used for storing instructions executed by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 320, when executed by processor 310, enable terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 320 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 310 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Therefore, the verification environment generated by the invention is automatically generated by the tool all the time, a user does not need to manually modify any generated verification environment, and if a certain node in the verification stage is subjected to project self-reasons (such as the design structure is updated, a design port is changed, the verification structure is changed, and the like) or the tool is updated, the user can generate the verification environment which is completely suitable for the verification requirement of the current stage at any time based on the adjustment of input parameters of the tool. Meanwhile, if a project multiplexing requirement (vertical multiplexing or horizontal multiplexing) exists, a user only needs to import an original input configuration file into a new project, and the flexibility, expandability and reusability of the verification environment are greatly improved. The technical effects achieved by the present embodiment can be referred to the above description, and are not described herein again.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
In the embodiments provided by the present invention, it should be understood that the disclosed system, system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A UVM-based verification platform development method is characterized by comprising the following steps:
predefining a new verification component and a verification IP of the verification platform to obtain an integration parameter;
compiling a flow script by a code generator according to the integrated parameters;
the simulator calls the compiling flow script to complete the compiling and verifying simulation of the verifying platform;
storing predefined integration parameters in a universal template file;
the definition process of predefining the new verification component of the verification platform and the verification IP thereof comprises the following steps:
(1) Importing a verification package: importing a verification component package and a verification IP package into a verification environment;
(2) Interface transmission: instantiating the interface classes of the verification component and the verification IP on the top layer of the verification environment, and completing the transmission of the interface classes;
(3) Interface connection: completing the connection of the interface signals and the related signals of the design to be tested in the pin list file so as to realize the driving and the detection of the verification component on the design to be tested;
(4) Top layer definition: for the integration of a new component and a verification IP, a top-level structure of the verification component is created and instantiated in a top-level environment class according to project requirements;
(5) Sequence bridging 1: the sequence of all verification components completes the transmission of transaction items by being mounted on a sequencer, so that all verification components and verification IP sub-sequencers need to be linked in a virtual sequencer on the verification top layer, the bridging of a bottom-layer sequencer is completed, and meanwhile, the one-to-one butt joint of each sub-sequencer handle in the virtual sequencer and a bottom-layer verification component sequencer entity object needs to be done in the connection stage on the verification top layer;
sequence bridging 2: after the sequencer is linked between the top layer and the bottom layer, all the verification components and the sequence library of the verification IP are associated with the top layer virtual sequence to realize deployment;
(6) Top layer driving: creating a corresponding test case according to a design use scene to be tested to call each verification component sequence and complete excitation transmission through a top environment of a verification platform;
and the verifier extracts the register information through the register description language based on the description of the related contents of the register in the design specification, and then automatically generates a register model and a corresponding function test sequence by combining the analysis of the corresponding register parameters in the general template file.
2. The UVM-based verification platform development method of claim 1, wherein the code generator compiles a flow script according to the integrated parameters, comprising:
the code generator analyzes the predefined integration parameters to automatically generate a register model and a corresponding functional test sequence, so that a new component and a verification IP are integrated into a verification environment generated by the code generator;
and compiling the flow script of the development method through the register model.
3. The UVM-based verification platform development method of claim 1, wherein the defining comprises: a top-level definition package and an interface definition package.
4. A UVM-based verification platform development system, comprising:
the predefined unit is used for configuring a new verification component and a verification IP thereof of the predefined verification platform to obtain an integrated parameter;
the script compiling unit is configured for the code generator to compile the flow script according to the integration parameters;
the compiling simulation unit is configured for calling the compiling flow script by the simulator to finish compiling and verifying simulation work of the verifying platform;
the verification platform development system stores predefined integration parameters in a universal template file;
the definition process of predefining the new verification component of the verification platform and the verification IP thereof comprises the following steps:
(1) Importing a verification package: importing a verification component package and a verification IP package into a verification environment;
(2) Interface transmission: instantiating the interface classes of the verification component and the verification IP on the top layer of the verification environment, and completing the transmission of the interface classes;
(3) Interface connection: completing the connection of the interface signals and the related signals of the design to be tested in the pin list file so as to realize the driving and the detection of the verification component on the design to be tested;
(4) Top layer definition: for the integration of a new component and a verification IP, a top-level structure of the verification component is created and instantiated in a top-level environment class according to project requirements;
(5) Sequence bridging 1: the sequence of all verification components completes the transmission of transaction items by being mounted on a sequencer, so that all verification components and verification IP sub-sequencers need to be linked in a virtual sequencer on the verification top layer, the bridging of a bottom-layer sequencer is completed, and meanwhile, the one-to-one butt joint of each sub-sequencer handle in the virtual sequencer and a bottom-layer verification component sequencer entity object needs to be done in the connection stage on the verification top layer;
sequence bridging 2: after the sequencer is linked between the top layer and the bottom layer, all the verification components and the sequence library of the verification IP are associated with the top layer virtual sequence to realize deployment;
(6) Top layer driving: creating a corresponding test case according to a design use scene to be tested to call each verification component sequence and complete excitation transmission through a verification platform top-level environment;
and the verifier extracts the register information through the register description language based on the description of the related contents of the register in the design specification, and then automatically generates a register model and a corresponding function test sequence by combining the analysis of the corresponding register parameters in the general template file.
5. A terminal, comprising:
a processor;
a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the method of any one of claims 1-3.
6. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-3.
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