CN103152136B - A kind of method using programmable logic device real-time reception multichannel IEC61850-9-2 sampled value - Google Patents
A kind of method using programmable logic device real-time reception multichannel IEC61850-9-2 sampled value Download PDFInfo
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- CN103152136B CN103152136B CN201310074732.0A CN201310074732A CN103152136B CN 103152136 B CN103152136 B CN 103152136B CN 201310074732 A CN201310074732 A CN 201310074732A CN 103152136 B CN103152136 B CN 103152136B
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Abstract
The invention discloses a kind of method using programmable logic device real-time reception multichannel IEC61850-9-2 sampled value, the Ethernet input of every road realizes separately MII interface module to receive the IEC61850-9-2 Ethernet sample values bag of optical fiber input, then the packet received unpacked by MAC module and calculate CRC check value, if check value is correct, decoded packet is together put into FIFO together with receives data packets moment 64 time stamp value, wait for the process of IEC61850-9-2 packet real-time processing module.Simultaneously, in order to accomplish to save CPU Ethernet interface bandwidth and the network storm situation effectively resisted under abnormal conditions, MAC module also can judge whether the packet of current reception is IEC61850-9-2 packet, if not then abandoning immediately, hardware is stopped the impact of network storm for systemic-function.
Description
Technical field
The present invention relates to a kind of method using programmable logic device real-time reception multichannel IEC61850-9-2 sample values, be applicable to the smart machine that the occasions such as electric power digital transformer station, Intelligent transformer station need real-time reception multichannel IEC61850-9-2 sample values.
Background technology
Have high reliability because fiber optic Ethernet transmits, transmission speed is fast, connect up the advantage facilitating cost low, in Intelligent transformer station, fiber optic Ethernet replaces most of cable becomes inevitable.IEC international organization proposes IEC61850-9-2 standard for use fiber optic Ethernet transmission transformer station analog quantity sampled value, and its physical layer uses 100M fiber optic Ethernet interface exactly.
Because the secondary equipment of intelligent converting station such as digital protection or oscillograph generally all will gather multi-analog signal, if the collect and transmit of these analog quantitys will corresponding multichannel 100M fiber optic Ethernet interface input by IEC61850-9-2 standard.Traditional way uses Ethernet switching chip multichannel Ethernet data to be merged into the Ethernet interface then sending into processor in a road in a device, or directly use the processor of band multichannel Ethernet interface.This two schemes has drawback, the first scheme is owing to employing Ethernet switching chip, the uncertainty of every road Ethernet data receive delay will be caused, and the ability resisting network storm also has problem, first scheme accomplishes the isolation of Liao Mei road Ethernet data, but the processor with multichannel Ethernet interface is general all costly and periphery circuit design is complicated, and this scheme also exists and resists the indifferent shortcoming of network storm.
Summary of the invention
The object of the invention is: a kind of method using programmable logic device real-time reception multichannel IEC61850-9-2 sample values is provided, and accomplish to resist the network storm abnormal conditions that may exist in system completely.
Technical solution provided by the invention is: a kind of method using programmable logic device real-time reception multichannel IEC61850-9-2 sampled value, it is characterized in that: the Ethernet input of every road realizes separately MII interface module to receive the IEC61850-9-2 Ethernet sample values bag of optical fiber input, then the packet received unpacked by MAC module and calculate CRC check value, if check value is correct, decoded packet is together put into FIFO together with receives data packets moment 64 time stamp value, wait for the process of IEC61850-9-2 packet real-time processing module.These 64 time stamp value are the real-times in order to realize receiving sample values bag, the count value of 64 bit time counters is specially achieved in FPGA inside, the counting precision of this counter is 20ns, is enough to the needs meeting IEC61850-9-2 packet real-time characteristic.Simultaneously, in order to accomplish to save CPU Ethernet interface bandwidth and the network storm situation effectively resisted under abnormal conditions, MAC module also can judge whether the packet of current reception is IEC61850-9-2 packet, if not then abandoning immediately, hardware is stopped the impact of network storm for systemic-function.
IEC61850-9-2 packet real-time processing module in order poll every road Ethernet receives FIFO, to guarantee that the packet of every circuit-switched data interface can obtain relatively consistent receive delay.Target operation when the time of reception of each packet all beats, CPU obtains the absolute moment of this receives data packets simultaneously when receiving packet, to eliminate the delay and jitter that multichannel data shared network passage brings.
Accompanying drawing explanation
Fig. 1 adopts the mode of Ethernet switching chip to be pooled on the way by multichannel IEC61850-9-2 sample values, then sends the scheme schematic diagram of the ethernet controller of a processor.
Fig. 2 is the scheme schematic diagram adopting the network processing unit with multiple ethernet controller directly to receive multichannel IEC61850-9-2 sample values.
Fig. 3 is the scheme schematic diagram of use programmable logic device real-time reception multichannel IEC61850-9-2 sample values of the invention process.
Fig. 4 is in the scheme of use programmable logic device real-time reception multichannel IEC61850-9-2 sample values of the invention process, the functional block diagram of the inner specific implementation of programmable logic device.
Embodiment
Below in conjunction with accompanying drawing and specific implementation method, the present invention is described in more detail.
As shown in Figure 1 and Figure 2, be in prior art, adopt the mode of Ethernet switching chip to be pooled on the way by multichannel IEC61850-9-2 sample values, then send the scheme schematic diagram (Fig. 1) of the ethernet controller of a processor; With adopt the scheme schematic diagram (Fig. 2) directly receiving multichannel IEC61850-9-2 sample values with the network processing unit of multiple ethernet controller.
The method of use programmable logic device real-time reception multichannel IEC61850-9-2 sample values of the invention process, use scale programmable logic device as FPGA etc., as shown in Figure 3, for Ethernet input in every road realizes separately MII interface module to receive the IEC61850-9-2 Ethernet sample values bag of optical fiber input, then the packet received unpacked by MAC module and calculate CRC check value, if check value is correct, decoded packet is together put into FIFO together with receives data packets moment 64 time stamp value, wait for the process of IEC61850-9-2 packet real-time processing module.These 64 time stamp value are the real-times in order to realize receiving sample values bag, the count value of 64 bit time counters is specially achieved in FPGA inside, the counting precision of this counter is 20ns, is enough to the needs meeting IEC61850-9-2 packet real-time characteristic.Simultaneously, in order to accomplish to save CPU Ethernet interface bandwidth and the network storm situation effectively resisted under abnormal conditions, MAC module also can judge whether the packet of current reception is IEC61850-9-2 packet, if not then abandoning immediately, hardware is stopped the impact of network storm for systemic-function.
Data in order to Shi Mei road IEC61850-9-2 Ethernet interface can both be more real-time send to CPU process, IEC61850-9-2 packet real-time processing module in order poll every road Ethernet receives FIFO, can ensure that the packet of every circuit-switched data interface can obtain relatively consistent receive delay like this.Simultaneously due on hardware for done the time of reception of each packet beat time target operation, so CPU just can obtain the absolute moment of this receives data packets simultaneously when receiving packet, thus eliminate the delay and jitter that multichannel data shared network passage brings, improve the precision characteristic of system.
After IEC61850-9-2 packet real-time processing module obtains the packet and time scale information receiving FIFO, just by the end of time scale information continued access to packet, then together mac controller is given by sending FIFO, change the CRC check value of packet owing to adding the time scale information of 64 to packet, also will be responsible for that CRC check is re-started for transmission packet calculate and the CRC check data bit putting into final data bag so send mac controller.After calculating CRC completes, mac controller is responsible for Ethernet interface final data bag being sent to CPU by MII interface.
Receives data packets FIFO in whole design and Packet Generation FIFO is to solve the inconsistent and stationary problem brought of former and later two data packet lengths.IEC61850-9-2 packet real-time processing module also must monitor the total bandwidth that total interface receives data speed, when the data speed of all data-interfaces is added 80%(i.e. 80Mbps being greater than CPU Ethernet interface data speed) time, will by status register to CPU outputting alarm information, remind CPU network reception overload, likely lost data packets this moment.
In order to obtain the absolute time of the actual reception of packet, signal when will be also system access IRIG-B couple, this time signal can be obtained from gps satellite receiving system by IRIG-B interface.Utilize IRIG-B decoder module to carry out decoding the temporal information obtained is synchronized to 64 time stamp counters, then each reception packet can be stamped the absolute time value received.If dropout or not access during IRIG-B couple, then the time scale information of all packets can only reflect the relative instant of reception and not have the information of absolute time.
Fig. 4 is in the scheme of use programmable logic device real-time reception multichannel IEC61850-9-2 sample values of the invention process, the functional block diagram of the inner specific implementation of programmable logic device.
Although the present invention with preferred embodiment openly as above; but they are not for limiting the present invention; anyly be familiar with this those skilled in the art; without departing from the spirit and scope of the invention; can make various changes or retouch from working as, what therefore protection scope of the present invention should define with the claims of the application is as the criterion.
Claims (6)
1. one kind uses the method for programmable logic device real-time reception multichannel IEC61850-9-2 sampled value, it is characterized in that: the Ethernet input of every road realizes separately MII interface module to receive the IEC61850-9-2 Ethernet sample values bag of optical fiber input, then the packet received unpacked by MAC module and calculate CRC check value, if check value is correct, decoded packet is together put into FIFO together with receives data packets moment 64 time stamp value, wait for the process of IEC61850-9-2 packet real-time processing module; MAC module also can judge whether the packet of current reception is IEC61850-9-2 packet, if not then abandoning immediately; After IEC61850-9-2 packet real-time processing module obtains receiving the packet of FIFO and time scale information, by the end of time scale information continued access to packet, then together mac controller is given by sending FIFO, change the CRC check value of packet owing to increasing the time scale information of 64 to packet, send mac controller and be responsible for that CRC check is re-started for transmission packet and calculate and the CRC check data bit putting into final data bag; After calculating CRC completes, final data bag is sent to the Ethernet interface of CPU by mac controller by MII interface.
2. method according to claim 1, it is characterized in that: described 64 time stamp value are the real-times for realizing receiving sample values bag, the count value of 64 bit time counters is realized in programmable logic device inside, the counting precision of this counter is 20ns, to meet the needs of IEC61850-9-2 packet real-time characteristic.
3. method according to claim 1, is characterized in that: IEC61850-9-2 packet real-time processing module in order poll every road Ethernet receives FIFO, to guarantee that the packet of every circuit-switched data interface can obtain relatively consistent receive delay.
4. method according to claim 3, it is characterized in that: target operation when the time of reception of each packet all beats, CPU obtains the absolute moment of this receives data packets simultaneously when receiving packet, to eliminate the delay and jitter that multichannel data shared network passage brings.
5. according to the method one of Claims 1-4 Suo Shu, it is characterized in that: when the data speed addition of all data-interfaces is greater than 80% of CPU Ethernet interface data speed, by status register to CPU outputting alarm information.
6. according to the method one of Claims 1-4 Suo Shu, it is characterized in that: utilize IRIG-B decoder module to carry out decoding temporal information is synchronized to 64 bit time counters, each reception packet stamps the absolute time value received.
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| CN104426687A (en) * | 2013-08-23 | 2015-03-18 | 南京南瑞继保电气有限公司 | A network storm filtering method applicable for a digital substation secondary device |
| CN103888320A (en) * | 2014-04-14 | 2014-06-25 | 北京四方继保自动化股份有限公司 | Switch device and method for measuring transmission delay through FPGA |
| CN106533975B (en) * | 2016-10-28 | 2019-08-02 | 江苏方天电力技术有限公司 | A kind of sampled value frame decoding implementation method based on gigabit networking |
| CN106612120B (en) * | 2016-12-16 | 2020-03-27 | 北京华航无线电测量研究所 | CRC32 checking method for SAR imaging system |
| CN107579810B (en) * | 2017-07-17 | 2021-06-15 | 中国电力科学研究院 | Electro-optical homology-based frame dispersion receiving and tracing method and system |
| CN108227561A (en) * | 2017-12-08 | 2018-06-29 | 中国航空工业集团公司成都飞机设计研究所 | A kind of markers alignment schemes of multiplicated system data acquisition |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101447122A (en) * | 2008-12-08 | 2009-06-03 | 中国电力科学研究院 | Intelligent device for collecting, transmitting and controlling data of substation |
| CN102004718A (en) * | 2010-11-18 | 2011-04-06 | 中国西电电气股份有限公司 | Merging unit based on field programmable gate array and microprocessor |
| CN201846138U (en) * | 2010-11-17 | 2011-05-25 | 国电南瑞科技股份有限公司 | Breaker intelligent assembly based on unified section data acquisition |
-
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101447122A (en) * | 2008-12-08 | 2009-06-03 | 中国电力科学研究院 | Intelligent device for collecting, transmitting and controlling data of substation |
| CN201846138U (en) * | 2010-11-17 | 2011-05-25 | 国电南瑞科技股份有限公司 | Breaker intelligent assembly based on unified section data acquisition |
| CN102004718A (en) * | 2010-11-18 | 2011-04-06 | 中国西电电气股份有限公司 | Merging unit based on field programmable gate array and microprocessor |
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