CN104038383A - Switch based process level network message analysis method - Google Patents
Switch based process level network message analysis method Download PDFInfo
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Abstract
A switch based process level network message analysis method comprises adding an FPGA (Field Programmable Gate Array) chip to an interface board based on the industrial switch software and hardware used by the existing digital substation; adding the FPGA chip between an external signal interface chip namely a PHY (physical layer) and a switch chip on the interface board and enabling PHY chips to be added to bilateral sides of every channel of the FPGA; enabling message or data to enter into the PHY through RJ45 or an optical port interface during the actual data transmission process and enabling the data to enter into the FPGA chip through an MII (Media Independent Interface); analyzing entered message or data through the FPGA chip, analyzing a message heater of the message and accordingly judging which kind of message the message belongs; performing right and wrong judgment on the message aiming at specific type message. Protection fault action or action rejection and the like can be caused due to conditions that the message during network transmission is wrong and the like, so that monitoring and diagnosing that whether the message transmitted in the network is wrong or not are very important.
Description
Technical field
The invention belongs to communication field in electric power system, the application that exchange data gathers.
Background technology
The network communicating system that a large amount of switching Ethernet and optical cable form in digital transformer substation has substituted traditional secondary stube cable and loop, is all to communicate by the agreement of IEC61850 standard between process layer, wall, substation level.In the networking mode of switch networking, a large amount of SMV sampling message and GOOSE messages transmit by switch, and whether the correctness direct relation of message arrives at a station interior protection equipment can malfunction or tripping.In station, network traffic data is more steady under normal circumstances, there will not be the unexpected growth of flow or die-offs, and may cause the message instantaneous delivery transmitting in switch die-off or suddenly increase when the appearance of merge cells and so on is abnormal, causes defencive function to be affected.
In the transmitting procedure of data, if the message that can transmit switch carries out statistic of classification, thereby can according to statistics, calculate the real-time traffic of all kinds message, when real-time traffic suddenly increases or die-offs, can roughly judge by the type of message is that the cataclysm that fault causes flow has occurred that device.Switch, to the GOOSE of transmission and the differentiation of correcting errors of SMV message, is stored vicious message, and is sent alarm signal by CPU, and prompting personnel overhauls and the searching of fault in time.
Summary of the invention
A kind of process-level network message analysis method based on switch of object of the present invention, be exactly in existing digital transformer substation, do not change on the basis of transformer station's networking mode, by the relevant change in switch soft or hard aspect, realize the statistics of switch to dissimilar message, and the judgement of correcting errors to particular type message, and the error message of diagnosing out is embodied with journal file or alarm mode.
The present invention solves its technical problem and is achieved through the following technical solutions: the process-level network message analysis method based on switch, on the basis of the industrial switch software and hardware using at existing digital transformer substation, the hardware configuration of change interface board increases fpga chip on interface board; On original interface board PHY by MII(Media Independent Interface, comprise a data-interface, and the management interface between MAC and PHY) be connected with exchange chip, now on interface board and the chip of external signal interface be to increase fpga chip between physical layer PHY and exchange chip, each directly connects a PHY chip each paths both sides of described FPGA; In the transmitting procedure of real data, message or data enter PHY by RJ45 or light mouth interface, and then data enter into fpga chip by MII; Now can utilize fpga chip, to the message entering or data analysis, which kind of message the heading of analytic message, be thereby judge this message; For the message of particular type, carry out the judgement of correcting errors of message.For example, for data sampling SMV message, when FPGA extracts the keyword in message, when being 0x88ba, keyword illustrates that this message is the data sampling SMV message receiving, FPGA now counts SMV(type) count value of message increases, subsequently data sampling SMV message is resolved, extract in data sampling SMV message with SmpCnt(Sample Counter) information, and the value of Sample Counter entrained in the value of Sample Counter and former frame data sampling SMV message is compared, whether the sampling message of judging data sampling SMV is continuous.If find that sampled value is discontinuous or data sampling message is wrong, by this message content storage, and the time of reception of message and sample counter information are sent to CPU management.
Realization of the present invention, without do too much change on the basis of existing industrial switch, without increasing dedicated processes fpga chip, has been controlled development cost, has good applicability, and operability can maximize again the utility function of developing switch simultaneously.In whole method, compared to the processing mode of original switch, FPGA is the core devices of realizing this function, by it, realizes the parsing of message and the statistics of type of message.The method realize key technology, its flow process is as follows:
The parsing of message.Owing to existing the real-time exchange of a large amount of messages in switch, CPU management cannot carry out real-time parsing and processing to all messages, and therefore increasing in the present invention FPGA carrys out a large amount of real-time packets that receive in processing and exchanging process.FPGA is by monitoring and analyze the signal on MII interface, in the moment that receives message, the heading of message is resolved, extract keyword wherein, for the different keywords of dissimilar message, each message is carried out to the processing of statistical counting, and statistics is stored in FPGA.
The judgement that special packet is corrected errors.Basic identical with above-mentioned processing procedure: first the 4-bit nibble data transaction receiving to be become to the data of 8-bit, be deposited in message buffer.When message enters behind buffering area, FPGA extracts the keyword in message, when being 0x88ba, keyword illustrates that this message is the data sampling SMV message receiving, resolve subsequently SMV message, extract in SMV message with SmpCnt(Sample Counter) information, and storage (for next frame SMV message in the value of Sample Counter compare).Now, the value of the Sample Counter in the SmpCnt information of the SMV message extracting and former frame SMV message is compared, relatively whether it is continuous.If find, the numerical value of Sample Counter is discontinuous, is judged as error message, and packet storage, in local journal file, and is sent to CPU management by FPGA by time of reception and sample counter information.
(3) access of CPU management to FPGA: CPU management need be regular or irregular by sending on gateway software by the statistics of all kinds message.Now need CPU management access FPGA to obtain ASSOCIATE STATISTICS result.In this programme, CPU management is connected by LOCAL BUS bus with FPGA, and CPU sheet phase selection is closed FPGA, by the memory address of dissimilar statistics, obtains its corresponding statistics.When sheet selects, use three or eight decoders, three address wires and a sheet by CPU select pin to realize the multiplexing of CPU chip selection signal, realize 8 road chip selection signals, connect 8 fpga chips.
FPGA is from loaded with hardware configuration and flush bonding processor software in a serial flash.
Beneficial effect of the present invention is: the invention provides a kind of process-level network message analysis method based on switch, in the process of switch storage forwarding, the dissimilar message that enters switch is carried out to statistic of classification, before and after comparing for SMV sampling message, whether the value of the Sample Counter of message, increase and judge correcting errors of message successively for the serial number in GOOSE message comparison message.The exception messages such as GOOSE message or sampling value message frame format mistake are stored in local journal file according to sequencing, relevant foundation is provided when searching problem.
The present invention be advantageous in that, existing industrial switch tactic pattern is not needed to make too much modification.FPGA is from loaded with hardware configuration and flush bonding processor software in a serial flash.Even equipment is delivered to behind scene in process of production, all can by rewriting flash content, change easily the hardware and software feature of FPGA.Programmable hardware in FPGA and software disposal ability mean that designer can be by integrating required additional functionality as the application program of hardware or software.The ability that just can realize new function by the FPGA that programmes again is simply to the product assurance in future (as supported IEEE1588v2.0), can also be very rapidly the new function of industrial switch and characteristic is and dedicates user to, introduces to the market.
One of principal character of digital transformer substation is exactly that the network communicating system forming with switching Ethernet and optical cable substitutes secondary stube cable and loop in the past.Network message has substituted traditional electric current and voltage in communication.The situations such as the message that transmits in network is wrong all likely cause the malfunction of protection or tripping etc., and therefore in monitoring and diagnostic network, whether message transmission mistake seems particularly important.In the mode with switch networking, all data are all transmitted by switch, can utilize switch to carry out preliminary diagnosis to the message of its transmission, and when the message that transmits in judging switch is wrong, switch sends message abnormal signal.In addition, can utilize switch to carry out the analysis and arrangement of different types of data, calculate the instantaneous delivery of different types of data.
Accompanying drawing explanation
The structured flowchart of Fig. 1 based on FPGA timestamp mark
Embodiment
Below by specific embodiment, the invention will be further described.
Process-level network message analysis method based on switch in transformer station.The method is on the basis of existing digital transformer substation network configuration, processing by switch to the message receiving, the statistics of the message of each type is passed to CPU management by LOCAL BUS bus, CPU calculates the instantaneous delivery of all types of messages, sends alarm signal when instantaneous delivery cataclysm.When switch detects the GOOSE of reception or SMV message, exist when abnormal, exception message is stored in to local file, and sends abnormality alarming.
Enforcement of the present invention comprises the following steps:
(1) enforcement of the present invention comprises the expansion of the inner fpga chip of switch, is provided with FPGA packet parsing and processing module, the processing that sampling message abnormal information is differentiated.
Utilize the basic functional principle of switch storage forwarding, when switch receives Frame, the message that switch is received carries out a preliminary parsing according to its type of message, analyze the message that belongs to which kind of type, frame number to dissimilar message is added up, for the judgement of correcting errors of the message of particular type; The parsing of message: owing to existing the real-time exchange of a large amount of messages in switch, CPU management cannot carry out real-time parsing and processing to all messages, therefore increasing in the present invention FPGA carrys out a large amount of real-time packets that receive in processing and exchanging process.FPGA is by monitoring and analyze the signal in MII excuse, in the moment that receives message, the heading of message is resolved, extract keyword wherein, for the different keywords of dissimilar message, each message is carried out to the processing of statistical counting, and statistics is stored in FPGA.
Utilize FPGA on exchange interface plate to carry out the statistics of the Frame of dissimilar message.
Utilize the FPGA on exchange interface plate, for the judgement of correcting errors of the message of particular type, when finding that this message is wrong, by this packet storage, and error message is informed to CPU, CPU produces alarm signal: FPGA and first the 4-bit nibble data transaction receiving is become to the data of 8-bit, is deposited in message buffer; When message enters behind buffering area, FPGA extracts the keyword in message, when being 0x88ba, keyword illustrates that this message is the data sampling SMV message receiving, resolve subsequently SMV message, extract in SMV message with SmpCnt(Sample Counter) information, and storage (for next frame SMV message in the value of Sample Counter compare).Now, the value of the Sample Counter in the SmpCnt information of the SMV message extracting and former frame SMV message is compared, relatively whether it is continuous.If find, the numerical value of Sample Counter is discontinuous, is judged as error message, and packet storage, in local journal file, and is sent to CPU management by FPGA by time of reception and sample counter information.
The access of CPU management to FPGA: CPU management need be regular or irregular by sending on gateway software by the statistics of all kinds message.Now need CPU management access FPGA packet parsing and processing module to obtain ASSOCIATE STATISTICS result.
In this programme, CPU management is connected by LOCAL BUS bus with FPGA, and CPU sheet phase selection is closed FPGA, by the memory address of statistics dissimilar in FPGA packet parsing and processing module, obtains its corresponding statistics.Between described CPU and FPGA, adopt the mode of LOCAL BUS bus to conduct interviews, respectively there is a PHY chip each paths both sides of described FPGA; On circuit board, comprise a plurality of fpga chips, every fpga chip is connected to four network interfaces of exchange chip by PHY chip BCM5241; Use three or eight decoders, three address wires and a sheet by CPU select pin to realize the multiplexing of CPU chip selection signal, realize 8 road chip selection signals, connect 8 fpga chips.
Described PHY chip model is BCM5241.Described exchange chip model is BCM53262.Respectively there is a PHY chip each paths both sides of FPGA.
On circuit board, comprise a plurality of fpga chips, every fpga chip is connected to four network interfaces of exchange chip by BCM5241.
Synchronous between FPGA: when a plurality of fpga chips of demand carry out the expansion of practical function, relate to synchronous between each fpga chip: each FPGA adopts unified crystal oscillator, and by the I/O mouth of FPGA, each FPGA is linked together, realize the interoperability between FPGA.
Exchange chip model is BCM53262; Described PHY chip model is BCM5241.
(2). whole switch is except original function of exchange module, added FPGA module, make it except realizing switch to different message classification statistical functions, can also be used to expansion and support IEEE1588v2.0 agreement, when expansion IEEE1588 agreement without increasing corresponding hardware module.
Although the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on claims person of defining.
Claims (6)
1. the process-level network message analysis method based on switch, is characterized in that, on the basis of the industrial switch software and hardware that uses at existing digital transformer substation, increasing fpga chip on interface board; On interface board and the chip of external signal interface be to increase fpga chip between physical layer PHY and exchange chip, each directly connects a PHY chip each paths both sides of described FPGA; In the transmitting procedure of real data, message or data enter PHY by RJ45 or light mouth interface, and then data enter into fpga chip by MII; Now utilize fpga chip, to the message entering or data analysis, which kind of message the heading of analytic message, be thereby judge this message; For the message of particular type, carry out the judgement of correcting errors of message.
2. the process-level network message analysis method based on switch according to claim 1, is characterized in that utilizing fpga chip, as follows to the flow process of the message entering or data analysis:
The parsing of message, FPGA is by monitoring and analyze the signal on MII interface, in the moment that receives message, the heading of message is resolved, extract keyword wherein, different keywords for dissimilar message, each message is carried out to the processing of statistical counting, and statistics is stored in FPGA;
The judgement that special packet is corrected errors, first becomes the 4-bit nibble data transaction receiving the data of 8-bit, is deposited in message buffer.When message enters behind buffering area, FPGA extracts the keyword in message, when being 0x88ba, keyword illustrates that this message is the data sampling SMV message receiving, resolve subsequently SMV message, extract in SMV message with SmpCnt(Sample Counter) information, and storage (for next frame SMV message in the value of Sample Counter compare).Now, the value of the Sample Counter in the SmpCnt information of the SMV message extracting and former frame SMV message is compared, relatively whether it is continuous.If find, the numerical value of Sample Counter is discontinuous, is judged as error message, and packet storage, in local journal file, and is sent to CPU management by FPGA by time of reception and sample counter information;
(3) access of CPU management to FPGA: CPU management need be regular or irregular by sending on gateway software by the statistics of all kinds message; Now need CPU management access FPGA to obtain ASSOCIATE STATISTICS result.
3. the process-level network message analysis method based on switch according to claim 1, it is characterized in that CPU management is connected by LOCAL BUS bus with FPGA, CPU sheet phase selection is closed FPGA, by the memory address of dissimilar statistics, obtains its corresponding statistics.When sheet selects, use three or eight decoders, three address wires and a sheet by CPU select pin to realize the multiplexing of CPU chip selection signal, realize 8 road chip selection signals, connect 8 fpga chips.
4. the analytical method of the process-level network message based on switch according to claim 1, it is characterized in that utilizing the FPGA on exchange interface plate, for the judgement of correcting errors of the message of particular type, when finding that this message is wrong, by this packet storage, and error message is informed to CPU, CPU produces alarm signal.
5. the analytical method of the process-level network message based on switch according to claim 1, it is characterized in that utilizing the overall structure that does not change switch, by replacing the interface board of existing switch, realize the variation of switch function, from economic benefit, there is certain feasibility.
6. the analytical method of the process-level network message based on switch according to claim 1, is characterized in that FPGA is from loaded with hardware configuration and flush bonding processor software in a serial flash.
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| CN104579818A (en) * | 2014-12-01 | 2015-04-29 | 国家电网公司 | Detection method of network anomaly message of intelligent substation |
| CN104917705A (en) * | 2015-06-18 | 2015-09-16 | 国家电网公司 | Network message management method of intelligent substation process layer switch |
| CN105515841A (en) * | 2015-11-27 | 2016-04-20 | 浪潮创新科技股份有限公司 | Snmp (Simple Network Management Protocol) information acquisition system based on FPGA (Field Programmable Gata Array) and monitoring method |
| CN107689931A (en) * | 2017-09-27 | 2018-02-13 | 广州海格通信集团股份有限公司 | It is a kind of that Ethernet exchanging function system and method are realized based on domestic FPGA |
| CN110321585A (en) * | 2019-04-09 | 2019-10-11 | 国网山西省电力公司电力科学研究院 | Based on GA-BP neural network switchgear method for detecting insulation defect and system |
| CN110995505A (en) * | 2019-12-19 | 2020-04-10 | 安徽皖通邮电股份有限公司 | Early warning device and method for realizing message error verification by indicator lamp |
| CN111049815A (en) * | 2019-12-05 | 2020-04-21 | 北京天诚同创电气有限公司 | Micro-grid communication system, communication device and control method thereof |
| CN111385135A (en) * | 2018-12-31 | 2020-07-07 | 长沙湘计海盾科技有限公司 | Network switching unit for automatically identifying network environment |
| CN113010465A (en) * | 2021-03-03 | 2021-06-22 | 国网北京市电力公司 | FPGA-based process layer data sampling board card and electronic device |
| CN113114706A (en) * | 2021-06-15 | 2021-07-13 | 南方电网数字电网研究院有限公司 | Multichannel Ethernet message processing method based on power chip |
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| CN104579818A (en) * | 2014-12-01 | 2015-04-29 | 国家电网公司 | Detection method of network anomaly message of intelligent substation |
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| CN111049815A (en) * | 2019-12-05 | 2020-04-21 | 北京天诚同创电气有限公司 | Micro-grid communication system, communication device and control method thereof |
| CN110995505A (en) * | 2019-12-19 | 2020-04-10 | 安徽皖通邮电股份有限公司 | Early warning device and method for realizing message error verification by indicator lamp |
| CN113010465A (en) * | 2021-03-03 | 2021-06-22 | 国网北京市电力公司 | FPGA-based process layer data sampling board card and electronic device |
| CN113114706A (en) * | 2021-06-15 | 2021-07-13 | 南方电网数字电网研究院有限公司 | Multichannel Ethernet message processing method based on power chip |
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Application publication date: 20140910 |