CN102932010A - Highly parallel encoder and method for encoding QC-LDPC (quasi-cyclic low-density parity-check) codes - Google Patents
Highly parallel encoder and method for encoding QC-LDPC (quasi-cyclic low-density parity-check) codes Download PDFInfo
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- CN102932010A CN102932010A CN2012104763563A CN201210476356A CN102932010A CN 102932010 A CN102932010 A CN 102932010A CN 2012104763563 A CN2012104763563 A CN 2012104763563A CN 201210476356 A CN201210476356 A CN 201210476356A CN 102932010 A CN102932010 A CN 102932010A
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Abstract
The invention relates to a solution to highly parallel encoding of the QC-LDPC (quasi-cyclic low-density parity-check) codes. The solution is characterized in that a highly parallel QC-LDPC code encoder of the system mainly comprises four parts including a register, lookup tables, a bc-bit two-input exclusive-or gate and a b-bit two-input exclusive-or gate. The highly parallel QC-LDPC code encoder provided by the invention is compatible with multiple code rates, can fully use the functions of the lookup tables in the FPGA (field programmable gate array) logic resources to reduce the resource demand effectively under the condition of keeping the encoding speed unchanged, and has the advantages of being easy to control, consuming few resources and power, being low in cost, etc.
Description
Technical field
The present invention relates to the communications field, particularly the highly-parallel implementation method of QC-LDPC code coder in a kind of communication system.
Background technology
Because the various distortions that exist in transmission channel and noise can produce transmitted signal and disturb, the situation that digital signal produces error code can appear in receiving terminal inevitably.In order to reduce the error rate, need to adopt channel coding technology.
Low-density checksum (Low-Density Parity-Check, LDPC) code becomes the study hotspot of field of channel coding with its excellent properties that approaches the Shannon limit.Quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.
The SRAA method is to utilize generator matrix G to encode.The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, j(1≤i≤a, the array that 1≤j≤t) consists of, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with the verification vector is high-density matrix.Suppose that b is not prime number, can be broken down into b=ux.Au road highly-parallel SRAA method is finished first encoding needs x+t clock cycle, needs (auc+t) b register, aucb two input and door and aucb two input XOR gate.When adopting FPGA to realize the ultrahigh speed coding, so many resource requirement means that power consumption is large, cost is high.
Summary of the invention
The large shortcoming of resources requirement that exists in the existing implementation for QC-LDPC code ultrahigh speed coding, the invention provides a kind of highly-parallel coding method based on look-up table, take full advantage of the look-up table function in the fpga logic resource, can keep effectively reducing resource requirement under the constant prerequisite of coding rate.
As shown in Figure 1, the highly-parallel encoder of QC-LDPC code mainly is comprised of 4 parts: register, look-up table, bc position two input XOR gate and b position two input XOR gate.Whole cataloged procedure divided for 4 steps finished: in the 1st step, input message vector s is saved to register R
1～R
a, zero clearing register R
A+1～R
tThe 2nd step, register R
1～R
aThe serial u position that moves to left, look-up table L
1～L
aDifference input vector h
1~ h
aWith output vector v
1~ v
a, bc position two input XOR gate B
1～B
A-1To vector v
1~ v
aSummation obtains vector v
A+1, b position two input XOR gate A
l(1≤l≤c) with vector v
A+1L section b bit and register R
A+lThe results added of serial ring shift left u position, and deposit back register R
A+lIn the 3rd step, repeat the 2nd and go on foot x time; The 4th step, parallel output code word (s, p).
The compatible multi code Rate of Chinese character of QC-LDPC highly-parallel encoder provided by the invention can keep effectively reducing resource requirement under the constant prerequisite of coding rate, thereby reach the purpose that reduces hardware cost and power consumption.
Can be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 is the highly-parallel encoder overall structure of QC-LDPC code;
Fig. 2 has compared traditional au road highly-parallel SRAA method and resource consumption of the present invention.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
The QC-LDPC code is the special LDPC code of a class, and its generator matrix G and check matrix H all are the arrays that is made of circular matrix, has segmentation circulation characteristics, therefore be called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of one of lastrow (first trip is footline) ring shift right; From the angle of row, each row of circular matrix all are that previous column (first is terminal column) circulation moves down one result.The set that the row vector of circular matrix consists of is identical with the set of column vector formation, therefore, circular matrix fully can by it first trip or first characterize.The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, j(1≤i≤a, the array that 1≤j≤t) consists of:
G(or H) the capable and b of continuous b row be called as respectively the capable and piece row of piece.The exponent number b that supposes circular matrix is not prime number, can be broken down into b=ux, and wherein, u and x are all non-1 positive integer.So, the front u of all circular matrixes is capable in capable, the rear c piece row of the piece of generator matrix G the m(1≤m≤a) has consisted of a u * bc rank matrix, is referred to as the sub-block row matrix, is denoted as U
mU
mCan be considered by bc u dimensional vector and consist of all U
mConsisted of an au * bc rank sub-block matrix U.
The corresponding code word (s, p) of generator matrix G, that the front a piece row of G are corresponding is information vector s, that rear c piece row are corresponding is verification vector p.Take the b bit as one section, information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a); Verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c).For the segment information of the i(1≤i≤a) vector s
i, s is arranged
i=(s
I, 1, s
I, 2..., s
I, b).
By the characteristics of formula (1), (2) and circular matrix, Fig. 1 has provided the highly-parallel encoder of QC-LDPC code, and it mainly is comprised of register, look-up table, bc position two input XOR gate and b position four kinds of functional modules of two input XOR gate.
Register R
1～R
aBe used for cache information vector s=(s
1, s
2..., s
a), register R
A+1～R
tBe used for calculating and storage verification vector p=(p
1, p
2..., p
c).
Look-up table L
1～L
aThe input of u position and the output of bc position are all arranged, finish respectively different u position information bits and sub-block row matrix U
1~ U
aProduct.The u position information bit s of parallel input
M, un+1, s
M, un+2..., s
M, un+u(1≤m≤a, 0≤n＜x) consist of vectorial h
m={ s
M, un+1, s
M, un+2..., s
M, un+u.Look-up table L
mInput be h
m, each road output is h
mWith sub-block row matrix U
mThe product of respective column, total output has consisted of vector v
mIf the unit of substantially searching of look-up table is considered as one two input and door, need so altogether acb two inputs and door.
Bc position two input XOR gate B
1～B
A-1With vector v
1~ v
aBe added together, obtain vector v
A+1In fact, v
A+1In each element be the vector { h
1, h
2..., h
aWith the product of sub-block matrix U respective column, v
A+1Vector { h
1, h
2..., h
aWith the product of sub-block matrix U.
B position two input XOR gate A
l(1≤l≤c) with vector v
A+1Continuous b bit be added to register R
A+lIn.
Two input XOR gate sums of all bc position two input XOR gate and b position two input XOR gate are acb.
The invention provides a kind of QC-LDPC highly-parallel coding method based on look-up table, in conjunction with the highly-parallel encoder (as shown in Figure 1) of QC-LDPC code, its coding step is described below:
In the 1st step, input message vector s is saved to register R
1～R
a, zero clearing register R
A+1～R
t
The 2nd step, register R
1～R
aThe serial u position that moves to left, look-up table L
1～L
aDifference input vector h
1~ h
aWith output vector v
1~ v
a, bc position two input XOR gate B
1～B
A-1To vector v
1~ v
aSummation obtains vector v
A+1, b position two input XOR gate A
l(1≤l≤c) with vector v
A+1L section b bit and register R
A+lThe results added of serial ring shift left u position, and deposit back register R
A+l
The 3rd step repeated the 2nd and goes on foot x time, after finishing, and register R
1～R
aThat store is information vector s=(s
1, s
2..., s
a), register R
A+1～R
tThat store is verification vector p=(p
1, p
2..., p
c);
The 4th step, parallel output code word (s, p).
Be not difficult to find out from above step, whole cataloged procedure needs x+t clock cycle altogether, and this and traditional au road highly-parallel SRAA method are identical.
Fig. 2 has compared traditional au road highly-parallel SRAA method and resource consumption of the present invention.Note, the unit of substantially searching with look-up table is considered as one two input and door here.Can know from Fig. 2 and to see, compare with au road highly-parallel SRAA method, the present invention used less register, XOR gate and with door, the amount of expending is respectively t/ (auc+t), 1/u and the 1/u of au road highly-parallel SRAA method.
As fully visible, compare with traditional au road highly-parallel SRAA method, the present invention has kept coding rate, can take full advantage of the look-up table function in the fpga logic resource, has that control is simple, resource consumption is few, power consumption is little, low cost and other advantages.
Above-described embodiment is more preferably embodiment of the present invention, and the common variation that those skilled in the art carries out in the technical solution of the present invention scope and replacement all should be included in protection scope of the present invention.
Claims (4)
1. the highly-parallel encoder of a QC-LDPC code, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, jThe array that consists of, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, b is broken down into b=ux, and u and x are all non-1 positive integer, the corresponding code word (s of generator matrix G, p), that the front a piece row of G are corresponding is information vector s, and that rear c piece row are corresponding is verification vector p, take the b bit as one section, information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a), i segment information vector s
i=(s
I, 1, s
I, 2..., s
I, b), verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c), it is characterized in that, described encoder comprises following parts:
Register R
1～R
t, register R
1～R
aBe used for cache information vector s=(s
1, s
2..., s
a), register R
A+1～R
tBe used for calculating and storage verification vector p=(p
1, p
2..., p
c);
Look-up table L
1～L
a, the vectorial h that the input u position information bit that walks abreast respectively consists of
m={ s
M, un+1, s
M, un+2..., s
M, un+u, parallel output bc bit vector v
m, wherein, 1≤m≤a, 0≤n＜x;
Bc position two input XOR gate B
1～B
A-1, with vector v
1~ v
aBe added together, obtain vector v
A+1
B position two input XOR gate A
1～A
c, A
lWith vector v
A+1The continuous b bit of l section be added to register R
A+lIn, wherein, 1≤l≤c.
2. highly-parallel encoder as claimed in claim 1 is characterized in that, described look-up table L
1～L
aFinish respectively different u position information bits and sub-block row matrix U
1~ U
aProduct, look-up table L
mInput be h
m, each road output is h
mWith sub-block row matrix U
mThe product of respective column, total output has consisted of vector v
m
3. highly-parallel encoder as claimed in claim 1 is characterized in that, described vector v
A+1In each element be the vector { h
1, h
2..., h
aWith the product of sub-block matrix U respective column, v
A+1Vector { h
1, h
2..., h
aWith the product of sub-block matrix U.
4. the highly-parallel coding method of a QC-LDPC code, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, jThe array that consists of, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, b is broken down into b=ux, and u and x are all non-1 positive integer, the corresponding code word (s of generator matrix G, p), that the front a piece row of G are corresponding is information vector s, and that rear c piece row are corresponding is verification vector p, take the b bit as one section, information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a), i segment information vector s
i=(s
I, 1, s
I, 2..., s
I, b), verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c), it is characterized in that, described coding method may further comprise the steps:
In the 1st step, input message vector s is saved to register R
1～R
a, zero clearing register R
A+1～R
t
The 2nd step, register R
1～R
aThe serial u position that moves to left, look-up table L
1～L
aDifference input vector h
1~ h
aWith output vector v
1~ v
a, bc position two input XOR gate B
1～R
A-1To vector v
1~ v
aSummation obtains vector v
A+1, b position two input XOR gate A
lWith vector v
A+1L section b bit and register R
A+lThe results added of serial ring shift left u position, and deposit back register R
A+l, wherein, 1≤l≤c;
The 3rd step repeated the 2nd and goes on foot x time, after finishing, and register R
1～R
aThat store is information vector s=(s
1, s
2..., s
a), register R
A+1～R
tThat store is verification vector p=(p
1, p
2..., p
c);
The 4th step, parallel output code word (s, p).
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6141788A (en) * | 1998-03-13 | 2000-10-31 | Lucent Technologies Inc. | Method and apparatus for forward error correction in packet networks |
| CN1717871A (en) * | 2002-10-05 | 2006-01-04 | 数字方敦股份有限公司 | Systematic encoding and decoding of chain reaction codes |
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2012
- 2012-11-21 CN CN201210476356.3A patent/CN102932010B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6141788A (en) * | 1998-03-13 | 2000-10-31 | Lucent Technologies Inc. | Method and apparatus for forward error correction in packet networks |
| CN1717871A (en) * | 2002-10-05 | 2006-01-04 | 数字方敦股份有限公司 | Systematic encoding and decoding of chain reaction codes |
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