CN102930094A - High-precision clock chip territory structure with temperature compensation function - Google Patents
High-precision clock chip territory structure with temperature compensation function Download PDFInfo
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- CN102930094A CN102930094A CN2012104119542A CN201210411954A CN102930094A CN 102930094 A CN102930094 A CN 102930094A CN 2012104119542 A CN2012104119542 A CN 2012104119542A CN 201210411954 A CN201210411954 A CN 201210411954A CN 102930094 A CN102930094 A CN 102930094A
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Abstract
The invention discloses a high-precision clock chip territory structure with a temperature compensation function. A basic rule is that a sensitive analog module which has a small signal and is easy to interfere gets away from a high-frequency digital module as much as possible; and the sensitive analog module and the high-frequency digital module are isolated by a high-amplitude analog module (such as a buffer and a comparator) and a low-speed digital module. The territory comprises a first territory region, a second territory region, a third territory region, a fourth territory region, a fifth territory region, a sixth territory region and a seventh territory region; the seventh territory is distributed around a clock chip territory, and other territories are arranged in the center of the chip; the first territory supplies a reference source to other territory regions; the second territory region is connected with the third territory region; the third territory region is connected with the sixth territory region; the sixth territory region is connected with the fourth territory region; and the fourth territory region is connected with the fifth territory region. According to the high-precision clock chip territory structure with the temperature compensation function, the sub territories are fixedly arranged, and the positions are rational in arrangement; and moreover, a power ground factor, a matching factory, a shielding factor and an interconnection factor are comprehensively considered, so that the influence of noise of a digital circuit switch on an analog circuit is reduced to the maximum extent, and the design success rate of the high-precision clock chip territory structure with the temperature compensation function is guaranteed.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, particularly a kind of high precision clock chip layout structure with temperature compensation
Background technology
At present band temperature compensation high precision clock chip has that high precision frequency stability, volume are little, low in energy consumption, high reliability, be widely used in the various electronic products, such as intelligent grid, radio communication base station, based on core and edge router, IP clock and the instrument etc. of SONET and synchronous ethernet.
Mainly be comprised of RTC (real time clock) and temperature compensating crystal oscillator and non-loss storer EEPROM with the high precision clock chip of temperature compensation, wherein RTC is digital circuit, and temperature compensating crystal oscillator is mimic channel.In general analog IC will be much larger than digital IC to the susceptibility of noise.For Digital Analog Hybrid Circuits, how carrying out that rational laying out pattern impacts the performance of analog IC with the noise of avoiding digital IC is the problem that the IC deviser must think over.Therefore be necessary to propose a kind of rational band temperature compensation high precision clock chip layout design proposal.
Summary of the invention
Cause clock chip performance problem not up to standard for solving owing to laying out pattern is unreasonable, the invention provides a kind of novel high precision clock chip layout structure with temperature compensation.Its cardinal rule be small-signal, the sensitive analog module that easily is disturbed as far as possible away from the high-frequency digital module, and the analog module of long arc (such as buffer and comparer) and low-speed digital module done isolation between them.This domain has comprised first published map-area, second edition map-area, third edition map-area, the 4th domain district, the 5th domain district, sixth version map-area, the 7th domain district.The 7th domain be distributed in the clock chip domain around, other domain district is all in chip central authorities.The first published map-area provides reference power source for other domain district.The second edition map-area links to each other with third edition map-area, and third edition map-area links to each other with the sixth version map-area, and the sixth version map-area links to each other with the 4th domain district, and the 4th domain district links to each other with the 5th domain district.Each sub-laying out pattern of the high precision clock chip of this novel practical band temperature compensation is fixed, location layout is reasonable, and power supply ground, coupling, shielding and interconnection factor have been considered, at utmost reduce the impact of digital circuit switch noise on mimic channel, guaranteed the power that is designed to the high precision clock chip of temperature compensation.
Description of drawings
Fig. 1 is the high precision clock chip layout structural drawing with temperature compensation
Embodiment
Research finds that the domain structure of the temperature compensating crystal oscillator (mimic channel) in the clock chip directly determines the degree of accuracy of output clock, thereby determines the performance of whole clock chip.Layout between temperature compensating crystal oscillator and digital RTC part and the EEPROM also can have influence on the performance of clock chip in addition.Therefore need careful layout with the optimization chip performance.
The first published map-area is benchmark domain district, and it provides reference current source and voltage source for whole chip.The second edition map-area is temperature measurement circuit, and its Output rusults is delivered to ADC and carried out analog to digital conversion, so it is adjacent with third edition map-area (adc circuit).Temperature measurement circuit domain district is comprised of a plurality of CMOS transistors and bipolar transistor and resistance capacitance.The megacryst pipe all adopts the homocentric layout that the four directions intersects to improve the device matching degree, and bipolar transistor also adopts becket to improve ghost effect and current carrying capacity around transistor technology.The analog to digital conversion result of third edition map-area is sent to sixth version map-area (EEPROM) and controls eeprom circuit offset is sent to the 4th domain district (DTCXO), so these three domain districts are adjacent.The 4th domain district is the crystal oscillator part, and its output frequency stability directly affects the performance of whole chip.For fear of the interference between crystal oscillator and the digital RTC part, crystal oscillator part and digital RTC partly are placed on respectively the upper right corner and the lower left corner of domain.Crystal oscillator is comprised of oscillator core circuit and load capacitance array, and wherein the tunable load capacitor array adopts the full symmetric structure.Whole crystal oscillator domain is isolated by dark N trap isolation strip.The 5th domain district is the digital circuit part, adopts center clock backbone method that clock network is connected up.The 7th domain district is IO interface domain district, comprises 12 parallel IO interface domains, they be evenly distributed in clock chip around, each PAD domain district for electric forming power ring, puncture preventing, thereby realize electrostatic discharge protection.
Each sub-laying out pattern of the high precision clock chip of this novel practical band temperature compensation is fixed, location layout is reasonable, and power supply ground, coupling, shielding and interconnection factor have been considered, reduce to the full extent the impact of digital circuit switch noise on mimic channel, guaranteed the power that is designed to the high precision clock chip of temperature compensation.
Technology contents of the present invention and technical characterictic disclose as above, but those of ordinary skill in the art may do change and the modification that does not deviate from spirit of the present invention based on the present invention.Therefore the present invention will can not be limited to these embodiment shown in this article, but will meet consistent with principle disclosed herein and features of novelty wide region.
Claims (8)
1. with the high precision clock chip layout structure of temperature compensation, it is characterized in that: described high precision clock chip layout with temperature compensation is by the first published map-area, the second edition map-area, third edition map-area, the 4th domain district, the 5th domain district, the sixth version map-area, the 7th domain district forms, wherein the 7th domain be distributed in the clock chip domain around, other domain district is all in chip central authorities, the first published map-area provides reference power source for other domain district, the second edition map-area links to each other with third edition map-area, third edition map-area links to each other with the sixth version map-area, the sixth version map-area links to each other with the 4th domain district, the 4th domain district links to each other with the 5th domain district, each sub-laying out pattern of the high precision clock chip of this novel practical band temperature compensation is fixed, location layout is reasonable, and considered power supply ground, coupling, shielding and interconnection factor, at utmost reduce the impact of digital circuit switch noise on mimic channel, guaranteed the power that is designed to the high precision clock chip of temperature compensation.
2. band temperature compensation high precision clock chip layout structure as claimed in claim 1 is characterized in that, described first published map-area is benchmark domain district, specifically comprises voltage reference domain and current reference domain.
3. band temperature compensation high precision clock chip layout structure as claimed in claim 1 is characterized in that, described the second domain is temperature detection domain district.Described temperature detection domain district is comprised of a plurality of CMOS transistors and bipolar transistor and resistance capacitance, the megacryst pipe all adopts the homocentric layout that the four directions intersects to improve the device matching degree, also adopts becket to improve ghost effect and the current carrying capacity of bipolar transistor around transistor technology.
4. band temperature compensation high precision clock chip layout structure as claimed in claim 1, it is characterized in that, described third edition map-area is digital-to-analog conversion (Analog-to-Digital Converter, ADC) domain district, and dark N trap isolation strip is arranged around the described digital-to-analog conversion domain district.
5. band temperature compensation high precision clock chip layout structure as claimed in claim 1 is characterized in that, described the 4th domain district is crystal oscillator.Described domain district is comprised of oscillator core circuit and load capacitance array, and wherein the tunable load capacitor array adopts the full symmetric structure, is furnished with dark N trap isolation strip around the described crystal oscillator domain.
6. band temperature compensation high precision clock chip layout structure as claimed in claim 1 is characterized in that, described the 5th domain district is real time clock circuit domain district, and this digital circuit domain adopts center clock backbone method that clock network is connected up.
7. band temperature compensation high precision clock chip layout structure as claimed in claim 1 is characterized in that, described sixth version map-area is electricallyerasable ROM (EEROM) (Electric Erase Read only ROM, EEPROM) domain district.
8. band temperature compensation high precision clock chip layout structure as claimed in claim 1 is characterized in that, described the 7th domain district is IO interface domain district.
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| CN2012104119542A CN102930094A (en) | 2012-10-25 | 2012-10-25 | High-precision clock chip territory structure with temperature compensation function |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104485330A (en) * | 2014-11-18 | 2015-04-01 | 北京七芯中创科技有限公司 | Layout structure of high-precision temperature-measuring chip with ultra-high ESD (Electronic Static Discharge) circuit |
| CN106777437A (en) * | 2015-11-24 | 2017-05-31 | 龙芯中科技术有限公司 | The building method of clock system, device and clock system |
| CN106953631A (en) * | 2016-01-06 | 2017-07-14 | 精工爱普生株式会社 | Circuit arrangement, oscillator, electronic equipment and moving body |
| CN107017839A (en) * | 2015-11-12 | 2017-08-04 | 精工爱普生株式会社 | Circuit arrangement, oscillator, electronic equipment and moving body |
| CN110263499A (en) * | 2019-07-24 | 2019-09-20 | 北京智芯微电子科技有限公司 | A kind of domain structure and radio frequency tag chip of high sensitivity large capacity radio frequency tag chip |
| CN112115672A (en) * | 2020-09-15 | 2020-12-22 | 中国兵器工业集团第二一四研究所苏州研发中心 | Layout structure of high-voltage multiplexer chip |
| CN116629186A (en) * | 2023-05-23 | 2023-08-22 | 广东匠芯创科技有限公司 | Layout design method and layout structure of two-stage fully differential operational amplifier |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104485330A (en) * | 2014-11-18 | 2015-04-01 | 北京七芯中创科技有限公司 | Layout structure of high-precision temperature-measuring chip with ultra-high ESD (Electronic Static Discharge) circuit |
| CN107017839A (en) * | 2015-11-12 | 2017-08-04 | 精工爱普生株式会社 | Circuit arrangement, oscillator, electronic equipment and moving body |
| CN106777437A (en) * | 2015-11-24 | 2017-05-31 | 龙芯中科技术有限公司 | The building method of clock system, device and clock system |
| CN106777437B (en) * | 2015-11-24 | 2020-05-19 | 龙芯中科技术有限公司 | Clock system construction method and device and clock system |
| CN106953631A (en) * | 2016-01-06 | 2017-07-14 | 精工爱普生株式会社 | Circuit arrangement, oscillator, electronic equipment and moving body |
| CN106953631B (en) * | 2016-01-06 | 2022-03-22 | 精工爱普生株式会社 | Circuit device, oscillator, electronic apparatus, and moving object |
| CN110263499A (en) * | 2019-07-24 | 2019-09-20 | 北京智芯微电子科技有限公司 | A kind of domain structure and radio frequency tag chip of high sensitivity large capacity radio frequency tag chip |
| CN110263499B (en) * | 2019-07-24 | 2024-03-05 | 北京智芯微电子科技有限公司 | Layout structure of radio frequency tag chip and radio frequency tag chip |
| CN112115672A (en) * | 2020-09-15 | 2020-12-22 | 中国兵器工业集团第二一四研究所苏州研发中心 | Layout structure of high-voltage multiplexer chip |
| CN112115672B (en) * | 2020-09-15 | 2024-01-26 | 中国兵器工业集团第二一四研究所苏州研发中心 | Layout structure of high-voltage multiplexer chip |
| CN116629186A (en) * | 2023-05-23 | 2023-08-22 | 广东匠芯创科技有限公司 | Layout design method and layout structure of two-stage fully differential operational amplifier |
| CN116629186B (en) * | 2023-05-23 | 2024-02-06 | 广东匠芯创科技有限公司 | Layout design method and layout structure of two-stage fully differential operational amplifier |
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Address after: Room 5, building 98, No. 102300 West Lake Road, Mentougou District, Beijing, China Applicant after: Beijing 7Q Technology Co., Ltd. Address before: 100029, A, block 69, mount, No. 202, Beichen West Road, Beijing, Chaoyang District Applicant before: Beijing 7Q Technology Co., Ltd. |
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Application publication date: 20130213 |