CN102929820A - SPI communication device compatible with single/dual wires and communication method thereof - Google Patents
SPI communication device compatible with single/dual wires and communication method thereof Download PDFInfo
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- CN102929820A CN102929820A CN2011104544843A CN201110454484A CN102929820A CN 102929820 A CN102929820 A CN 102929820A CN 2011104544843 A CN2011104544843 A CN 2011104544843A CN 201110454484 A CN201110454484 A CN 201110454484A CN 102929820 A CN102929820 A CN 102929820A
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Abstract
The invention discloses an SPI communication device compatible with single/dual wires and a communication method thereof. The communication device comprises a host machine, a plurality of slave machines and an SPI bus, wherein the slave machines communicate with the host machine through the SPI bus, and the device is characterized in that a programmable logic processing unit is further connected between the slave machines and the SPI bus, the host machine is connected with the gating end of the programmable logic processing unit through a chip selection signal wire; and the host machine is controlled to be connected with the slave machines through a programmable controller, and the required slave machines communicate with the host machine according to different chip selection logics. According to the invention, complete compatibility of an SPI interface hardware with single/dual wires can be achieved, and one host machine can be in gating connection with the plurality of slave machines through the programmable logic processing unit.
Description
Technical field
The present invention relates to the communications field, in particular a kind of SPI communicator and communication means thereof of single/double wire compatible.
Background technology
More and more detailed along with the develop rapidly of communication industry and the division of labor in society, the manufacturing of communication apparatus more and more presents modular trend, communication module is a more wide in range concept, be to have the parts that the ﹑ of a certain or several standalone features is comprised of one or more components and parts in the communication apparatus (device), use at present more have Subscriber Interface Module SIM (hereinafter to be referred as line module) and TIM trunk interface module (hereinafter to be referred as trunk module).
User interface parameters (as: two wires port Impedance AD, the gain of DA twocouese level point; Feed voltage, electric current; Ringing frequency, voltage, electric current; Metering pulse; Dislodging machine testing threshold value; Caller identification signal level etc.) and trunk interface parameter (as: simulated impedance and analog gain etc.) all can adjust and arrange by the SPI interface, serial peripheral equipment interface SPI allows to carry out between main frame (the SPI interface that generally has standard) and the slave (communication module) synchronous data transmission of high speed.The demand of this communication module amount with programmable functions is increasing, the requirement of matter is more and more higher, user and the producer are more and more, the definition of module and pin position also more and more " standardization " (this standardization is that more convenient user has how better selection for the benign competition between convenient different manufacturing firms.They mutually promote and affect, jointly be devoted to industry healthy development and form gradually), the pin that an outstanding problem that in use runs into is line module and trunk module is compatible, but the mode of SPI communication is inconsistent, a kind of be Application standard the SPI interface (as shown in Figure 1, hereinafter to be referred as two-wire SPI), standard SPI interface uses 4 signal line and host interface, be respectively: (the SPI slave is selected pin, Low level effective), SCK (the serial clock of spi bus, sent by main frame, no matter be to send data or receive data all will produce for main frame), MOSI (main frame output/slave the input signal of spi bus, to the MOSI of slave hereinafter to be referred as DI), MISO (the main frame input/slave output signal of spi bus, to the MISO of slave hereinafter to be referred as DO).
Another kind is to use off-gauge SPI interface (as shown in Figure 2, hereinafter to be referred as single line SPI), off-gauge SPI uses 3 signal line and host interface, transmit-receive sharing one signal line DI/0 (transmit-receive sharing pin, when main frame sends data, data are inputted from the DI/0 mouth of slave through resistance 1 from the MOSI mouth output of main frame, when host receiving data, data are inputted from the MISO mouth of main frame through resistance 2 from the DI/0 mouth output of slave), DI/O takies the pin position of DI in the standard SPI interface, and the DO pin is unsettled in slave inside.
SPI interface for the compatible with single two-wire, general way is at the DI(of slave single line SPI to be DI/O) and the MISO mouth of main frame between reserve resistance 3, when slave is two-wire SPI interface, remove resistance 3, when slave is single line SPI interface, increase resistance 3(as shown in Figure 3).When main frame sends data, drag down communication process of host-initiated by the pin with the slave of needs.The data that main frame and slave will need to send are put into corresponding shift register.Main frame produces time clock with swap data at the SCK pin, there is not any problem at slave in this scheme when being single, and has successful case, and detailed process is when the SPI two-wire is used, the data of main frame shift out from the MOSI of main frame, move into through the DI mouth of resistance 1 from slave; The data of slave shift out from the DO of slave, move into from the MISO of main frame through resistance 2, main frame by drawing high of slave realized with slave synchronously.When single line SPI used, the data of main frame shifted out from the MOSI of main frame, moved into through the DI/O mouth of resistance 1 from slave, because DI/O connects the MISO of main frames through resistance 3, MISO is input pin, so DI/O place data are not exerted an influence.The data of slave shift out from the DI/O of slave, MISO from main frame moves into through resistance 3, because this moment, DI/O also linked to each other with MOSI through resistance 1, MOSI is that output pin can exert an influence to DI/O, therefore when read operation, the MOSI pin to be set to input pin, when write operation, again MOSI be set to output pin.
When a plurality of slave is arranged, because want a plurality of slaves in parallel on spi bus, the one, increased the quantity of chip selection signal, I/O (I/O port of main frame) mouthful of resource that need to take main frame is more; The 2nd, a plurality of slaves of spi bus demand motive, driving force might be not; The 3rd, owing to there is the phase mutual interference in a plurality of slaves in parallel, particularly the parallel connection of a plurality of resistance 3 may increase this interference when single line is used on the transceiving data line of main frame; The 4th, add resistance value magnitude relationship to the resistance matching problem of signal transmission, also affect the speed of data transmission simultaneously, select improper meeting that characteristics of signals is exerted an influence; The 5th, need to change hardware for different slaves, be unfavorable for producing.
Therefore, prior art has yet to be improved and developed.
Summary of the invention
The technical problem to be solved in the present invention is, defects for prior art, a kind of SPI communicator and communication means thereof of single/double wire compatible are provided, it can realize that single two-wire SPI interface hardware can be fully compatible, and can realize that a main frame connects a plurality of slaves by FPGA (Field Programmable Gate Array) processing unit gating.
The technical scheme that technical solution problem of the present invention adopts is as follows:
A kind of SPI communicator of single/double wire compatible, comprise main frame, a plurality of slave and spi bus, described slave communicates by described spi bus and described main frame, wherein, also be connected a FPGA (Field Programmable Gate Array) processing unit between described slave and the described spi bus, described main frame also selects signal wire to link to each other with the gating end of described FPGA (Field Programmable Gate Array) processing unit by a slice;
Described main frame is controlled with described slave by described Programmable Logic Controller and is connected, and communicates according to slave and the described main frame of different chip selection logics with needs.
The SPI communicator of described single/double wire compatible, wherein, described FPGA (Field Programmable Gate Array) processing unit is a CPLD.
The SPI communicator of described single/double wire compatible, wherein, the I/O mouth of main frame is deciphered by CPLD and is produced the sheet choosing.
The SPI communicator of described single/double wire compatible, wherein, when described slave was 8, described spi bus comprised:
Main frame output/slave input signal cable the MOSI that is used for transmission main frame output data;
Main frame input/slave output signal line the MISO that is used for transmission main frame input data;
The first clock cable SCK1;
Be used for transmission and write the SPI write signal line of indicator signal SPI_WR;
Be used for transmission and read the SPI reading signal lines of indicator signal SPI_RD;
SPI type line SPI_TYPE is used for corresponding to two-wire SPI when SPI_TYPE is 1, corresponds to single line SPI when SPI_TYPE is 0.
The SPI communicator of described single/double wire compatible, wherein, described chip selection signal line is 4,4 I/O confessions that connect respectively CPLD produce 8 chip selection signals:
Comprise in described 4 I/O mouths that three sheet selected control donsoles and one enable the control mouth and is respectively an I/ O mouth I/O[1], the 2nd I/ O mouth I/O[2], the 3rd I/ O mouth I/O[3], the 4th I/ O mouth I/O[4].
The SPI communicator of described single/double wire compatible, wherein, a slice that the SPI slave of each slave selects pin to be connected to CPLD is selected logic output terminal, and when being 8 slaves, CPLD provides 8 chip selection logics.
The SPI communicator of described single/double wire compatible, wherein, described main frame is CPU.
A kind of communication means of SPI communicator of as mentioned above single/double wire compatible wherein, comprises step:
When slave was two-wire SPI, CPLD linked to each other the main frame output/slave input signal cable MOSI of main frame with the data input pin DI of slave, and the data output end DO of slave is linked to each other with the main frame input/slave output signal line MISO of main frame; When main frame sends data, select one road slave by CPLD, then the data of main frame are from the main frame output/slave input signal cable MOSI output of main frame, through the data-in port DI input of CPLD from slave; During host receiving data, also to select one road slave, the data of slave are exported from the data output end DO of slave, and process CPLD is from the main frame input/slave output signal line MISO input of main frame, and main frame is by selecting pin to draw high the synchronous of realization and slave the SPI slave of slave:
Operation when slave is single line SPI is controlled by a write command signal and and reads indicator signal, link to each other with the main frame input/slave output signal line MISO of main frame when reading the input/output terminal DI/O with slave of CPLD when effective, when with effect, CPLD links to each other the main frame output/slave input signal cable MOSI of main frame with the input/output terminal DI/O of slave; When main frame sends data, select one road slave juxtaposition with effect by CPLD, then the data of main frame are from the main frame output/slave input signal cable MOSI output of main frame, through the input/output terminal DI/O input of CPLD from slave; During host receiving data, at first to select one road slave juxtaposition to read effectively, then the data of slave shift out from the input/output terminal DI/O of slave, process CPLD moves into from the main frame input/slave output signal line MISO of main frame, and main frame is by selecting pin to draw high the synchronous of realization and slave the SPI slave of slave.
The communication means of the SPI communicator of described single/double wire compatible, wherein, it also comprises step:
Process steps is write in two-wire SPI communication: main frame is selected one road slave to open the sheet choosing by CPLD to enable, write order and address and check whether to write by the judgement symbol position and finish, if finish then data writing, check by the judgement symbol position whether data writing is finished, whole SPI writes the process end if finish then, proceeds next operation;
Two-wire SPI communication read procedure step: main frame is selected one road slave to open the sheet choosing by CPLD to enable, write order and address and check whether to write by the judgement symbol position and finish, finish a blank operation generation clock that then continues to write among the SPI if write, wait for that described blank operation writes and finish, then from the SPI reception buffer, read the data that receive if finish, whole SPI read procedure finishes, and continues and carries out next one operation;
Process steps is write in single line SPI communication: main frame is selected one road slave to open the sheet choosing by CPLD to enable, put to write order and address and check whether to write by the judgement symbol position with effect and finish, then put with the effect data writing if finish, check by the judgement symbol position whether data writing is finished, whole SPI writes the process end if finish then, proceeds next operation;
Single line SPI communication read procedure step: main frame is selected one road slave to open the sheet choosing by CPLD to enable, put to write order and address and check whether to write by the judgement symbol position with effect and finish, if write to finish and then put a blank operation generation clock of reading effectively to write among the SPI, wait for that described blank operation writes and finish, if finish then and can from the SPI reception buffer, read the data that receive, whole SPI read procedure finishes, and proceeds next operation.
SPI communicator and the communication means thereof of single/double wire compatible provided by the present invention, it can be realized that single two-wire SPI interface hardware can be fully compatible, and have following advantage by a FPGA (Field Programmable Gate Array) processing unit:
1: single two-wire SPI interface hardware is compatibility fully, only needs to revise the CPLD firmware and gets final product, and it is flexible, convenient that interface is selected.
The driving force of the bus of 2:SPI can be adjusted by CPLD, and this facilitates for the expansion of slave.
3: the I/O mouth of main frame is deciphered the mode that produces the sheet choosing by CPLD saved the I/O mouth of main frame, and increased the SPI enable bit, guarantee when operating without SPI, to close all SPI sheet choosings.
4: when single line is used MOSI and MISO are isolated fully, under the different read-write modes DI/O linked to each other from different pin and avoided the interference that may exist each other.
Description of drawings
Fig. 1 is the master-slave communication mechanism synoptic diagram of two-wire SPI in the prior art.
Fig. 2 is the master-slave communication mechanism synoptic diagram of single line SPI in the prior art.
Fig. 3 is SPI single/double wire compatible scenario-frame synoptic diagram traditional in the prior art.
Fig. 4 is the SPI communication apparatus structure synoptic diagram of the single/double wire compatible of the embodiment of the invention.
Fig. 5 is that the two-wire SPI of the embodiment of the invention writes process flow diagram flow chart.
Fig. 6 is the two-wire line SPI reading data course process flow diagram of the embodiment of the invention.
Fig. 7 is that the single line SPI of the embodiment of the invention writes the data procedures process flow diagram.
Fig. 8 is the single line SPI reading data course process flow diagram of the embodiment of the invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, clear and definite, developing simultaneously referring to accompanying drawing, the present invention is described in more detail for embodiment.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
The SPI communicator of a kind of single/double wire compatible that the embodiment of the invention provides, comprise main frame, a plurality of slave (slave 1 as shown in Figure 4 is to slave 8) and spi bus 101, described slave communicates with described main frame by described spi bus 101, also be connected a FPGA (Field Programmable Gate Array) processing unit between described slave and the described spi bus, described main frame also selects signal wire 102 to link to each other with the gating end of described FPGA (Field Programmable Gate Array) processing unit by a slice;
Described main frame is controlled with described slave by described Programmable Logic Controller and is connected, and communicates according to slave and the described main frame of different chip selection logics with needs.
Preferably, adopting described FPGA (Field Programmable Gate Array) processing unit is a CPLD((Complex Programmable Logic Device) CPLD).
Below will the SPI communicator of single/double wire compatible shown in Figure 4 be elaborated, as shown in Figure 4, between main frame and slave, increase CPLD(FPGA (Field Programmable Gate Array) processing unit), by CPLD (Complex Programmable Logic Device) FPGA (Field Programmable Gate Array) processing unit the SPI interface is adjusted, to adapt to the SPI interface of single two-wire, below describe as an example of 8 road interfaces example, main frame described in the present embodiment is CPU.
As shown in Figure 4, when described slave was 8, described spi bus 101 comprised:
Main frame output/slave input signal cable the MOSI that is used for transmission main frame output data;
Main frame input/slave output signal line the MISO that is used for transmission main frame input data;
Clock cable SCK(i.e. the first clock cable SCK1);
Be used for transmission and write the SPI write signal line of indicator signal SPI_WR;
Be used for transmission and read the SPI reading signal lines of indicator signal SPI_RD;
SPI type line SPI_TYPE is used for corresponding to two-wire SPI when SPI_TYPE is 1, corresponds to single line SPI when SPI_TYPE is 0.
In this truth example, described main frame is by the control of the chip selection signal in the chip selection signal line 102 CPLD gating, and as shown in Figure 4, described chip selection signal line is 4, and 4 I/O confessions that connect respectively CPLD produce 8 chip selection signals:
As shown in Figure 4, comprise in described 4 I/O mouths that three sheet selected control donsoles and one enable the control mouth and is respectively an I/ O mouth I/O[1], the 2nd I/ O mouth I/O[2], the 3rd I/ O mouth I/O[3], the 4th I/ O mouth I/O[4].
A slice that the SPI slave of each slave selects pin to be connected to CPLD is selected logic output terminal, and when being 8 slaves, CPLD provides 8 chip selection logics, SS0 as shown in Figure 4, SS1 ... SS7.
As shown in Figure 4, slave 1 to the clock line SCK of slave 8 connect together, the data output end DO of two-wire SPI connects together, connecting together is connected to respectively described CPLD for the data input pin DI of two-wire SPI or (the data input and output DI/O of single line SPI).
In the present embodiment, at first according to the SPI interface type of slave with the firmware programming of CPLD in the CPLD chip, CPLD is delivered in the main frame by the interface type of SPI_TYPE pin (the I/O mouth of CPLD) end with slave, slave is two-wire SPI when SPI_TYPE is 1 specifically, be single line SPI when SPI_TYPE is 0, like this, can define as required selection, select very flexible.
When entering chip selection logic, in the present embodiment in order to guarantee that main frame can communicate by letter with 8 slaves, 8 chip selection logics also must be provided, chip selection logic by I/0 mouth data through CPLD(FPGA (Field Programmable Gate Array) processing unit) decoding produces, provide 8 chip selection signals to need altogether 3 I/O mouths (2^3=8), in order to guarantee when operating without SPI, can forbid the SPI communication of all mouthfuls, a SPI enable bit must be provided, before the SPI operation, open and enable, after operation is finished, close and enable, therefore CPU need provide altogether 4 I/O mouths (I/O[0 as shown in Figure 4] mouthful, I/O[1] mouthful, I/O[2] mouthful, I/O[3] mouthful) for producing the SPI chip selection signal, logic such as following table 1 are as showing:
Annotate the 1:H=high level, the L=low level, X=is indefinite;
Annotating 2:Q1, Q2 is level 0 or 1;
Annotate 3: input is for CPLD with output.
Table 1: chip selection logic table
The below specifically describes the SPI read-write control procedure of the embodiment of the invention:
In SPI read-write process, be very different on the SPI communication logic for the SPI of two-wire communication and single line, all these differences are all carried out logic control and adjustment by CPLD, so main frame is delivered to CPLD(FPGA (Field Programmable Gate Array) processing unit by SPI_WR (SPI writes indicator signal) and SPI_RD (SPI reads indicator signal) with reading writing information), as shown in Figure 4, CPLD(FPGA (Field Programmable Gate Array) processing unit) according to read-write data receiving and transmitting signal line is adjusted, concrete logic is as follows:
1) when SPI_TYPE is 1 (when slave is two-wire SPI), the read-write steering logic is as shown in table 2 below:
Table 2: double rail logic table
In this enforcement when slave is two-wire SPI, no matter adopt what SPI_RD of SPI_WR to be worth CPLD(FPGA (Field Programmable Gate Array) processing unit why) MOSI that controls main frame links to each other with the DI of slave, the DO of slave is linked to each other with the MISO of main frame.When main frame sends data, at first according to the chip selection logic table shown in the upper table 1 write sheet select control bit (I/O[0], I/O[1], I/O[2]), opening afterwards sheet choosing enables (I/O[3]) and selects one road slave, then the data of main frame shift out from the MOSI of main frame, move into from the DI mouth of slave through CPLD; During host receiving data, at first also will select one road slave, the data of slave shift out from the DO of slave, move into from the MISO of main frame through CPLD, main frame by drawing high of slave realized with slave synchronously.
2), when SPI_TYPE is 0 (when slave is single line SPI), the read-write steering logic as shown in table 3 below:
Table 3 is: the single line logic
Operation when slave is single line SPI is controlled by SPI_WR and SPI_RD signal, when reading (SPI_WR=0 when effective, SPI_RD=1) CPLD links to each other the DI/O of slave with the MISO of main frame, and (SPI_WR=1, SPI_RD=0) CPLD links to each other the MOSI of main frame with the DI/O of slave when with effect.When main frame sends data, at first according to the chip selection logic table shown in the upper table 1 write sheet select control bit (I/O[0], I/O[1], I/O[2]), opening afterwards sheet choosing enables (I/O[3]) and selects one road slave juxtaposition " with effect ", then the data of main frame shift out from the MOSI of main frame, move into from the DI/O mouth of slave through CPLD; During host receiving data, at first will select one road slave juxtaposition " read effectively ", then the data of slave shift out from the DI/O of slave, move into from the MISO of main frame through CPLD, main frame by drawing high of slave realized with slave synchronously.
The present invention is the SPI communicator of the single/double wire compatible of embodiment as shown in Figure 4, and operating process is as follows:
It is as follows that process is write in two-wire SPI operation, idiographic flow is as shown in Figure 5: select one road slave to open the sheet choosing and enable, write order and address and check whether to write by the judgement symbol position and finish, if finish then data writing, check by the judgement symbol position whether data writing is finished, whole SPI writes the process end if finish then, can proceed next operation.
Two-wire SPI operation read procedure is as follows, idiographic flow is as shown in Figure 6: select one road slave to open the sheet choosing and enable, write order and address and check whether to write by the judgement symbol position and finish, finish that then to continue to write 0x06(0x06 be a blank operation among the SPI if write) produce clock, wait 0x06 writes and finishes, if finish then and can read the data that receive from the SPI reception buffer, whole SPI read procedure finishes, and can continue and carry out next one operation.
It is as follows that process is write in single line SPI operation, idiographic flow such as Fig. 7 show: select one road slave to open the sheet choosing and enable, whether put " with effect " writes order and address and checks to write by the judgement symbol position and finish, put " with effect " data writing if finish then, check by the judgement symbol position whether data writing is finished, whole SPI writes the process end if finish then, can proceed next operation.
Single line SPI operation read procedure is as follows, idiographic flow is as shown in Figure 8: select one road slave to open the sheet choosing and enable, whether put " with effect " writes order and address and checks to write by the judgement symbol position and finish, finish then and put " reading effectively " and write 0x06 and produce clock if write, wait 0x06 writes and finishes, if finish then and can read the data that receive from the SPI reception buffer, whole SPI read procedure finishes, and can proceed next operation.
When writing data 0x06, read-write control should be set to " reading effectively " for paying special attention in the single line SPI reading data course, because this operation just is the synchronizing clock signals when producing the SPI read data, this process is the process of real receive data, be set to WriteMode if will read and write control, the data sent of slave will be lost so.
Therefore, the SPI communicator that a kind of single/double wire compatible is provided of the embodiment of the invention, it can realize that single two-wire SPI interface hardware can be fully compatible, and can realize that a main frame connects a plurality of slaves by FPGA (Field Programmable Gate Array) processing unit gating.
Based on the principle of work of the SPI communicator of the single/double wire compatible of above-described embodiment, the embodiment of the invention also provides a kind of communication means of SPI communicator of described single/double wire compatible, mainly may further comprise the steps:
When slave was two-wire SPI, CPLD linked to each other the main frame output/slave input signal cable MOSI of main frame with the data input pin DI of slave, and the data output end DO of slave is linked to each other with the main frame input/slave output signal line MISO of main frame; When main frame sends data, select one road slave by CPLD, then the data of main frame are from the main frame output/slave input signal cable MOSI output of main frame, through the data-in port DI input of CPLD from slave; During host receiving data, also to select one road slave, the data of slave are from the data output end DO output of slave, process CPLD is from the main frame input/slave output signal line MISO input of main frame, and main frame is by selecting pin to draw high the synchronous of realization and slave the SPI slave of slave: specifically as mentioned above.
Operation when slave is single line SPI is controlled by a write command signal and and reads indicator signal, link to each other with the main frame input/slave output signal line MISO of main frame when reading the input/output terminal DI/O with slave of CPLD when effective, when with effect, CPLD links to each other the main frame output/slave input signal cable MOSI of main frame with the input/output terminal DI/O of slave; When main frame sends data, select one road slave juxtaposition with effect by CPLD, then the data of main frame are from the main frame output/slave input signal cable MOSI output of main frame, through the input/output terminal DI/O input of CPLD from slave; During host receiving data, at first to select one road slave juxtaposition to read effectively, then the data of slave shift out from the input/output terminal DI/O of slave, process CPLD moves into from the main frame input/slave output signal line MISO of main frame, and main frame is by selecting pin to draw high the synchronous of realization and slave the SPI slave of slave: specifically as mentioned above.
It also comprises step:
Process steps is write in two-wire SPI communication: main frame is selected one road slave to open the sheet choosing by CPLD to enable, write order and address and check whether to write by the judgement symbol position and finish, if finish then data writing, check by the judgement symbol position whether data writing is finished, whole SPI writes the process end if finish then, proceeds next operation: specifically as mentioned above.
Two-wire SPI communication read procedure step: main frame is selected one road slave to open the sheet choosing by CPLD to enable, write order and address and check whether to write by the judgement symbol position and finish, finish a blank operation generation clock that then continues to write among the SPI if write, wait for that described blank operation writes and finish, then from the SPI reception buffer, read the data that receive if finish, whole SPI read procedure finishes, and continues and carries out next one operation: specifically as mentioned above.
Process steps is write in single line SPI communication: main frame is selected one road slave to open the sheet choosing by CPLD to enable, put to write order and address and check whether to write by the judgement symbol position with effect and finish, then put with the effect data writing if finish, check by the judgement symbol position whether data writing is finished, whole SPI writes the process end if finish then, proceeds next operation: specifically as mentioned above.
Single line SPI communication read procedure step: main frame is selected one road slave to open the sheet choosing by CPLD to enable, put to write order and address and check whether to write by the judgement symbol position with effect and finish, if write to finish and then put a blank operation generation clock of reading effectively to write among the SPI, wait for that described blank operation writes and finish, if finish then and can from the SPI reception buffer, read the data that receive, whole SPI read procedure finishes, and proceeds next operation: specifically as mentioned above.
In sum, SPI communicator and the communication means thereof of single/double wire compatible provided by the present invention, it can be realized that single two-wire SPI interface hardware can be fully compatible, and have following advantage by a FPGA (Field Programmable Gate Array) processing unit:
1: single two-wire SPI interface hardware is compatibility fully, only needs to revise the CPLD firmware and gets final product, and it is flexible, convenient that interface is selected.
The driving force of the bus of 2:SPI can be adjusted by CPLD, and this facilitates for the expansion of slave.
3: the I/O mouth of main frame is deciphered the mode that produces the sheet choosing by CPLD saved the I/O mouth of main frame, and increased the SPI enable bit, guarantee when operating without SPI, to close all SPI sheet choosings.
4: when single line is used MOSI and MISO are isolated fully, under the different read-write modes DI/O linked to each other from different pin and avoided the interference that may exist each other.
Should be understood that application of the present invention is not limited to above-mentioned giving an example, for those of ordinary skills, can be improved according to the above description or conversion that all these improvement and conversion all should belong to the protection domain of claims of the present invention.
Claims (9)
1. the SPI communicator of a single/double wire compatible, comprise main frame, a plurality of slave and spi bus, described slave communicates by described spi bus and described main frame, it is characterized in that, also be connected a FPGA (Field Programmable Gate Array) processing unit between described slave and the described spi bus, described main frame also selects signal wire to link to each other with the gating end of described FPGA (Field Programmable Gate Array) processing unit by a slice;
Described main frame is controlled with described slave by described Programmable Logic Controller and is connected, and communicates according to slave and the described main frame of different chip selection logics with needs.
2. the SPI communicator of described single/double wire compatible according to claim 1 is characterized in that described FPGA (Field Programmable Gate Array) processing unit is a CPLD.
3. the SPI communicator of described single/double wire compatible according to claim 2 is characterized in that, the I/O mouth of main frame is deciphered by CPLD and produced the sheet choosing.
4. the SPI communicator of described single/double wire compatible according to claim 2 is characterized in that when described slave was 8, described spi bus comprised:
Main frame output/slave input signal cable the MOSI that is used for transmission main frame output data;
Main frame input/slave output signal line the MISO that is used for transmission main frame input data;
The first clock cable SCK1;
Be used for transmission and write the SPI write signal line of indicator signal SPI_WR;
Be used for transmission and read the SPI reading signal lines of indicator signal SPI_RD;
SPI type line SPI_TYPE is used for corresponding to two-wire SPI when SPI_TYPE is 1, corresponds to single line SPI when SPI_TYPE is 0.
5. the SPI communicator of described single/double wire compatible according to claim 4 is characterized in that described chip selection signal line is 4, and 4 I/O confessions that connect respectively CPLD produce 8 chip selection signals:
Comprise in described 4 I/O mouths that three sheet selected control donsoles and one enable the control mouth and is respectively an I/ O mouth (I/O[1]), the 2nd I/ O mouth (I/O[2]), the 3rd I/ O mouth (I/O[3]), the 4th I/ O mouth (I/O[4]).
6. the SPI communicator of described single/double wire compatible according to claim 4 is characterized in that, a slice that the SPI slave of each slave selects pin to be connected to CPLD is selected logic output terminal, and when being 8 slaves, CPLD provides 8 chip selection logics.
7. the SPI communicator of described single/double wire compatible according to claim 1 is characterized in that described main frame is CPU.
8. want the communication means of 2-7 SPI communicator of single/double wire compatible as described in each such as right for one kind, it is characterized in that, comprise step:
When slave was two-wire SPI, CPLD linked to each other the main frame output/slave input signal cable MOSI of main frame with the data input pin DI of slave, and the data output end DO of slave is linked to each other with the main frame input/slave output signal line MISO of main frame; When main frame sends data, select one road slave by CPLD, then the data of main frame are from the main frame output/slave input signal cable MOSI output of main frame, through the data-in port DI input of CPLD from slave; During host receiving data, also to select one road slave, the data of slave are exported from the data output end DO of slave, and process CPLD is from the main frame input/slave output signal line MISO input of main frame, and main frame is by selecting pin to draw high the synchronous of realization and slave the SPI slave of slave:
Operation when slave is single line SPI is controlled by a write command signal and and reads indicator signal, link to each other with the main frame input/slave output signal line MISO of main frame when reading the input/output terminal DI/O with slave of CPLD when effective, when with effect, CPLD links to each other the main frame output/slave input signal cable MOSI of main frame with the input/output terminal DI/O of slave; When main frame sends data, select one road slave juxtaposition with effect by CPLD, then the data of main frame are from the main frame output/slave input signal cable MOSI output of main frame, through the input/output terminal DI/O input of CPLD from slave; During host receiving data, at first to select one road slave juxtaposition to read effectively, then the data of slave shift out from the input/output terminal DI/O of slave, process CPLD moves into from the main frame input/slave output signal line MISO of main frame, and main frame is by selecting pin to draw high the synchronous of realization and slave the SPI slave of slave.
9. the communication means of the SPI communicator of described single/double wire compatible according to claim 8 is characterized in that it also comprises step:
Process steps is write in two-wire SPI communication: main frame is selected one road slave to open the sheet choosing by CPLD to enable, write order and address and check whether to write by the judgement symbol position and finish, if finish then data writing, check by the judgement symbol position whether data writing is finished, whole SPI writes the process end if finish then, proceeds next operation;
Two-wire SPI communication read procedure step: main frame is selected one road slave to open the sheet choosing by CPLD to enable, write order and address and check whether to write by the judgement symbol position and finish, finish a blank operation generation clock that then continues to write among the SPI if write, wait for that described blank operation writes and finish, then from the SPI reception buffer, read the data that receive if finish, whole SPI read procedure finishes, and continues and carries out next one operation;
Process steps is write in single line SPI communication: main frame is selected one road slave to open the sheet choosing by CPLD to enable, put to write order and address and check whether to write by the judgement symbol position with effect and finish, then put with the effect data writing if finish, check by the judgement symbol position whether data writing is finished, whole SPI writes the process end if finish then, proceeds next operation;
Single line SPI communication read procedure step: main frame is selected one road slave to open the sheet choosing by CPLD to enable, put to write order and address and check whether to write by the judgement symbol position with effect and finish, if write to finish and then put a blank operation generation clock of reading effectively to write among the SPI, wait for that described blank operation writes and finish, if finish then and can from the SPI reception buffer, read the data that receive, whole SPI read procedure finishes, and proceeds next operation.
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