CN102866951B - Rapid positioning method of internal storage boundary crossing errors of embedded system - Google Patents
Rapid positioning method of internal storage boundary crossing errors of embedded system Download PDFInfo
- Publication number
- CN102866951B CN102866951B CN201210355651.3A CN201210355651A CN102866951B CN 102866951 B CN102866951 B CN 102866951B CN 201210355651 A CN201210355651 A CN 201210355651A CN 102866951 B CN102866951 B CN 102866951B
- Authority
- CN
- China
- Prior art keywords
- task
- memory
- border
- programmable logic
- function
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a rapid positioning method of internal storage boundary crossing errors of an embedded system, which comprises the following steps of: monitoring several boundary crossing use internal storage areas through the programmable logic device, and producing interruption when the boundary crossing use internal storage areas are visited, wherein the internal storage areas are configured on a programmable logic device; querying the executing current task before interruption through a central processing unit (CPU), and obtaining a function for visiting the boundary crossing use internal storage areas; and determining whether the function causes the internal storage boundary crossing or not according to a legal visit task set and a legal visit function set configured on the programmable logic device, and outputting the task of the function causing the internal storage boundary crossing and an instruction address. The rapid positioning method can fast determine the task which causes the internal storage boundary crossing errors and the specific function which is directly called by the task to cause the internal storage boundary crossing errors, therefore, the time for troubleshooting the concealed errors of the embedded system can be reduced, and the efficiency of the system debugging can be improved.
Description
Technical field
The present invention relates to embedded system, be specifically related to embedded system memory border-crossing error method for rapidly positioning.
Background technology
Memory overwriting mistake is mistake more common in software, is also very fatal mistake.The widespread use of C language is a double-edged sword, benefit is: it enables a large amount of personnel of specialized education that were not subject to grasp program design faster, possesses certain Software for Design ability, also software decoding process is made greatly to shorten, harm is: or due to the pressure of project process, or due to the error of programmer, the software error much just should got rid of in the compilation phase, not be compiled system discovery; Or be found and had warning message to export, but having been ignored by programmer; Finally develop into serious run-time error, memory overwriting mistake is most just to be produced thus, as this several situation of Fig. 4, Fig. 5, Fig. 6 and Fig. 7, the root of mistake is all very small, or fallen " * " number, or loop variable numerical value only many 1, seem a just simple clerical mistake, but cause memory overwriting mistake.
Memory overwriting mistake is due to the illegal use to internal memory, the consequence produced is very serious, the lighter is not correct data due to the data used, and causes the result of system output error, as the situation of Fig. 4 and Fig. 6, although software is read to cross the border or write-overflow, but because the data misread or the data revised do not use further by mistake, but directly output, in this case, system is still healthy and strong, but Output rusults mistake; Severe one destroys the system core due to border-crossing error, causes system crash, as the situation of Fig. 5 and Fig. 7, unexpected data are used as a function and are performed by the former, consequence is well imagined, latter directly removes interrupt vector table, and when there being interruption to produce, system will be collapsed.
And along with system is tending towards huge, memory overwriting mistake more and more difficulty finds immediate cause, especially when the probability causing the execution route of memory overwriting to perform is very low.The memory overwriting mistake that a module causes, the investigation time is sometimes even considerably beyond the time of this module of design.
Embedded system is due to the inherent characteristic of itself, debugging often adopts the remote debugging in conjunction with main frame and target machine, the examination of each step all needs the repeatedly mutual of main frame and target machine, and debugging efficiency is extremely low, and the difficulty of investigation EMS memory error is large more than simple debug host software.Therefore, the effective means of debug host software: " breaking ", " single step ", " checking variable and internal memory at breakpoint place " etc., substantially can not use in embedded systems, the hidden mistake of investigation embedded system completes often through code check with in the mode that then statement that the insertion of suspect code inside prints some significant variable carries out analyzing based on the information printed, and these, need could realize on the basis of cost a large amount of time, further, whether these debugging methods effectively depend on ability and the experience of programming personnel to a great extent.
As can be seen here, be badly in need of a kind of embedded system memory border-crossing error method for rapidly positioning, to reduce the time of the hidden mistake of investigation embedded system, improve the efficiency of system debug.
Summary of the invention
Technical matters to be solved by this invention solves embedded system in debug process, for the problem that the memory overwriting mistake investigation time is long.
In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is to provide a kind of embedded system memory border-crossing error method for rapidly positioning, comprises the following steps:
Monitored some use region of memorys that cross the border of configuration on it by programmable logic device (PLD), produce when using region of memory accessed when crossing the border described in any one and interrupt;
The current task that CPU inquiry is performing before interrupting, and obtain crossing the border described in access using the function of region of memory according to the instruction counter of current task;
Close according to the Lawful access task-set that described programmable logic device (PLD) configures and Lawful access function, determine whether described function is the function causing memory overwriting, and export the task name and the instruction address that cause the function of memory overwriting.
In the above-mentioned methods, described crossing the border uses region of memory comprise start address, end address and enliven logo area, when using region of memory accessed when crossing the border, its logo area is set as " enlivening ", and removes other " enlivening " mark using region of memory that crosses the border;
Described Lawful access mission bit stream comprises task identification and task name;
Described Lawful access function information comprises function name, function start address sum functions end address;
Described task name is associated with described function name.
In the above-mentioned methods, described programmable logic device (PLD) periodically to cpu address bus sampling, obtains the memory address that current task uses.
In the above-mentioned methods, obtain crossing the border described in access using the instruction address of region of memory according to the task control block message of described current task, and according to the task-set sum functions collection configured in programmable logic device (PLD), judge whether described current task uses the Lawful access task of region of memory for crossing the border described in access, judge whether function corresponding to above-mentioned instruction address uses the Lawful access function of region of memory for crossing the border described in access simultaneously, if have at least one to be no in above-mentioned two judged results, then export current task name and instruction address.
The present invention, by means of programmable logic device (PLD), combined with hardware and software, determine to cause task (or the process of memory overwriting mistake fast, below all with task presentation) and the concrete function directly causing memory overwriting mistake of this task call, to decrease the time of the hidden mistake of investigation embedded system, improve the efficiency of system debug.
Accompanying drawing explanation
Fig. 1 is process flow diagram of the present invention;
Fig. 2 is the annexation schematic diagram of programmable logic device (PLD) and CPU;
Fig. 3 is the configuration information schematic diagram of programmable logic device (PLD);
Fig. 4 is the slight effect schematic diagram that internal memory is read to cross the border to system;
Fig. 5 is that internal memory is read the collapsibility crossed the border on system and affected schematic diagram;
Fig. 6 is the slight effect schematic diagram of memory write-overflow to system;
Fig. 7 is that the collapsibility of memory write-overflow on system affects schematic diagram;
Fig. 8 is the task control block (TCB) example of real-time multi-task operating system.
Embodiment
Embedded system memory border-crossing error method for rapidly positioning provided by the invention, some use region of memorys that cross the border of configuration on it are monitored by programmable logic device (PLD), and produce interruption when any one crosses the border and uses region of memory accessed, according to interrupting, CPU judges that current task and Access Violation use the function of region of memory whether legal, and export the function and the instruction address that cause memory overwriting.Below in conjunction with accompanying drawing, the present invention is described in detail.
Fig. 1 is process flow diagram of the present invention, and as shown in Figure 1, embedded system memory border-crossing error method for rapidly positioning comprises the following steps.
Step 1: set some crossing the border and use the task-set sum functions collection of region of memory and the above-mentioned region of memory of Lawful access, referred to as Lawful access task-set and Lawful access collection of functions in programmable logic device (PLD).
As shown in Figure 3, each crosses the border and uses region of memory comprise start address, end address and enliven logo area, when multiple cross the border that to use in region of memory some accessed time, its logo area is set as " enlivening "; It is distinguish to cross the border which to use in region of memory current accessed, to facilitate software process that zone bit " enlivens " object.Each Lawful access task comprises task identification and task name; Each Lawful access function comprises function name, function start address sum functions end address; Task name function name is associated.
Step 2, set the sample frequency of programmable logic device (PLD) by CPU, monitored some use region of memorys that cross the border of configuration it on by the monitor task in programmable logic device (PLD), produce interruption when any one crosses the border and uses region of memory accessed.The order that starts or stops that the startup of monitor task and stopping are sent by CPU controls.Be described as follows:
Fig. 2 is the connection diagram of programmable logic device (PLD) and CPU, only give the annexation figure for realizing address bus monitoring sampling section here, and the interface annexation of CPU management and control programming device has generality, does not repeat them here.
CPU management and control the information interaction that the interface of programmable logic device (PLD) is used for realizing between CPU and programmable logic device (PLD), use the generalized case of programmable logic device (PLD) identical with system, namely the storage inside of programmable logic device (PLD) directly uses as the addressable address space of CPU, also programmable logic device (PLD) can be regarded as peripherals administration and the access of CPU.
The primary memory of embedded system can be that SRAM or DRAM(comprises SDRAM and DDR etc.), for SRAM and DRAM, the annexation that address bus detects and logic have very big difference, Fig. 2 is actual gives of comprising SRAM or DRAM total annexation, is determined on a case-by-case basis in practical application.If use DRAM class memory device, then only use a subset in address wire " A0..A31 " to input as row address and column address, row choosing " RAS ", column selection " CAS " must use, and use the system of SDRAM, and " SDRAM_CLK " also needs to adopt.If use SRAM class memory device, then address wire " A0..A31 " is selected depending on the situation of SRAM device, and " RAS ", " CAS " and " SDRAM_CLK " then do not adopt.
" INTR " is interrupt request singal, when programmable logic device (PLD) judges certain region of memory scope configured of address bus sampling hit, then exports a pulse to interrupt to CPU request at " INTR ".
CPU writes the task-set sum functions collection of cross the border use region of memory (can be one or more) and the above-mentioned region of memory of Lawful access to programmable logic device (PLD) by management control interface, monitor that (each task-set can comprise a task, also can comprise many tasks for region of memory range information (can be one or more), legitimate tasks information and Lawful access function information; Each collection of functions can comprise a function or many functions equally).As shown in Figure 3, cross the border and use region of memory to comprise many memory range information, every bar memory range information comprises start address, end address and enlivens logo area; Legitimate tasks information comprises task identification and task name; Legal function information comprises function name, function start address sum functions end address; Task name function name is associated.
After configuration information sets, set the sample frequency of programmable logic device (PLD) by CPU, it should be noted that: sample frequency should lower than the access frequency of storer, otherwise likely some important internal storage access are not monitored to.
Then programmable logic device (PLD) starts or stops according to the state of " start/stop " zone bit on it and performs monitoring task, " start/stop " zone bit can be changed by the order that starts or stops of CPU, also automatically can be revised by programmable logic device (PLD) according to the duty of programmable logic device (PLD), CPU sends startup command, then " start/stop " zone bit is revised as " startup ", CPU sends and ceases and desist order, then " start/stop " zone bit is revised as " stopping ".When " start/stop " zone bit is " startup ", programmable logic device (PLD) starts periodically to operations such as address wire samplings, otherwise does not do any operation.If in programmable logic device (PLD) sampling process, it is " stopping " that CPU revises " start/stop " zone bit, then programmable logic device (PLD) quit work in next sampling period.
When certain sampling determines that the address obtained is dropped in certain the built-in regional extent configured, and the region of memory range information of configuration is more than one, then the logo area of enlivening of this region of memory of set is " enlivening ", remove " enlivening " mark enlivening logo area of other region of memory, and " start/stop " zone bit is revised as " stopping ".Then in the upper output pulse of interrupt request singal " INTR ".
In above-mentioned functions, except configuration information is completed jointly by CPU and programmable logic device (PLD), other function is completed automatically by programmable logic device (PLD).
The current task that step 3:CPU inquiry is performing before interrupting, and obtain the instruction counter of described current task, the value then based on described instruction counter obtains crossing the border described in access using the function of region of memory.
Step 4: according to the Lawful access task-set that described programmable logic device (PLD) configures and Lawful access collection of functions, determines whether described function is the function causing memory overwriting, and exports the task and the instruction address that cause the function of memory overwriting.
May be there is larger difference along with the difference of CPU and real-time multi-task operating system in the design of interrupt service routine, but main mechanism and principle are similar.In most cases as follows: during initialization interrupt service routine, interrupt service routine to be connected with an interrupt vector, close when interrupt service routine starts to perform and interrupt and remove related interrupts state, at the end of interrupt service routine, open interruption.It should be noted that, in embedded systems, interrupt service routine is not suitable for taking too many CPU time, generally, interrupt service routine only responds the time producing and interrupt, record some information, then notify associating with this interruption of task, the task that association is all given in major part work has been gone.
In the present invention, interrupt service routine designs equally and only does less work, have no progeny in interrupt service routine response, the work done is: obtain current interrupted task identification and be stored into correct position, then notice and the task of interrupting associating have gone remaining work, why will obtain current interrupted task and buffer memory, are the execution because monitoring task can be tried to be the first, can there is task scheduling in system, cannot obtain real current interrupted mission bit stream when monitoring task starts to perform.
In fact, monitor the startup of task in the Lawful access task completed in monitoring task and the filtration work of Lawful access function and programming device and stop being placed in interrupt service routine completing.If the benefit completing these work in interrupt service routine is: too much task scheduling can occur anti-locking system, because current active task is not monitoring task, so need to reschedule from current active task switch to monitoring task system.Harm is: if Lawful access mission bit stream sum functions information is too much, Lawful access task sum functions information filtering work will take more CPU time, and in embedded system, interrupting should the least possible CPU time that takies, therefore these functions are moved on to realize in monitoring task relatively good.
Monitoring task coordinates interrupt service routine and arranges, technologically speaking, what monitoring task was done is operated in interrupt service routine and can realizes, but in embedded system, interrupt service routine is not suitable for taking too many CPU time, therefore, major part work all move on to complete in monitoring task more reasonable.
First, monitoring task need be notified from interrupt service routine (normally with semaphore transmit mode), then started oneself work (as can not get interrupt service routine notice, monitoring task is then in blocked state).
Then, the current accessed task identification A(that monitoring task need obtain this region of memory from interrupt service routine is stored into certain region), and obtain task control block (TCB) based on A mark, the example of task control block (TCB) as shown in Figure 8, the partial information of what Fig. 8 described is task control block (TCB) in real-time multi-task operating system VXWORKS.Obtained the instruction counter (instruction address) of current execution by task control block (TCB) further, then perform Lawful access task filtering function.
If the Lawful access task of this task of filter result this region of memory non-, then export this mission bit stream and instruction counter information.
If this task of filter result is the Lawful access task of this region of memory, then, monitoring task has also needed Lawful access function filtering function, if filter result is Lawful access function, then do not perform any operation, otherwise export this mission bit stream and instruction counter information.
After the operation of above-mentioned filtering function and correspondence completes, " start/stop " zone bit is revised as " startup ", gets back to the state continuing to wait for interrupt service routine notice.
Monitoring task is actually periodic task, from the notice receiving interrupt service routine, to Output rusults or complete filter but be a treatment cycle without result end of output.But treatment cycle is not fixed value, and reports with the interruption of programming device and associate.
In the present invention, programmable logic device (PLD) can be the devices such as GAL, CPLD or FPGA, as such devices existing in system, can directly and other functional module this device multiplexing, and not need to increase a slice such devices specially; As not having such devices in system, then visual concrete condition selects suitable device.
The software of embedded system is based on real-time multi-task operating system, and this real-time multi-task operating system can be the one in the embedded OSs such as VXWORKS, LINUX, OS II, ECOS.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structure change made under enlightenment of the present invention, and every have identical or close technical scheme with the present invention, all falls within protection scope of the present invention.
Claims (4)
1. embedded system memory border-crossing error method for rapidly positioning, is characterized in that, comprises the following steps:
Monitored some use region of memorys that cross the border of configuration on it by programmable logic device (PLD), produce when using region of memory accessed when crossing the border described in any one and interrupt; Described crossing the border uses region of memory to comprise start address, end address and logo area, and when using region of memory accessed when crossing the border, its logo area is set as " enlivening ", and removes other " enlivening " mark using region of memory that crosses the border;
The current task that CPU inquiry is performing before interrupting, and obtain crossing the border described in access using the function of region of memory according to the instruction counter of current task;
According to the Lawful access task-set that described programmable logic device (PLD) configures and Lawful access collection of functions, determine whether described function is the function causing memory overwriting, and export the task name and the instruction address that cause the function of memory overwriting;
Programmable logic device (PLD) starts or stops according to the state of " start/stop " zone bit on it and performs monitoring task, " start/stop " zone bit can be changed by the order that starts or stops of CPU, also automatically can be revised by programmable logic device (PLD) according to the duty of programmable logic device (PLD), CPU sends startup command, then " start/stop " zone bit is revised as " startup ", CPU sends and ceases and desist order, then " start/stop " zone bit is revised as " stopping "; When " start/stop " zone bit is " startup ", programmable logic device (PLD) starts periodically to address wire sampling operation, otherwise does not do any operation; If in programmable logic device (PLD) sampling process, it is " stopping " that CPU revises " start/stop " zone bit, then programmable logic device (PLD) quit work in next sampling period;
When certain sampling determines that the address obtained is dropped in certain the built-in regional extent configured, and the region of memory range information of configuration is more than one, then the logo area of enlivening of this region of memory of set is " enlivening ", remove " enlivening " mark enlivening logo area of other region of memory, and " start/stop " zone bit is revised as " stopping ".
2. embedded system memory border-crossing error method for rapidly positioning as claimed in claim 1, is characterized in that,
Described Lawful access mission bit stream comprises task identification and task name;
Described Lawful access function information comprises function name, function start address sum functions end address;
Described task name is associated with described function name.
3. embedded system memory border-crossing error method for rapidly positioning as claimed in claim 1, is characterized in that,
Described programmable logic device (PLD) periodically to cpu address bus sampling, obtains the memory address that current task uses.
4. embedded system memory border-crossing error method for rapidly positioning as claimed in claim 1, is characterized in that,
Obtain crossing the border described in access using the instruction address of region of memory according to the task control block message of described current task, and according to the task-set sum functions collection configured in programmable logic device (PLD), judge whether described current task uses the Lawful access task of region of memory for crossing the border described in access, judge whether function corresponding to above-mentioned instruction address uses the Lawful access function of region of memory for crossing the border described in access simultaneously, if have at least one to be no in above-mentioned two judged results, then export current task name and instruction address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210355651.3A CN102866951B (en) | 2012-09-21 | 2012-09-21 | Rapid positioning method of internal storage boundary crossing errors of embedded system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210355651.3A CN102866951B (en) | 2012-09-21 | 2012-09-21 | Rapid positioning method of internal storage boundary crossing errors of embedded system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102866951A CN102866951A (en) | 2013-01-09 |
| CN102866951B true CN102866951B (en) | 2015-07-15 |
Family
ID=47445830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210355651.3A Active CN102866951B (en) | 2012-09-21 | 2012-09-21 | Rapid positioning method of internal storage boundary crossing errors of embedded system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102866951B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104461880B (en) * | 2014-12-04 | 2018-01-09 | 福建星网视易信息系统有限公司 | The method and system of automatic detection memory overwriting in a kind of embedded system |
| CN106126360B (en) * | 2016-06-28 | 2020-08-25 | 海信视像科技股份有限公司 | Address hole shielding method and device |
| CN106502926B (en) * | 2016-09-26 | 2019-11-19 | 华为技术有限公司 | A kind of internal memory monitoring method, internal storage access controller and SoC system |
| CN109086193B (en) * | 2017-06-13 | 2022-01-21 | 阿里巴巴集团控股有限公司 | Monitoring method, device and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1885275A (en) * | 2005-06-20 | 2006-12-27 | 中兴通讯股份有限公司 | Embedded system and real-time monitoring and processing method thereof |
| CN101110042A (en) * | 2006-07-20 | 2008-01-23 | 中兴通讯股份有限公司 | Method for detecting memory accessing outside |
| CN101174241A (en) * | 2006-10-31 | 2008-05-07 | 中兴通讯股份有限公司 | Locating method and system for repeated memory release |
| CN101174242A (en) * | 2007-09-26 | 2008-05-07 | 中兴通讯股份有限公司 | Method and system for capturing and storing bare nucleus exception in multi-core processor |
| CN101533370A (en) * | 2009-04-09 | 2009-09-16 | 成都市华为赛门铁克科技有限公司 | Memory abnormal access positioning method and device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8607094B2 (en) * | 2009-09-29 | 2013-12-10 | Hyundai Motor Company | Operational system test method |
-
2012
- 2012-09-21 CN CN201210355651.3A patent/CN102866951B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1885275A (en) * | 2005-06-20 | 2006-12-27 | 中兴通讯股份有限公司 | Embedded system and real-time monitoring and processing method thereof |
| CN101110042A (en) * | 2006-07-20 | 2008-01-23 | 中兴通讯股份有限公司 | Method for detecting memory accessing outside |
| CN101174241A (en) * | 2006-10-31 | 2008-05-07 | 中兴通讯股份有限公司 | Locating method and system for repeated memory release |
| CN101174242A (en) * | 2007-09-26 | 2008-05-07 | 中兴通讯股份有限公司 | Method and system for capturing and storing bare nucleus exception in multi-core processor |
| CN101533370A (en) * | 2009-04-09 | 2009-09-16 | 成都市华为赛门铁克科技有限公司 | Memory abnormal access positioning method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102866951A (en) | 2013-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103268277B (en) | A kind of method and system of output journal information | |
| KR102025078B1 (en) | Diagnosing code using single step execution | |
| CN102866951B (en) | Rapid positioning method of internal storage boundary crossing errors of embedded system | |
| CN101251821B (en) | Selective disabling of diagnostic functions within a data processing system | |
| US20030154430A1 (en) | On-chip instrumenation | |
| CN108549591A (en) | A kind of black box device and its implementation of embedded system | |
| CN105718374A (en) | Method and system for hotspot module instruction tracking | |
| CN104778116B (en) | A kind of multibreak software debugging device and method | |
| CN102207913B (en) | The control method and device of write-protect in embedded system | |
| CN100388234C (en) | Method for monitoring internal memory varible rewrite based on finite-state-machine | |
| CN109254883B (en) | Debugging device and method for on-chip memory | |
| CN104685509B (en) | For the method and control device of the separated operation for controlling the program block linked | |
| CN101639805A (en) | Method and equipment for tracing variable in program debugging | |
| CN103197914B (en) | Multiprocessor postpones the method and system performed | |
| CN109144873A (en) | A kind of linux kernel processing method and processing device | |
| CN104410671A (en) | Snapshot capturing method and data monitoring tool | |
| CN105095079B (en) | A kind of method and apparatus of hot spot module instruction trace | |
| CN113377701B (en) | Serial port control system based on complex programmable logic device CPLD and communication method thereof | |
| CN110011854A (en) | MDS fault handling method, device, storage system and computer readable storage medium | |
| US20060265577A1 (en) | Real-time monitoring, alignment, and translation of cpu stalls or events | |
| CN101329650A (en) | Smart card emulator | |
| CN106528414A (en) | Processor chip simulator | |
| CN109634796A (en) | A kind of method for diagnosing faults of computer, apparatus and system | |
| CN100369009C (en) | Monitor system and method capable of using interrupt signal of system management | |
| Lu et al. | An approach for improving fault-tolerance in automotive modular embedded software |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170327 Address after: 430000 East Lake high tech Development Zone, Hubei Province, No. 6, No., high and new technology development zone, No. four Patentee after: Fenghuo Communication Science &. Technology Co., Ltd. Address before: East Lake high tech city of Wuhan province Hubei Dongxin road 430074 No. 5 East optical communication industry building in Wuhan Fenghuo Network Co Ltd Patentee before: Wuhan Fenghuo Network Co., Ltd. |