CN102681586B - There is the voltage regulator of the defencive function that powers on - Google Patents
There is the voltage regulator of the defencive function that powers on Download PDFInfo
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- CN102681586B CN102681586B CN201210191414.8A CN201210191414A CN102681586B CN 102681586 B CN102681586 B CN 102681586B CN 201210191414 A CN201210191414 A CN 201210191414A CN 102681586 B CN102681586 B CN 102681586B
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Abstract
The invention discloses a kind of voltage regulator with the defencive function that powers on, comprise mirror-image constant flow source, control circuit, biasing circuit, feedback circuit, output transistor and power-on protective circuit, wherein, this power-on protective circuit and this biasing circuit are connected in parallel in this control circuit, with between reference voltage in time powering on non-stationary phase, make this mirror-image constant flow source, path is formed between this control circuit and this power-on protective circuit, it is zero that this voltage regulator is exported, pass through the present invention, it is zero that voltage regulator can be made to export in the period that powers on, reach the object of protection subsequent conditioning circuit.
Description
Technical field
The present invention relates to a kind of voltage regulator, particularly relate to a kind of voltage regulator with the defencive function that powers on.
Background technology
Fig. 1 is the circuit diagram of voltage regulator common in prior art.As shown in Figure 1, voltage regulator comprises PMOS transistor P1/P2, nmos pass transistor N1/N2, bias current Ibias, PMOS transistor P3 and resistance R1/R2, wherein, P1/P2/P3 source electrode connects supply voltage, the feedback voltage FB that N1 grid connecting resistance R1/R2 intermediate node produces, N2 grid meets reference voltage VREF, and the output voltage VR of PMOS transistor P3 drain electrode stable output is to integrated circuit (IC).
But, but there are the following problems for above-mentioned voltage regulator: when VREF/Ibias can not follow supply voltage VDD rising when powering on, the drain voltage of nmos pass transistor N2 is determined (now M2/N2 all not conductings) by the electric leakage dividing potential drop of M2/N2, drain voltage and PMOS transistor P3 grid floating, when voltage is lower, P3 heavily conducting, thus the drain voltage of P3 (i.e. output voltage) VR equals supply voltage VDD, the sequential of VDD/Ibias/VREF/VR as shown in Figure 2, when this means to power on, voltage regulator does not normally work, thus make supply voltage VDD high pressure directly be added in follow-up IC(integrated circuit) on, the damage of follow-up integrated circuit may be caused.
In sum, there is cisco unity malfunction when powering on and cause supply voltage to be directly added in the problem that follow-up integrated circuit causes circuit to damage in the voltage regulator of known prior art, therefore the real technological means being necessary to propose to improve, solves this problem.
Summary of the invention
For overcoming the deficiency that above-mentioned prior art exists, the object of the present invention is to provide a kind of voltage regulator with the defencive function that powers on, and it makes voltage regulator output during powering on be zero by a power-on protective circuit, reaches the object of protection subsequent conditioning circuit.
For reaching above-mentioned and other object; the invention provides a kind of voltage regulator with the defencive function that powers on; comprise mirror-image constant flow source, control circuit, biasing circuit, feedback circuit and output transistor; in addition; this voltage regulator also comprises a power-on protective circuit; this power-on protective circuit and this biasing circuit are connected in parallel in this control circuit; with between reference voltage in time powering on non-stationary phase; make this mirror-image constant flow source, form path between this control circuit and this power-on protective circuit, it is zero that this voltage regulator is exported.
Further, this power-on protective circuit comprises the 4th PMOS transistor, and the 4th PMOS transistor grid connects reference voltage, and source electrode is connected to this control circuit, grounded drain.
Further, this mirror-image constant flow source comprises the first PMOS transistor and the second PMOS transistor, this first PMOS transistor and this second PMOS transistor source electrode are all connected to supply voltage, be connected with this second PMOS transistor grid after the interconnection of this first PMOS transistor grid leak, two PMOS transistor drain electrodes are all connected to this control circuit, and this second PMOS transistor drain electrode simultaneously also lotus root is connected to this output transistor gates.
Further, this control circuit comprises the first nmos pass transistor and the second nmos pass transistor, this the first nmos pass transistor grid connects the feedback voltage that this feedback circuit exports, drain electrode drains with this first PMOS transistor and is connected, source electrode is connected with the 4th PMOS transistor source electrode and this biasing circuit, this the second nmos pass transistor grid connects reference voltage, drains to drain with this second PMOS transistor and this output transistor gates is connected, and source electrode is connected with the 4th PMOS transistor source electrode and this biasing circuit.
Further, this feedback circuit comprises the first resistance and the second resistance, and this first resistance and this second resistant series are connected to this output transistor and drain and between ground, the intermediate node of this first resistance and this second resistance exports this feedback voltage.
Further, this biasing circuit is bias current sources.
Further, this output transistor is PMOS transistor.
Compared with prior art; the voltage regulator that the present invention is a kind of has a defencive function that powers on by increase by power-on protective circuit to make to form path between mirror-image constant flow source, control circuit and power-on protective circuit in time powering on; reach in power on period make voltage regulator export be zero object; thus protect subsequent conditioning circuit, solve in prior art the problem that during powering on, voltage regulator does not normally work.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of voltage regulator common in prior art;
Fig. 2 is the time diagram of the voltage regulator of prior art;
Fig. 3 is a kind of circuit diagram with the preferred embodiment of the voltage regulator of the defencive function that powers on of the present invention;
Fig. 4 is the sequential chart of present pre-ferred embodiments.
Embodiment
Below by way of specific instantiation and accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention is also implemented by other different instantiation or is applied, and the every details in this instructions also can based on different viewpoints and application, carries out various modification and change not deviating under spirit of the present invention.
Fig. 3 is a kind of circuit diagram with the preferred embodiment of the voltage regulator of the defencive function that powers on of the present invention.As shown in Figure 3, a kind of voltage regulator 300 with the defencive function that powers on of the present invention, comprising: mirror-image constant flow source 301, control circuit 302, biasing circuit 303, feedback circuit 304, output transistor P3 and power-on protective circuit 305.Voltage regulator 300 be for provide through its output terminal 30 stable with reliable output voltage VR the (not shown) to another circuit or system.
Mirror-image constant flow source 301 comprises the first PMOS transistor P1 and the second PMOS transistor P2, first PMOS transistor P1 and the second PMOS transistor P2 source electrode are all connected to supply voltage VDD, be connected with the second PMOS transistor P2 grid after first PMOS transistor P1 grid leak interconnection, two PMOS transistor drain electrodes are all connected to control circuit 302, and the second PMOS transistor drain electrode simultaneously also lotus root is connected to output transistor P3 control end, control circuit 302 and mirror-image constant flow source 301, it comprises first input end, second input end and output terminal, first input end is for receiving reference voltage VREF, second input end is for receiving feedback voltage FB, output terminal lotus root is connected to the control end of output transistor P3, specifically, control circuit 302 comprises the first nmos pass transistor N1 and the second nmos pass transistor N2, wherein, first nmos pass transistor N1 grid meets feedback voltage FB, drain electrode drains with the first PMOS transistor P1 and is connected, source electrode is connected with power-on protective circuit 305 and biasing circuit 303, second nmos pass transistor N2 grid meets reference voltage VREF, drain electrode drains with the second PMOS transistor P2 and the control end of output transistor P3 is connected, source electrode is connected with power-on protective circuit 305 and biasing circuit 303, biasing circuit 303 is all connected with the first nmos pass transistor N1, the second nmos pass transistor source electrode, and in present pre-ferred embodiments, biasing circuit 303 is a bias current sources Ibias, feedback circuit 304 comprises the first resistance R1 and the second resistance R2, resistance R1 and R2 are connected in series with coating-forming voltage feedback circuit, carries out dividing potential drop to produce feedback voltage FB by this to the output voltage VR of voltage regulator, output transistor P3 is the 3rd PMOS transistor, its grid and control end, and source electrode meets supply voltage VDD, and drain electrode exports output voltage VR to subsequent conditioning circuit, power-on protective circuit 305 and biasing circuit 302 are connected in control circuit 302, exporting in the period that powers on for making voltage regulator 300 is 0, thus protection subsequent conditioning circuit, at present pre-ferred embodiments weight, power-on protective circuit 305 comprises the 4th PMOS transistor P4, 4th PMOS transistor P4 grid meets reference voltage VREF, and source electrode is all connected with the first nmos pass transistor N1, the second nmos pass transistor source electrode, grounded drain.
Fig. 4 is the sequential chart of present pre-ferred embodiments, below cooperation Fig. 4 is introduced the principle of work for the present invention further: when powering on, Ibias not yet sets up, now VREF is low, cause the first nmos pass transistor N1, second nmos pass transistor N2 is all obstructed, 4th PMOS transistor P4 conducting, if the dividing potential drop of output voltage VR (i.e. feedback voltage FB) makes the first nmos pass transistor N1 conducting, then the first PMOS transistor P1 conducting, P1-N1, P2 forms mirror image, thus the second PMOS transistor P2 conducting but the second nmos pass transistor N2 is obstructed, supply voltage VDD adds to the grid level of output transistor P3 by the second PMOS transistor P2, thus output transistor P3 can not conducting, the output voltage VR of its drain voltage and voltage regulator exports like this is zero, after powering on, Ibias and VREF is all normal, and P4 will be in off state, thus N2 drain voltage maintains reasonable value, thus P3 is made to form a variable resistor, when VR raises, then feedback voltage FB raises, thus N1 grid voltage raises, for maintaining Ibias inconvenience, the Vgs of N1 increases, and the Vgs of N2 declines, and the resistance being equivalent to N2 becomes large, and electric current is constant, then the grid voltage of the drain voltage of N2 and P3 raises, thus P3 conducting dies down VR is declined, such VR just Absorbable organic halogens at setting value VRV.
In sum; the voltage regulator that the present invention is a kind of has a defencive function that powers on by increase by power-on protective circuit to make to form path between mirror-image constant flow source, control circuit and power-on protective circuit in time powering on; reach in power on period make voltage regulator export be zero object; thus protect subsequent conditioning circuit, solve in prior art the problem that during powering on, voltage regulator does not normally work.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can carry out modifying to above-described embodiment and change.Therefore, the scope of the present invention, should listed by claims.
Claims (6)
1. one kind has the voltage regulator of the defencive function that powers on, comprise mirror-image constant flow source, control circuit, biasing circuit, feedback circuit and output transistor, it is characterized in that: this voltage regulator also comprises a power-on protective circuit, this power-on protective circuit and this biasing circuit are connected in parallel in this control circuit, with between reference voltage in time powering on non-stationary phase, make this mirror-image constant flow source, form path between this control circuit and this power-on protective circuit, it is zero that this voltage regulator is exported; This power-on protective circuit comprises the 4th PMOS transistor, and the 4th PMOS transistor grid connects reference voltage, and source electrode is connected to this control circuit, grounded drain.
2. there is the voltage regulator of the defencive function that powers on as claimed in claim 1; it is characterized in that: this mirror-image constant flow source comprises the first PMOS transistor and the second PMOS transistor; this first PMOS transistor and this second PMOS transistor source electrode are all connected to supply voltage; be connected with this second PMOS transistor grid after the interconnection of this first PMOS transistor grid leak; two PMOS transistor drain electrodes are all connected to this control circuit, and this second PMOS transistor drain electrode simultaneously is also coupled to this output transistor gates.
3. there is the voltage regulator of the defencive function that powers on as claimed in claim 2, it is characterized in that: this control circuit comprises the first nmos pass transistor and the second nmos pass transistor, this the first nmos pass transistor grid connects the feedback voltage that this feedback circuit exports, drain electrode drains with this first PMOS transistor and is connected, source electrode is connected with the 4th PMOS transistor source electrode and this biasing circuit, this the second nmos pass transistor grid connects reference voltage, drain electrode drains with this second PMOS transistor and this output transistor gates is connected, source electrode is connected with the 4th PMOS transistor source electrode and this biasing circuit.
4. there is the voltage regulator of the defencive function that powers on as claimed in claim 3; it is characterized in that: this feedback circuit comprises the first resistance and the second resistance; this first resistance and this second resistant series are connected to this output transistor and drain and between ground, the intermediate node of this first resistance and this second resistance exports this feedback voltage.
5. there is the voltage regulator of the defencive function that powers on as claimed in claim 1, it is characterized in that: this biasing circuit is bias current sources.
6. there is the voltage regulator of the defencive function that powers on as claimed in claim 1, it is characterized in that: this output transistor is PMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210191414.8A CN102681586B (en) | 2012-06-11 | 2012-06-11 | There is the voltage regulator of the defencive function that powers on |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210191414.8A CN102681586B (en) | 2012-06-11 | 2012-06-11 | There is the voltage regulator of the defencive function that powers on |
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| CN102681586A CN102681586A (en) | 2012-09-19 |
| CN102681586B true CN102681586B (en) | 2015-08-19 |
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| CN201210191414.8A Active CN102681586B (en) | 2012-06-11 | 2012-06-11 | There is the voltage regulator of the defencive function that powers on |
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| US9851740B2 (en) * | 2016-04-08 | 2017-12-26 | Qualcomm Incorporated | Systems and methods to provide reference voltage or current |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0895325A2 (en) * | 1997-07-31 | 1999-02-03 | Kabushiki Kaisha Toshiba | Temperature dependent constant-current generating circuit and light emitting semiconductor element driving circuit using the same |
| US20020145467A1 (en) * | 2001-04-05 | 2002-10-10 | Minch Bradley A. | Folded floating-gate differential pair amplifier |
| CN1503453A (en) * | 2002-11-25 | 2004-06-09 | 上海贝岭股份有限公司 | Self-adaptive controlled voltage-stabilized source |
| CN101192070A (en) * | 2006-11-24 | 2008-06-04 | 北京中电华大电子设计有限责任公司 | Power-on protection method and circuit for voltage regulator |
| CN201674388U (en) * | 2010-05-13 | 2010-12-15 | 西安深亚电子有限公司 | Power tube current limiting protection adjusting circuit for powered devices (PDs) |
| CN102214987A (en) * | 2010-04-06 | 2011-10-12 | 大连精拓光电有限公司 | System for providing over-current protection for switching power converter |
-
2012
- 2012-06-11 CN CN201210191414.8A patent/CN102681586B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0895325A2 (en) * | 1997-07-31 | 1999-02-03 | Kabushiki Kaisha Toshiba | Temperature dependent constant-current generating circuit and light emitting semiconductor element driving circuit using the same |
| US20020145467A1 (en) * | 2001-04-05 | 2002-10-10 | Minch Bradley A. | Folded floating-gate differential pair amplifier |
| CN1503453A (en) * | 2002-11-25 | 2004-06-09 | 上海贝岭股份有限公司 | Self-adaptive controlled voltage-stabilized source |
| CN101192070A (en) * | 2006-11-24 | 2008-06-04 | 北京中电华大电子设计有限责任公司 | Power-on protection method and circuit for voltage regulator |
| CN102214987A (en) * | 2010-04-06 | 2011-10-12 | 大连精拓光电有限公司 | System for providing over-current protection for switching power converter |
| CN201674388U (en) * | 2010-05-13 | 2010-12-15 | 西安深亚电子有限公司 | Power tube current limiting protection adjusting circuit for powered devices (PDs) |
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| CN102681586A (en) | 2012-09-19 |
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Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address after: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Grace Semiconductor Manufacturing Corp. |
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