CN102681586A

CN102681586A - Voltage regulator with power-on protection function

Info

Publication number: CN102681586A
Application number: CN2012101914148A
Authority: CN
Inventors: 杨光军; 肖军; 黄碧
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2012-06-11
Filing date: 2012-06-11
Publication date: 2012-09-19
Anticipated expiration: 2032-06-11
Also published as: CN102681586B

Abstract

The invention discloses a voltage regulator with a power-on protection function, which comprises an image constant-current source, a control circuit, a biasing circuit, a feedback circuit, an output transistor and a power-on protection circuit, wherein the power-on protection circuit and the biasing circuit are connected in parallel to the control circuit, and when a reference voltage is not stabilized in a power-on process, a path is formed among the image constant-current source, the control circuit and the power-on protection circuit, so that the output of the voltage regulator is zero. According to the invention, the output of the voltage regulator can be zero in the power-on process, thereby achieving the purpose of protecting subsequent circuits.

Description

Voltage regulator with the defencive function that powers on

Technical field

The present invention relates to a kind of voltage regulator, particularly relate to a kind of voltage regulator with the defencive function that powers on.

Background technology

Fig. 1 is the circuit diagram of voltage regulator common in the prior art.As shown in Figure 1; Voltage regulator comprises PMOS transistor P1/P2, nmos pass transistor N1/N2, bias current Ibias, PMOS transistor P3 and resistance R 1/R2; Wherein, the P1/P2/P3 source electrode connects supply voltage, the feedback voltage FB that N1 grid connecting resistance R1/R2 intermediate node produces; The N2 grid meets reference voltage VREF, and PMOS transistor P3 drain electrode output stable output voltage V R give IC.

Yet but there is following problem in above-mentioned voltage regulator: when VREF/Ibias can not follow supply voltage VDD rising when powering on, the drain voltage of nmos pass transistor N2 was by the electric leakage dividing potential drop decision (all not conductings of M2/N2 this moment) of M2/N2; Drain voltage is that PMOS transistor P3 grid is floating empty, when voltage is low, and the P3 heavily conducting; Thereby the drain voltage of P3 (being output voltage) VR equals supply voltage VDD; The sequential of VDD/Ibias/VREF/VR is as shown in Figure 2, this means that when powering on, voltage regulator does not have operate as normal; Thereby supply voltage VDD high pressure directly is added on the follow-up IC (integrated circuit), possibly causes the damage of follow-up integrated circuit.

In sum, the problem that the voltage regulator that can know prior art exists cisco unity malfunction when powering on to cause supply voltage directly to be added in to cause circuit to damage on the follow-up integrated circuit is necessary to propose improved technological means therefore in fact, solves this problem.

Summary of the invention

For overcoming the deficiency that above-mentioned prior art exists, the present invention's purpose is to provide a kind of voltage regulator with the defencive function that powers on, and it makes voltage regulator during powering on, be output as zero through the holding circuit that powers on, and has reached the purpose of protection subsequent conditioning circuit.

For reaching above-mentioned and other purpose; The present invention provides a kind of voltage regulator with the defencive function that powers on; Comprise mirror-image constant flow source, control circuit, biasing circuit, feedback circuit and output transistor, in addition, this voltage regulator also comprises the holding circuit that powers on; This power on holding circuit and this biasing circuit are connected in parallel in this control circuit; With reference voltage when powering on not between stationary phase, this mirror-image constant flow source, this control circuit and this are powered on form path between the holding circuit, make this voltage regulator be output as zero.

Further, this holding circuit that powers on comprises the 4th PMOS transistor, and the 4th PMOS transistor gate connects reference voltage, and source electrode is connected to this control circuit, grounded drain.

Further; This mirror-image constant flow source comprises a PMOS transistor AND gate the 2nd PMOS transistor; The one PMOS transistor AND gate the 2nd PMOS transistor source all is connected to supply voltage; The one PMOS transistor grid leak interconnection back is connected with the 2nd PMOS transistor gate, and two PMOS transistor drains all are connected to this control circuit, simultaneously the 2nd PMOS transistor drain also lotus root be connected to this output transistor gates.

Further; This control circuit comprises first nmos pass transistor and second nmos pass transistor, and this first nmos pass transistor grid connects the feedback voltage of this feedback circuit output, and drain electrode links to each other with a PMOS transistor drain; Source electrode links to each other with the 4th PMOS transistor source and this biasing circuit; This second nmos pass transistor grid connects reference voltage, and drain electrode links to each other with the 2nd PMOS transistor drain and this output transistor gates, and source electrode links to each other with the 4th PMOS transistor source and this biasing circuit.

Further, this feedback circuit comprises first resistance and second resistance, and this first resistance and this second resistance string are connected between drain electrode of this output transistor and the ground, among this first resistance and this second resistance between node export this feedback voltage.

Further, this biasing circuit is a bias current sources.

Further, this output transistor is the PMOS transistor.

Compared with prior art; The voltage regulator that the present invention is a kind of to have a defencive function that powers on forms path through increasing by the holding circuit that powers on when powering on, to make mirror-image constant flow source, control circuit and to power between the holding circuit; Reached and during powering on, made voltage regulator be output as zero purpose; Thereby protected subsequent conditioning circuit, solved the problem that voltage regulator during powering in the prior art does not have operate as normal.

Description of drawings

Fig. 1 is the circuit diagram of voltage regulator common in the prior art;

Fig. 2 is the sequential synoptic diagram of the voltage regulator of prior art;

The circuit diagram of the preferred embodiment of the voltage regulator that Fig. 3 has a defencive function that powers on for the present invention is a kind of;

Fig. 4 is the sequential chart of preferred embodiment of the present invention.

Embodiment

Below through specific instantiation and accompanying drawings embodiment of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this instructions disclosed.The present invention also can implement or use through other different instantiation, and each item details in this instructions also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not deviating from.

The circuit diagram of the preferred embodiment of the voltage regulator that Fig. 3 has a defencive function that powers on for the present invention is a kind of.As shown in Figure 3, a kind of voltage regulator 300 with the defencive function that powers on of the present invention comprises: mirror-image constant flow source 301, control circuit 302, biasing circuit 303, feedback circuit 304, output transistor P3 and the holding circuit 305 that powers on.Voltage regulator 300 is to be used for seeing through its output terminal 30 stable and reliable output voltage V R is provided the (not shown) to another circuit or system.

Mirror-image constant flow source 301 comprises a PMOS transistor P1 and the 2nd PMOS transistor P2; The one PMOS transistor P1 and the 2nd PMOS transistor P2 source electrode all are connected to supply voltage VDD; The one PMOS transistor P1 grid leak interconnection back is connected with the 2nd PMOS transistor P2 grid; Two PMOS transistor drains all are connected to control circuit 302, and while the 2nd PMOS transistor drain also lotus root is connected to output transistor P3 control end; Control circuit 302 and mirror-image constant flow source 301, it comprises first input end, second input end and output terminal, and first input end is used to receive reference voltage VREF; Second input end is used to receive feedback voltage FB, and the output terminal lotus root is connected to the control end of output transistor P3, specifically; Control circuit 302 comprises the first nmos pass transistor N1 and the second nmos pass transistor N2; Wherein, the first nmos pass transistor N1 grid meets feedback voltage FB, and drain electrode links to each other with PMOS transistor P1 drain electrode; Source electrode links to each other with power on holding circuit 305 and biasing circuit 303; The second nmos pass transistor N2 grid meets reference voltage VREF, and drain electrode links to each other with the control end of the 2nd PMOS transistor P2 drain electrode and output transistor P3, and source electrode links to each other with power on holding circuit 305 and biasing circuit 303; Biasing circuit 303 all is connected with the first nmos pass transistor N1, the second nmos pass transistor source electrode, and in preferred embodiment of the present invention, biasing circuit 303 is a bias current sources Ibias; Feedback circuit 304 comprises first resistance R 1 and second resistance R 2, and resistance R 1 is connected in series to form voltage feedback circuit with R2, and the output voltage V R to voltage regulator carries out dividing potential drop to produce feedback voltage FB by this; Output transistor P3 is the 3rd PMOS transistor, and its grid is a control end, and source electrode meets supply voltage VDD, and R is to subsequent conditioning circuit for drain electrode output output voltage V; The holding circuit that powers on 305 is connected in control circuit 302 with biasing circuit 302; Be used to make voltage regulator 300 during powering on, to be output as 0, thereby the protection subsequent conditioning circuit is heavy in preferred embodiment of the present invention; The holding circuit that powers on 305 comprises the 4th PMOS transistor P4; The 4th PMOS transistor P4 grid meets reference voltage VREF, and source electrode all is connected grounded drain with the first nmos pass transistor N1, the second nmos pass transistor source electrode.

Fig. 4 is the sequential chart of preferred embodiment of the present invention; Below will cooperate Fig. 4 further to introduce and be the present invention's principle of work: Ibias sets up as yet when powering on, and VREF is low at this moment, causes the first nmos pass transistor N1, the second nmos pass transistor N2 all obstructed; The 4th PMOS transistor P4 conducting; If the dividing potential drop (being feedback voltage FB) of output voltage V R makes the nmos pass transistor N1 conducting of winning, a then PMOS transistor P1 conducting, P1-N1, P2 form mirror image; Thereby the 2nd PMOS transistor P2 conducting but the second nmos pass transistor N2 is obstructed; Supply voltage VDD adds to the grid level of output transistor P3 through the 2nd PMOS transistor P2, thereby output transistor P3 can not conducting, and its drain voltage is that the output voltage V R of voltage regulator is output as zero like this; After powering on, Ibias and VREF are all normal, and P4 will be in off state, thereby the N2 drain voltage is kept reasonable value; Thereby make P3 form a variable resistor, when VR raise, then feedback voltage FB raise, thereby the N1 grid voltage raises; For keeping Ibias inconvenience, the Vgs of N1 increases, and the Vgs of N2 descends, and equivalence is that the resistance of N2 becomes big; And electric current is constant, and then the drain voltage of N2 is that the grid voltage of P3 raises, thereby the P3 conducting dies down VR is descended, and VR just can be stabilized in setting value VRV like this.

In sum; The voltage regulator that the present invention is a kind of to have a defencive function that powers on forms path through increasing by the holding circuit that powers on when powering on, to make mirror-image constant flow source, control circuit and to power between the holding circuit; Reached and during powering on, made voltage regulator be output as zero purpose; Thereby protected subsequent conditioning circuit, solved the problem that voltage regulator during powering in the prior art does not have operate as normal.

The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, rights protection scope of the present invention should be listed like claims.

Claims

1. voltage regulator with the defencive function that powers on; Comprise mirror-image constant flow source, control circuit, biasing circuit, feedback circuit and output transistor; It is characterized in that: this voltage regulator also comprises the holding circuit that powers on, and this power on holding circuit and this biasing circuit are connected in parallel in this control circuit, with reference voltage when powering on not between stationary phase; This mirror-image constant flow source, this control circuit and this are powered on form path between the holding circuit, make this voltage regulator be output as zero.

2. the voltage regulator with the defencive function that powers on as claimed in claim 1 is characterized in that: this holding circuit that powers on comprises the 4th PMOS transistor, and the 4th PMOS transistor gate connects reference voltage, and source electrode is connected to this control circuit, grounded drain.

3. the voltage regulator with the defencive function that powers on as claimed in claim 2; It is characterized in that: this mirror-image constant flow source comprises a PMOS transistor AND gate the 2nd PMOS transistor; The one PMOS transistor AND gate the 2nd PMOS transistor source all is connected to supply voltage; The one PMOS transistor grid leak interconnection back is connected with the 2nd PMOS transistor gate, and two PMOS transistor drains all are connected to this control circuit, simultaneously the 2nd PMOS transistor drain also lotus root be connected to this output transistor gates.

4. the voltage regulator with the defencive function that powers on as claimed in claim 3; It is characterized in that: this control circuit comprises first nmos pass transistor and second nmos pass transistor; This first nmos pass transistor grid connects the feedback voltage of this feedback circuit output; Drain electrode links to each other with a PMOS transistor drain, and source electrode links to each other with the 4th PMOS transistor source and this biasing circuit, and this second nmos pass transistor grid connects reference voltage; Drain electrode links to each other with the 2nd PMOS transistor drain and this output transistor gates, and source electrode links to each other with the 4th PMOS transistor source and this biasing circuit.

5. the voltage regulator with the defencive function that powers on as claimed in claim 4; It is characterized in that: this feedback circuit comprises first resistance and second resistance; This first resistance and this second resistance string are connected between drain electrode of this output transistor and the ground, among this first resistance and this second resistance between node export this feedback voltage.

6. the voltage regulator with the defencive function that powers on as claimed in claim 1 is characterized in that: this biasing circuit is a bias current sources.

7. the voltage regulator with the defencive function that powers on as claimed in claim 1 is characterized in that: this output transistor is the PMOS transistor.