CN102436525B - Method for automatically repairing hold time violation in multi-node parallel mode in integrated circuit designing process - Google Patents
Method for automatically repairing hold time violation in multi-node parallel mode in integrated circuit designing process Download PDFInfo
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- CN102436525B CN102436525B CN201110332101.5A CN201110332101A CN102436525B CN 102436525 B CN102436525 B CN 102436525B CN 201110332101 A CN201110332101 A CN 201110332101A CN 102436525 B CN102436525 B CN 102436525B
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Abstract
The invention discloses a method for automatically repairing hold time violation in multi-node parallel mode in an integrated circuit designing process. The method includes 1 building time margin value according to nodes in all groups formed by extracted nodes and summarizing the time value to a list in descending order; 2 judging whether the list is empty; 3 setting the first element of the list as an operation object; 4 inspecting all elements behind the operation objects in the list sequentially and eliminating elements relevant to the operation objects; 5 repeating step 4 till all elements in the list do not have relevance; 6 judging types of groups in the list so as to revise value of nodes in the groups; 7 inserting buffer units at the positions of corresponding nodes according to the value of the elements in the list; and 8 selecting whether to do next round of hold time violation repairing. Due to integral analysis of the whole circuit, the buffer units can be inserted parallelly and efficiently to repair hold time violation, a period of repairing the hold time violation in the integrated circuit designing process is greatly shortened, and accordingly a designing period is shortened.
Description
Technical field
The invention belongs to VLSI (very large scale integrated circuit) designs, manufacturing technology field, in especially a kind of integrated circuit (IC) design process, multi-node parallel is repaired the method that the retention time breaks rules automatically.
Background technology
In modern large scale integrated circuit design process, automatic placement and routing's instrument can trial initiatively be repaired retention time fault.But in the high frequency large scale integrated circuit design of complicated clock zone, existing instrument is limited in one's ability for repairing in automatic placement and routing's process in the processing that the retention time breaks rules.Generally, need a large amount of manpowers to do long-time repair repeatedly, what this work meeting was considerable expends the chip design output cycle.
The method of repairing manually retention time fault also can be used in modern large scale integrated circuit design process, but the prerequisite of launching this work is circuit clock territory, and number comparatively simple and that the retention time breaks rules is not a lot of situation, and artificial repair often can only be analyzed reparation one by one to the retention time path that breaks rules.When circuit clock territory is comparatively complicated, the workload of manually repairing retention time fault will double.
Summary of the invention
The object of the invention is to overcome the shortcoming of above-mentioned prior art, provide multi-node parallel in a kind of integrated circuit (IC) design process automatically to repair the method that the retention time breaks rules, the method can break rules the automatic paralleling efficient reparation retention time, can shorten the cycle that in large scale integrated circuit design process, the retention time repairs, thereby shorten the chip design cycle.
The object of the invention is to solve by the following technical programs:
In integrated circuit (IC) design process, multi-node parallel is repaired the method that the retention time breaks rules automatically, it is characterized in that, comprises the following steps:
1) for each, have the timing path that the retention time breaks rules, two nodes that extract its of nargin maximum form a group Time Created, by all groups, by descending the gathering of summation of group interior nodes margin value Time Created, are a list;
2) whether the list that in judgement, step produces is empty; In this way, report circuit holding time fault unrepairable, as otherwise carry out next step;
3) first element of setting list is operand
4) investigate successively all elements after operand in list, remove all elements relevant to operand, described relevant, refer in two elements, have node belong to altogether a certain Time Created path, rearrange list, setting next element is operand;
5) repeating step 4), until all list elements do not possess correlativity;
6) two nodes that in report list, each element comprises are made as node A and Node B, and corresponding time margin value is t
aand t
b, by under common Time Created path Time Created nargin maximal value be made as t
cOM, according to t
a, t
band t
cOMthe type of magnitude relationship judgement list element, according to the value of node in the type revision list element of list element, the value of upgrading all elements also arranges list;
7) according to the value of element in list, at corresponding group interior nodes place, insert buffer cell;
8) select whether to do the retention time fault reparation of next round; In this way, the time sequence information of refresh circuit; As otherwise the report retention time break rules to repair complete.
In the above step 1) in: the path that all retention times break rules first listed; Then analyze one by one nargin Time Created of the relevant pin node of each many input blocks on every retention time fault timing path; Two values and the interdependent node that finally take out nargin maximum Time Created on every retention time fault timing path, form a group, according to the summation of group interior nodes margin value Time Created, by each descending gathering of group, is a list.
Further, above-mentioned steps 4) specifically according to following steps, carry out:
In S41, setting list, first group, for investigating object, as list only has a group, directly turns to S45 step;
S42, check to investigate object and whether have node to belong to same Time Created of path in next group thereafter: in this way, described in deleting from list next group thereafter; As no, described in reservation next group thereafter;
S43, repetition S42 are until complete other correlativity inspections of all groups in investigation object and list;
S44, setting list next node, for investigating object, as it is last group of list, directly turn to S45, otherwise turn to S42;
The type of S45, preparation judgement group is to do the adjustment of group internal segment point value.
Further, above-mentioned steps 6) specifically according to following steps, carry out:
S61, according to t
a, t
band t
cOMthe type of magnitude relationship judgement list element:
If t
abe not equal to t
b, and t
aand t
bvalue be all less than t
cOM, again and t
awith t
band be greater than t
cOM, this group belongs to Class1;
If t
abe not equal to t
b, and t
aand t
bvalue be all less than t
cOM, again and t
awith t
band be less than t
cOM, this group belongs to type 2;
If t
bequal t
cOM, and both values are all greater than t
a, this group belongs to type 3;
If t
aequal t
cOM, and both values are all greater than t
b, this group belongs to type 4;
If three's value is equal, this group belongs to type 5;
S62, according to group type, the value of correction group interior nodes, establishing revised value is T
awith T
b:
If group, for Class1, has T
a=t
a, T
b=t
cOM-t
a;
If group, for type 2, has T
a=t
a, T
b=t
b;
If group, for type 3, has T
a=t
a, T
b=t
b-t
a;
If group, for type 4, has T
a=t
a-t
b, T
b=t
b;
If group, for type 5, has T
a=t
a, T
b=0;
S63, arrangement list.
Further, above step 7) be specially:
S71, according to the selected suitable buffer cell of nodal information;
The delay time parameter of S72, investigation buffer cell;
S73, by organizing the time parameter of value corresponding to interior nodes divided by buffer cell in list, business's value is rounded to preservation;
S74, according to the numerical value after the rounding of business, at corresponding circuit node place, insert buffer cell.
In above step S73, when business's value is rounded, only house does not enter.
The present invention has following beneficial effect:
The present invention, by the holistic approach to whole circuit, can walk abreast, insert efficiently buffer cell and break rules to repair the retention time.With respect to existing single path, analyze one by one the method that the retention time breaks rules of repairing, method provided by the invention can greatly shorten the cycle that in large scale integrated circuit design process, the retention time repairs, thereby shortens the chip design cycle.
Accompanying drawing explanation
Fig. 1 is detail flowchart of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail:
Referring to Fig. 1, the method that the automatic reparation retention time of the present invention breaks rules, comprises the following steps:
1) for each, there is the timing path of retention time fault, extracting two maximum nodes of its nargin Time Created (setup time margin) and form a group, is a list by all groups by descending the gathering of summation of group interior nodes margin value Time Created;
In this step, as shown in Figure 1, first to list the path that all retention times break rules; Then analyze one by one nargin Time Created of the relevant pin node of each many input blocks on every retention time fault timing path; Maximum two values and the interdependent node that finally take out nargin Time Created on every retention time fault timing path form a group, by all groups, by descending the gathering of summation of group interior nodes margin value Time Created, are a list;
2) whether the list that in judgement, step produces is empty; In this way, report circuit holding time fault unrepairable, as otherwise carry out next step;
3) first element of setting list is operand
4) investigate successively all elements after operand in list, remove all elements to operand ' relevant ', described ' being correlated with ', refer in two elements and have node to belong to altogether a certain path Time Created (setup time path), also can be referred to as to have correlativity; Rearrange list, setting next element is operand;
5) repeating step 4), until all list elements do not possess correlativity, as shown in table 1 for certain circuit employing the present invention repairs in retention time fault process automatically, the results list after list element decorrelation;
Table 1:
6) (establish node A and Node B, corresponding value is t to two nodes that in report list, each element (i.e. group) comprises
aand t
b) under common Time Created path Time Created nargin maximal value (be made as t
cOM), according to t
a, t
band t
cOMthe type (has 5 types, rear detailed description) of magnitude relationship judgement list element, according to the value of node in the type revision list element of list element, the value of upgrading all elements also arranges list; As shown in table 2 for certain circuit employing the present invention repairs in retention time fault process automatically, report t
a, t
band t
cOMthe results list;
Table 2:
As shown in table 3 for certain circuit employing the present invention repairs in retention time fault process automatically, the results list in correction list element after the value of node;
Table 3:
7) according to the value of element in list, at corresponding Nodes, insert buffer cell (buffer), specifically according to following steps, carry out:
S71, according to the selected suitable buffer cell of nodal information;
The delay time parameter of S72, investigation buffer cell;
S73, will in list, organize the time parameter of value corresponding to interior nodes divided by buffer cell, business's value is rounded to preservation (when business's value is rounded, only house does not enter);
S74, according to the numerical value after the rounding of business, at corresponding circuit node place, insert buffer cell.
As shown in table 4 for certain circuit employing the present invention repairs in retention time fault process automatically, according to list element, insert the results list of buffer cell:
Table 4:
8) select whether to do the retention time fault reparation of next round; In this way, the time sequence information of refresh circuit; As otherwise the report retention time break rules to repair complete.
For above for removing the step 4 of correlativity), be below elaborated:
Referring to Fig. 1, the concrete implementation step of above step 4 is as follows:
In S41, setting list, first node, for investigating object, as list only has a group, directly turns to S45 step;
S42, check to investigate object and whether have node to belong to same Time Created of path in next group thereafter: in this way, described in deleting from list next group thereafter; As no, described in reservation next group thereafter;
S43, repetition S42 are until complete the correlativity inspection of investigating other all nodes in object and list;
S44, setting list next node, for investigating object, as it is last node of list, directly turn to S45, otherwise turn to S42;
The type of S45, preparation judgement group is worth adjusting to do group interior nodes.
Step 6 for the type of above judgement group and the value of correction group interior nodes), below elaborate:
(establish node A and Node B, corresponding value is t to two nodes that in S61, report list, each element (i.e. group) comprises
aand t
b) under common Time Created path Time Created nargin maximal value (be made as t
cOM);
S62, according to t
a, t
band t
cOMthe type of magnitude relationship judgement list element:
If t
abe not equal to t
b, and t
aand t
bvalue be all less than t
cOM, again and t
awith t
band be greater than t
cOM, this group belongs to Class1;
If t
abe not equal to t
b, and t
aand t
bvalue be all less than t
cOM, again and t
awith t
band be less than t
cOM, this group belongs to type 2;
If t
bequal t
cOM, and both values are all greater than t
a, this group belongs to type 3;
If t
aequal t
cOM, and both values are all greater than t
b, this group belongs to type 4;
If three's value is equal, this group belongs to type 5;
S63, according to group type, the value of correction group interior nodes, establishing revised value is T
awith T
b:
If group, for Class1, has T
a=t
a, T
b=t
cOM-t
a;
If group, for type 2, has T
a=t
a, T
b=t
b;
If group, for type 3, has T
a=t
a, T
b=t
b-t
a;
If group, for type 4, has T
a=t
a-t
b, T
b=t
b;
If group, for type 5, has T
a=t
a, T
b=0;
S64, arrangement list;
In sum, the present invention, by the holistic approach to whole circuit, can walk abreast, insert efficiently buffer cell and break rules to repair the retention time.With respect to existing single path, analyze one by one the method that the retention time breaks rules of repairing, the method can be reduced the cycle of repairing retention time fault in integrated circuit (IC) design process greatly, thereby shortens the design cycle.
Claims (4)
1. in integrated circuit (IC) design process, multi-node parallel is repaired the method that the retention time breaks rules automatically, it is characterized in that, comprises the following steps:
1) for each, have the timing path that the retention time breaks rules, two nodes that extract its of nargin maximum form a group Time Created, by all groups, by descending the gathering of summation of group interior nodes margin value Time Created, are a list;
2) whether the list that in judgement, step produces is empty; In this way, report circuit holding time fault unrepairable, as no, carry out next step;
3) first element of setting list is operand;
4) investigate successively all elements after operand in list, remove all elements relevant to operand, described relevant, refer in two elements, have node belong to altogether a certain Time Created path, rearrange list, setting next element is operand;
5) repeating step 4), until all list elements do not possess correlativity;
6) two nodes that in report list, each element comprises are made as node A and Node B, and corresponding time margin value is t
aand t
b, by under common Time Created path Time Created nargin maximal value be made as t
cOM, according to t
a, t
band t
cOMthe type of magnitude relationship judgement list element, according to the value of node in the type revision list element of list element, the value of upgrading all elements also arranges list;
7) according to the value of element in list corresponding Nodes in group, insert buffer cell;
8) select whether to do the retention time fault reparation of next round; In this way, the time sequence information of refresh circuit; As no, report that retention time fault reparation is complete;
Step 4) specifically according to following steps, carry out:
In S41, setting list, first group, for investigating object, as list only has a group, directly turns to S45 step;
S42, check to investigate object and whether have node to belong to same Time Created of path in next group thereafter: in this way, described in deleting from list next group thereafter; As no, described in reservation next group thereafter;
S43, repetition S42 are until complete other correlativity inspections of all groups in investigation object and list;
S44, the next group of setting list, for investigating object, as it is last group of list, directly turn to S45, otherwise turn to S42;
The type of S45, preparation judgement group is to do the adjustment of group internal segment point value;
Step 6) be specially:
S61, according to t
a, t
band t
cOMthe type of magnitude relationship judgement list element:
If t
abe not equal to t
b, and t
aand t
bvalue be all less than t
cOM, again and t
awith t
band be greater than t
cOM, this group belongs to Class1;
If t
abe not equal to t
b, and t
aand t
bvalue be all less than t
cOM, again and t
awith t
band be less than t
cOM, this group belongs to type 2;
If t
bequal t
cOM, and both values are all greater than t
a, this group belongs to type 3;
If t
aequal t
cOM, and both values are all greater than t
b, this group belongs to type 4;
If three's value is equal, this group belongs to type 5;
S62, according to group type, the value of correction group interior nodes, establishing revised value is T
awith T
b:
If group, for Class1, has T
a=t
a, T
b=t
cOM-t
a;
If group, for type 2, has T
a=t
a, T
b=t
b;
If group, for type 3, has T
a=t
a, T
b=t
b-t
a;
If group, for type 4, has T
a=t
a-t
b, T
b=t
b;
If group, for type 5, has T
a=t
a, T
b=0;
S63, arrangement list.
2. in integrated circuit (IC) design process according to claim 1, multi-node parallel is repaired the method that the retention time breaks rules automatically, it is characterized in that, in described step 1) in: the path that all retention times break rules first listed; Then analyze one by one nargin Time Created of the relevant pin node of each many input blocks on every retention time fault timing path; Two values and the interdependent node that finally take out nargin maximum Time Created on every retention time fault timing path, form a group, according to the summation of group interior nodes margin value Time Created, by each descending gathering of group, is a list.
3. in integrated circuit (IC) design process according to claim 1, multi-node parallel is repaired the method that the retention time breaks rules automatically, it is characterized in that step 7) be specially:
S71, according to the selected buffer cell of group interior nodes information;
The delay time parameter of S72, investigation buffer cell;
S73, by organizing the time parameter of value corresponding to interior nodes divided by buffer cell in list, business's value is rounded to preservation;
S74, according to the numerical value after the rounding of business, at corresponding circuit node place, insert buffer cell.
4. in integrated circuit (IC) design process according to claim 3, multi-node parallel is repaired the method that the retention time breaks rules automatically, it is characterized in that, in S73, when business's value is rounded, only house does not enter.
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|---|---|---|---|
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|---|---|---|---|
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| CN102436525B true CN102436525B (en) | 2014-10-15 |
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| CN107330177B (en) * | 2017-06-26 | 2020-03-20 | 北方电子研究院安徽有限公司 | Clock tree fan-out default repairing method based on Tcl/Tk script |
| CN112069763B (en) * | 2020-09-29 | 2022-11-29 | 上海兆芯集成电路有限公司 | Method for correcting circuit |
| CN112364584B (en) * | 2021-01-13 | 2021-03-23 | 南京集成电路设计服务产业创新中心有限公司 | Static time sequence analysis method based on distribution |
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2011
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Address after: 710075 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee before: Xi'an Sinochip Semiconductors Co., Ltd. |