CN102420877A - Multi-mode high-speed intelligent asynchronous serial port communication module and realizing method thereof - Google Patents
Multi-mode high-speed intelligent asynchronous serial port communication module and realizing method thereof Download PDFInfo
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Abstract
The invention discloses a multi-mode high-speed intelligent asynchronous serial port communication module and a realizing method thereof. A hardware architecture based by the multi-mode high-speed intelligent asynchronous serial port communication module is a CPCI (compact peripheral component interconnect) bus module. Hardware of the CPCI bus module comprises a programmable logic unit, a mass storage module, a general asynchronous receiving and transmitting controller, a high-speed digital isolator and an interface level switch device and the like. The invention has the advantages that: 1, an intelligent mode and a non-intelligent mode can be selected through software according to actual demands of a user; 2, when the multi-mode high-speed intelligent asynchronous serial port communication module is in the intelligent mode, data frame formats of all serial ports can be flexibly set through the software; and 3, when the multi-mode high-speed intelligent asynchronous serial port communication module is in the non-intelligent mode, the multi-mode high-speed intelligent asynchronous serial port communication module automatically judges data frame begins, data length, check, frame ends, and other information according to the set data frame formats during receiving the data.
Description
Technical field
The invention belongs to the communication interface technique field, be based on the method that hardware logic is realized multi-mode high-speed intelligent asynchronous serial communication specifically.
Background technology
Serial communication is simple with it, reliability is high and the characteristics such as easy of programming occupy an important position in system's control and data communication always, and it not only not have to eliminate because of the progress in epoch, and is more and more perfect on specification on the contrary, and application also more and more widely.
But because the characteristics of serial communication: the exchanges data of universal asynchronous receiving-transmitting controller and host computer (CPU) is received and dispatched by byte; Be that the universal asynchronous receiving-transmitting controller receives that the message of 1 byte just sends an interrupt signal to CPU and informs that CPU fetches data; By correctness (the heading tail tag knowledge of CPU to data; Verification and etc.) judge and handle that so the serial ports transceive data is fast more, just many more in its unit interval to the interruption of CPU application.In General System, CPU wants network data toward contact, does figure demonstration and processing etc., has so just had a strong impact on the disposal ability of CPU, therefore also becomes the bottleneck of serial communication speed.
Utilize us for many years in the achievements and experiences in Computer Communications Interface field; The multi-mode high-speed intelligent asynchronous serial communication module based on the hardware logic realization of autonomous Design exploitation can work in intelligent mode through software setting and (through microprocessor on the plate data carried out discriminating processing; Only send to CPU to satisfactory data) and non intelligent pattern (traditional serial interface communication mode; Data are not dealt with; Receive that data just send CPU to, are come data are resolved by CPU), and support multiple serial communication protocol standard; Can under the situation that does not take cpu resource, improve serial communication speed, can satisfy the requirement of different field user asynchronous serial communication.
Summary of the invention
The object of the invention provides a kind of multi-mode high-speed intelligent asynchronous serial communication module and implementation method, to satisfy the requirement of different control system and data communication.
Hardware structure of the present invention is based on the intelligent asynchronous serial communication module of cpci bus, and this module hardware comprises programmable logic cells, big capacity storage, universal asynchronous receiving-transmitting controller, high-speed figure isolating device and interface level switching device.Described programmable logic cells is connected with CPU through cpci bus, and submits data and the data that issue that receive CPU to CPU; Described big capacity storage is connected with described programmable logic cells through the RAM interface, receives the temporary processing of data; Described universal asynchronous receiving-transmitting controller is connected with described programmable logic cells through local bus, and the transmitting-receiving that communicates data is handled; Described high-speed figure isolating device two ends are connected with described interface level switching device with described universal asynchronous receiving-transmitting controller respectively, communicate the transmission of signal; Described interface level switching device one end is connected through the RS232/RS485/RS422 interface with peripheral hardware, and the other end is connected with described high-speed figure isolating device, communicates the logic level transition and the transmission of signal.
Described programmable logic cells is a core part of the present invention; Its inner integrated embedded microprocessor and by the various functional modules of Verilog hardware description language design; The main exchanges data that realizes this plate and CPU is with exchanges data and all logic controls of this plate of universal asynchronous receiving-transmitting controller.The various functional modules of described Verilog hardware description language design comprise model selection register, interface mask register, serial data transceiver module, Frame receives identification module, data-moving module and CPCI changes local bus module etc.
A. described model selection register can be through writing the selection that different values realizes this plate intelligent mode and non intelligent pattern.
B. described interface mask register can be through writing interface standard (RS232, RS422, the RS485 etc.) selection that different values realizes each serial ports of this plate.
C. described serial data transceiver module judges at first that when receiving the universal asynchronous receiving-transmitting controller receives buffering area whether data are arranged, if having, then takes out a byte data and it is sent to the Frame identification module; Judge when sending sending flag bit sees whether the universal asynchronous receiving-transmitting controller allows to send, and then the data that will send among the FIFO is write universal asynchronous receiving-transmitting controller transmitter register if allow to send, and waits to be sent.
D. described Frame receives the Frame discriminating form that identification module can be provided with each serial ports, and they receive only the data that meet the data frame format of setting separately, and weed out the data of the data frame format that does not meet oneself.
E. described data-moving module is responsible for the data-moving that receives among the FIFO is kept in big capacity storage when receiving; And whether the inquiry dual port RAM is in the state of can writing and residual memory space whether greater than the size of Frame; If meet the demands; The frame data that will be temporary in again in the said big capacity storage are moved in the dual port RAM, and send interrupt requests to CPU; When sending, receive the transmission interrupt requests of CPU after, the data that will send are transferred to inner FIFO fast from dual port RAM, and notice serial data transceiver module sends data.
F. described CPCI changes the local bus module and mainly converts cpci bus into local bus that this plate uses, to realize the exchanges data of CPU and this plate.
The implementation method of a kind of multi-mode high-speed intelligent of the present invention asynchronous serial communication module, comprise under device initialize setting, the intelligent mode that data transmit-receive is handled and non intelligent pattern under data transmit-receive handle.
(1) described device initialize setting comprises following content:
A. interface standard setting: RS232, RS422 or RS485.
B. the serial ports mode of operation is provided with: intelligent mode or non intelligent pattern.
C. if work for described intelligent mode, is then carried out the data frame format setting, comprising: heading, message trailer etc.
D. the serial ports parameter is provided with: comprise baud rate, data bit (5～8), check digit (odd, even parity check or no parity check position), position of rest (1,1.5 or 2) etc.
(2) described intelligent mode is the data frame transfer pattern with respect to CPU, and the reception flow process of its data may further comprise the steps shown in accompanying drawing 3:
Step 101: distant place equipment sends to certain serial ports with data flow; Described interface level transducer is the TTL signal with the transform electric of IEA232/IEA485/IEA422 communication; Be transferred to described universal asynchronous receiving-transmitting controller through described high-speed figure isolator, get into step 102;
Step 102: the serial data transceiver module in the programmable logic cells checks regularly whether the receiving register of said each serial ports of universal asynchronous receiving-transmitting controller has data, if having, then gets into step 103;
Step 103: the serial data transceiver module is read the byte data in the receiving register, and this byte data is sent to the Frame identification module, gets into step 104;
Step 104: the Frame identification module is differentiated the byte data of receiving according to the data frame format of initialization setting, if the requirement of data fit data frame format then gets into step 105; If do not meet, then get into step 106, lose this byte data and also other data of this frame that receive are before emptied from receive FIFO, come back to step 102;
Step 105: data are deposited in the reception FIFO of the inner corresponding serial ports of programmable logic cells, and get into step 107;
Step 107: judge in the described FIFO whether be complete frame data, if then get into step 108;
Step 108: these frame data are deposited in the described big capacity storage, get into step 109;
Step 109: the data-moving module judges whether the dual port RAM district that offers for this serial ports in the programmable logic cells is in the state of can writing and residual memory space whether greater than the size of Frame, if then get into step 110.If be not judged as not, then data exist in the big capacity storage;
Step 110: the data-moving module is transferred to data in the dual port RAM and to CPU in the big capacity storage and is sent a hardware interrupts request, gets into step 111;
After step 111:CPU receives interrupt requests, change the local bus module through CPCI these frame data are read in the CPU internal memory.
So far, a complete Frame receiving course just is through with.
The transmission flow of its data may further comprise the steps shown in accompanying drawing 4:
The frame data that step 201:CPU will send change the local bus module through CPCI and write certain serial ports dual port RAM district, and see one off for the data-moving module and send interrupt requests, get into step 202;
Step 202: the data-moving module is moved this serial ports transmission FIFO district with these frame data after receiving interrupt request singal fast in dual port RAM, get into step 203;
Step 203: whether the corresponding serial ports of serial data transceiver module inquiry universal asynchronous receiving-transmitting controller in the programmable logic cells is to allow transmit status, if then get into step 204;
Step 204: the serial data transceiver module is read byte data among the FIFO, and it is write universal asynchronous receiving-transmitting controller transmitter register, gets into step 205;
Step 205: the universal asynchronous receiving-transmitting controller with data conversion be serial data after high-speed figure isolating device and interface level switching device send to peripheral hardware, get into step 206;
Step 206: repeating step 203～step 205, all sent up to these frame data.
So far, a complete Frame process of transmitting just is through with.
(2) described non intelligent pattern is conventional serial interface communication mode; Be CPU through cpci bus directly and the universal asynchronous receiving-transmitting controller be the unit interaction data with the byte; This moment, described programmable logic cells inside had only CPCI to change the work of local bus module, and remaining element is not all worked.The reception flow process of its data may further comprise the steps shown in accompanying drawing 5:
Step 301: distant place equipment sends to certain serial ports with data flow; Described interface level transducer is the TTL signal with the transform electric of IEA232/IEA485/IEA422 communication; Be transferred to described universal asynchronous receiving-transmitting controller through described high-speed figure isolator, get into step 302;
Step 302: described universal asynchronous receiving-transmitting controller is received after the byte data it is deposited in the receiving register and to CPU and is sent a hardware interrupts request, gets into step 303;
Step 303:CPU reads this byte data through CPCI commentaries on classics local bus module after receiving interrupt requests, gets into step 304;
Whether step 304:CPU judgment data meets the message format requirement, if meet, then gets into step 305; If do not meet, then get into step 306, lose this byte data and also other data of this frame that receive are before emptied from internal memory, and return step 303;
Step 305:CPU gets into step 307 with this byte data write memory;
Step 307: repeating step 301～step 306 finishes receiving up to these frame data.
So far, a complete Frame receiving course just is through with.
The transmission flow of its data may further comprise the steps shown in accompanying drawing 6:
Step 401:CPU checks at first whether the corresponding serial ports of universal asynchronous receiving-transmitting controller is in the permission transmit status, if allow to send, then gets into step 402;
1 byte data that step 402:CPU will send writes universal asynchronous receiving-transmitting controller transmitter register, gets into step 403;
Step 403: the universal asynchronous receiving-transmitting controller with data conversion be serial data after high-speed figure isolating device and interface level switching device send to peripheral hardware, get into step 404;
Step 404: repeating step 401～step 403, all sent up to these frame data.
So far, a complete Frame process of transmitting just is through with.
The advantage of a kind of multi-mode high-speed intelligent of the present invention asynchronous serial communication module and implementation method is:
(1) can select intelligent mode and non intelligent pattern through software according to user's actual needs;
When (2) working in intelligent mode, the data frame format of each serial ports can be set through software flexible;
When (3) working in intelligent mode; When module receives data will according to the automatic judgment data frame head of setting of data frame format, data length, verification and, information such as postamble; Meet the data that set frame format if having, then data are put into buffering area and notified CPU; When module was sent data, CPU put into complete frame data that microprocessor sends data on buffering area and the notice board.When adopting this pattern, CPU is unit transmission data with the byte with the universal asynchronous receiving-transmitting controller no longer directly, but with plate on microprocessor communication, so transmission rate obtained raising greatly, the utilance of CPU also is improved;
When (4) working in intelligent mode; Because the data that receive can be temporary in the big capacity storage in described outside; Therefore can reach through the size that disposes big capacity storage in the system less demanding the serial data real-time; Send interruption perhaps by the requirement of CPU to CPU again after receiving the N frame data, meet the demands, just the phenomenon of data can not occur losing as long as receive buffer size in system's automatic query string mouth data during the free time.
Therefore, adopt the present invention program can satisfy the demand of different field user to asynchronous serial communication.
Description of drawings
Fig. 1 be the present invention based on the hardware principle block diagram.
Fig. 2 is a programmable logic cells internal logic block diagram provided by the invention.
Fig. 3 is that the Frame under the intelligent mode of the present invention receives flow chart.
Fig. 4 is the Frame transmission flow figure under the intelligent mode of the present invention.
Fig. 5 is that the Frame under the non intelligent pattern of the present invention receives flow chart.
Fig. 6 is the Frame transmission flow figure under the non intelligent pattern of the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention is elaborated.
Shown in accompanying drawing 1, the present invention based on hardware structure be the cpci bus module, this module hardware comprises programmable logic cells, big capacity storage, universal asynchronous receiving-transmitting controller, high-speed figure isolating device and interface level switching device etc.
Described programmable logic cells is the EP3C40 of altera corp or the XC5VLX30 of Xilinx company etc., mainly realizes the exchanges data of this plate and CPU, with exchanges data and all logic controls of this plate of universal asynchronous receiving-transmitting controller.
The K4S511632E that described big capacity storage is a Samsung company or the HY57V561620 of Hynix company etc.; It is as the extension storage district of described programmable logic cells; Being mainly each road serial ports provides configurable big capacity to receive buffering area, to satisfy the requirement of different system to the data throughput.
The ST16C554 that described universal asynchronous receiving-transmitting controller is an EXAR company or the TL16C754B of TI company etc.; Main realize between described interface level switching device and the described programmable logic cells string ← → and data transaction, and function such as control data transmission speed.
The ISO7221 that described high-speed figure isolating device is a TI company or the ADuM5241 of AD company etc.; The main electrical isolation that realizes between described universal asynchronous receiving-transmitting controller and the described interface level switching device can not damaged because of the outside transient high voltages that occurs under the extreme case to protect described universal asynchronous receiving-transmitting controller and built-in system.
The AD7306JRZ of the SP526 that described interface level switching device is a Sipex company, the MAX3088 of Maxim company or AD company etc. mainly realize level and the conversion of logical relation between the RS232/RS422/RS485 electric signal of external transmission and the TTL signal that the universal asynchronous receiving-transmitting controller can be discerned.
Shown in accompanying drawing 2; Core cell of the present invention is a programmable logic cells; Its inner integrated embedded microprocessor and by the various functional modules of Verilog hardware description language autonomous Design; Comprise that model selection register, interface mask register, serial data transceiver module, Frame receive identification module, data-moving module and CPCI commentaries on classics local bus module etc.; It mainly realizes the exchanges data of this plate and CPU, with exchanges data and all logic controls of this plate of universal asynchronous receiving-transmitting controller.The explanation of each functional module is following:
(1) model selection register can be through writing the selection that different values realizes this plate intelligent mode and non intelligent pattern to mode register;
(2) interface mask register can write interface standard (RS232, RS422, the RS485 etc.) selection that different values realizes each serial ports of this plate through the docking port mask register;
(3) serial data transceiver module, serial data transceiver module judge at first that when receiving the universal asynchronous receiving-transmitting controller receives buffering area whether data are arranged, if having, then take out a byte data and it is sent to the Frame identification module; Judge when sending sending flag bit sees whether the universal asynchronous receiving-transmitting controller allows to send, and then the data that will send among the FIFO is write universal asynchronous receiving-transmitting controller transmitter register if allow to send, and waits to be sent.
The serial data transceiver module has adopted the working method of poll when the reception of 8 serial ports being carried out data and transmission, promptly to sending data and receiving The data time-sharing mode.High workload baud rate 614400bps according to this module calculates, send or receive a byte data (by 10,1 start bit; 8 data bit; 1 position of rest) needs 16.3us, that is to say, the transmitter register of 8 road serial ports and the scanning of receiving register poll one time; And corresponding data are read out and the temporal summation that corresponding data write transmitter register can not could not had influence on the normal transmitting-receiving of data greater than 16.3us from receiving register.So, though in fact inner transmitting-receiving is under a kind of work in series pattern, to the communication between the serial ports of every road, still can regard the concurrent working mode as, the data communication between them is independent of each other.
(4) Frame receives identification module.When receiving data; Programmable logic cells can be screened data; Have 8 Frames that are made up of the Verilog hardware description language to receive identification module in the programmable logic cells, they work alone, and the Frame that each serial ports can be set is differentiated form; They receive only the data that meet the data frame format of setting separately, and weed out the data of the data frame format that does not meet oneself.When this Frame meets the requirements, just it is deposited in the reception FIFO of corresponding serial ports, after receiving a complete Frame, it is transferred to outside large-capacity data buffer area.For not losing of data, FIFO adopts ping-pong operation, promptly a serial port setting 2 receive FIFO; First frame data deposit FIFO1 in; And notification data moves module data taken out from FIFO1, and when fetching data, the next frame data will no longer write FIFO1; But deposit FIFO2 in, so just prevented that FIFO from not running through the situation that promptly writes and taking place.
(5) data-moving module.The data-moving module is responsible for the data-moving that receives among the FIFO is kept in big capacity storage when receiving; And whether the inquiry dual port RAM is in the state of can writing and residual memory space whether greater than the size of Frame; If meet the demands; The frame data that will be temporary in again in the said big capacity storage are moved in the dual port RAM, and send interrupt requests to CPU; When sending, receive the transmission interrupt requests of CPU after, the data that will send are transferred to inner FIFO fast from dual port RAM, and notice serial data transceiver module sends data.Do you why to data be transferred to FIFO from dual port RAM? Because it is very slow with respect to the speed that the past dual port RAM of CPU writes data that the universal asynchronous receiving-transmitting controller sends the speed of data; For a Frame to be sent; If the words that the serial data transceiver module directly fetches data from dual port RAM; Then it will occupy the control of dual port RAM for a long time, and forbid that CPU writes next frame data to be sent to dual port RAM, so just influence transmitting efficiency.So earlier data are moved FIFO fast, discharge the control of dual port RAM, so that CPU operates dual port RAM.
(6) CPCI changes the local bus module.Because cpci bus address wire and data wire are multiplexing; It can not be directly and universal asynchronous receiving-transmitting controller and big capacity storage etc. carry out exchanges data; So common CPCI expansion card all need use the PCI bridging chip, convert cpci bus into local bus that this plate uses.The present invention adopts programmable logic cells, realizes the function of PCI bridge with hardware description language.
Shown in accompanying drawing 3, described intelligent mode is the data frame transfer pattern with respect to CPU, and the reception flow process of its data may further comprise the steps:
Step 101: distant place equipment sends to certain serial ports with data flow; Described interface level transducer is the TTL signal with the transform electric of IEA232/IEA485/IEA422 communication; Be transferred to described universal asynchronous receiving-transmitting controller through described high-speed figure isolator, get into step 102;
Step 102: the serial data transceiver module in the programmable logic cells checks regularly whether the receiving register of said each serial ports of universal asynchronous receiving-transmitting controller has data, if having, then gets into step 103;
Step 103: the serial data transceiver module is read the byte data in the receiving register, and this byte data is sent to the Frame identification module, gets into step 104;
Step 104: the Frame identification module is differentiated the byte data of receiving according to the data frame format of initialization setting, if the requirement of data fit data frame format then gets into step 105; If do not meet, then get into step 106, lose this byte data and also other data of this frame that receive are before emptied from receive FIFO, come back to step 102;
Step 105: data are deposited in the reception FIFO of the inner corresponding serial ports of programmable logic cells, and get into step 107;
Step 107: judge in the described FIFO whether be complete frame data, if then get into step 108;
Step 108: these frame data are deposited in the described big capacity storage, get into step 109;
Step 109: the data-moving module judges whether the dual port RAM district that offers for this serial ports in the programmable logic cells is in the state of can writing and residual memory space whether greater than the size of Frame, if then get into step 110.If be not judged as not, then data exist in the big capacity storage;
Step 110: the data-moving module is transferred to data in the dual port RAM and to CPU in the big capacity storage and is sent a hardware interrupts request, gets into step 111;
After step 111:CPU receives interrupt requests, change the local bus module through CPCI these frame data are read in the CPU internal memory.
So far, a complete Frame receiving course just is through with.
Shown in accompanying drawing 4, the transmission flow of data may further comprise the steps under the intelligent mode:
The frame data that step 201:CPU will send change the local bus module through CPCI and write certain serial ports dual port RAM district, and see one off for the data-moving module and send interrupt requests, get into step 202;
Step 202: the data-moving module is moved this serial ports transmission FIFO district with these frame data after receiving interrupt request singal fast in dual port RAM, get into step 203;
Step 203: whether the corresponding serial ports of serial data transceiver module inquiry universal asynchronous receiving-transmitting controller in the programmable logic cells is to allow transmit status, if then get into step 204;
Step 204: the serial data transceiver module is read byte data among the FIFO, and it is write universal asynchronous receiving-transmitting controller transmitter register, gets into step 205;
Step 205: the universal asynchronous receiving-transmitting controller with data conversion be serial data after high-speed figure isolating device and interface level switching device send to peripheral hardware, get into step 206;
Step 206: repeating step 203～step 205, all sent up to these frame data.
So far, a complete Frame process of transmitting just is through with.
Shown in accompanying drawing 5; Described non intelligent pattern is conventional serial interface communication mode; Be that CPU is the unit interaction data with the byte with the universal asynchronous receiving-transmitting controller directly, this moment, described programmable logic cells inside had only the work of CPCI commentaries on classics local bus module, and remaining element is not all worked.The reception flow process of its data may further comprise the steps:
Step 301: distant place equipment sends to certain serial ports with data flow; Described interface level transducer is the TTL signal with the transform electric of IEA232/IEA485/IEA422 communication; Be transferred to described universal asynchronous receiving-transmitting controller through described high-speed figure isolator, get into step 302;
Step 302: described universal asynchronous receiving-transmitting controller is received after the byte data it is deposited in the receiving register and to CPU and is sent a hardware interrupts request, gets into step 303;
Step 303:CPU reads this byte data through CPCI commentaries on classics local bus module after receiving interrupt requests, gets into step 304;
Whether step 304:CPU judgment data meets the message format requirement, if meet, then gets into step 305; If do not meet, then get into step 306, lose this byte data and also other data of this frame that receive are before emptied from internal memory, and return step 303;
Step 305:CPU gets into step 307 with this byte data write memory;
Step 307: repeating step 301～step 306 finishes receiving up to these frame data.
So far, a complete Frame receiving course just is through with.
Shown in accompanying drawing 6, the transmission flow of data may further comprise the steps under the non intelligent pattern:
Step 401:CPU checks at first whether the corresponding serial ports of universal asynchronous receiving-transmitting controller is in the permission transmit status, if allow to send, then gets into step 402;
1 byte data that step 402:CPU will send writes universal asynchronous receiving-transmitting controller transmitter register, gets into step 403;
Step 403: the universal asynchronous receiving-transmitting controller with data conversion be serial data after high-speed figure isolating device and interface level switching device send to peripheral hardware, get into step 404;
Step 404: repeating step 401～step 403, all sent up to these frame data.
So far, a complete Frame process of transmitting just is through with.
Claims (3)
1. multi-mode high-speed intelligent asynchronous serial communication module; It is characterized in that: its hardware structure is based on the asynchronous serial communication module of cpci bus, and this module hardware comprises programmable logic cells, big capacity storage, universal asynchronous receiving-transmitting controller, high-speed figure isolating device and interface level switching device; Described programmable logic cells is connected with CPU through cpci bus, and submits data and the data that issue that receive CPU to CPU; Described big capacity storage is connected with described programmable logic cells through the RAM interface, receives the temporary processing of data; Described universal asynchronous receiving-transmitting controller is connected with described programmable logic cells through local bus, and the transmitting-receiving that communicates data is handled; Described high-speed figure isolating device two ends are connected with described interface level switching device with described universal asynchronous receiving-transmitting controller respectively, communicate the transmission of signal; Described interface level switching device one end is connected through the RS232/RS485/RS422 interface with peripheral hardware, and the other end is connected with described high-speed figure isolating device, communicates the logic level transition and the transmission of signal.
2. the described a kind of multi-mode high-speed intelligent asynchronous serial communication module of root a tree name claim 1; It is characterized in that: described programmable logic cells is the core part; Its inner integrated embedded microprocessor and by the various functional modules of Verilog hardware description language design, the various functional modules of described Verilog hardware description language design comprise: model selection register, interface mask register, serial data transceiver module, Frame receives identification module, data-moving module and CPCI changes the local bus module.
3. the implementation method of the described a kind of multi-mode high-speed intelligent asynchronous serial communication module of root a tree name claim 1 is characterized in that: this method comprise under device initialize setting, the intelligent mode that data transmit-receive is handled and non intelligent pattern under data transmit-receive handle;
Described device initialize setting comprises following content:
A. interface standard setting: RS232, RS422 or RS485;
B. the serial ports mode of operation is provided with: intelligent mode or non intelligent pattern;
C. if work for described intelligent mode, is then carried out the data frame format setting, comprising: heading, message trailer;
D. the serial ports parameter is provided with: comprise baud rate, data bit (5～8), check digit (odd, even parity check or no parity check position), position of rest (1,1.5 or 2);
Described intelligent mode is the data frame transfer pattern with respect to CPU, and the reception flow process of its data may further comprise the steps:
Step 101: distant place equipment sends to certain serial ports with data flow; Described interface level transducer is the TTL signal with the transform electric of IEA232/IEA485/IEA422 communication; Be transferred to described universal asynchronous receiving-transmitting controller through described high-speed figure isolator, get into step 102;
Step 102: the serial data transceiver module in the programmable logic cells checks regularly whether the receiving register of said each serial ports of universal asynchronous receiving-transmitting controller has data, if having, then gets into step 103;
Step 103: the serial data transceiver module is read the byte data in the receiving register, and this byte data is sent to the Frame identification module, gets into step 104;
Step 104: the Frame identification module is differentiated the byte data of receiving according to the data frame format of initialization setting, if the requirement of data fit data frame format then gets into step 105; If do not meet, then get into step 106, lose this byte data and also other data of this frame that receive are before emptied from receive FIFO, come back to step 102;
Step 105: data are deposited in the reception FIFO of the inner corresponding serial ports of programmable logic cells, and get into step 107;
Step 107: judge in the described FIFO whether be complete frame data, if then get into step 108;
Step 108: these frame data are deposited in the described big capacity storage, get into step 109;
Step 109: the data-moving module judges whether the dual port RAM district that offers for this serial ports in the programmable logic cells is in the state of can writing and residual memory space whether greater than the size of Frame, if then get into step 110; If be not judged as not, then data exist in the big capacity storage;
Step 110: the data-moving module is transferred to data in the dual port RAM and to CPU in the big capacity storage and is sent a hardware interrupts request, gets into step 111;
After step 111:CPU receives interrupt requests, change the local bus module through CPCI these frame data are read in the CPU internal memory;
The transmission flow of its data may further comprise the steps:
The frame data that step 201:CPU will send change the local bus module through CPCI and write certain serial ports dual port RAM district, and see one off for the data-moving module and send interrupt requests, get into step 202;
Step 202: the data-moving module is moved this serial ports transmission FIFO district with these frame data after receiving interrupt request singal fast in dual port RAM, get into step 203;
Step 203: whether the corresponding serial ports of serial data transceiver module inquiry universal asynchronous receiving-transmitting controller in the programmable logic cells is to allow transmit status, if then get into step 204;
Step 204: the serial data transceiver module is read byte data among the FIFO, and it is write universal asynchronous receiving-transmitting controller transmitter register, gets into step 205;
Step 205: the universal asynchronous receiving-transmitting controller with data conversion be serial data after high-speed figure isolating device and interface level switching device send to peripheral hardware, get into step 206;
Step 206: repeating step 203～step 205, all sent up to these frame data;
Described non intelligent pattern is conventional serial interface communication mode; Be CPU directly and the universal asynchronous receiving-transmitting controller be the unit interaction data with the byte; This moment, described programmable logic cells inside had only CPCI to change the work of local bus module, and remaining element is not all worked; The reception flow process of its data may further comprise the steps:
Step 301: distant place equipment sends to certain serial ports with data flow; Described interface level transducer is the TTL signal with the transform electric of IEA232/IEA485/IEA422 communication; Be transferred to described universal asynchronous receiving-transmitting controller through described high-speed figure isolator, get into step 302;
Step 302: described universal asynchronous receiving-transmitting controller is received after the byte data it is deposited in the receiving register and to CPU and is sent a hardware interrupts request, gets into step 303;
Step 303:CPU reads this byte data through CPCI commentaries on classics local bus module after receiving interrupt requests, gets into step 304;
Whether step 304:CPU judgment data meets the message format requirement, if meet, then gets into step 305; If do not meet, then get into step 306, lose this byte data and also other data of this frame that receive are before emptied from internal memory, and return step 303;
Step 305:CPU gets into step 307 with this byte data write memory;
Step 307: repeating step 301～step 306 finishes receiving up to these frame data;
The transmission flow of data may further comprise the steps under the non intelligent pattern:
Step 401:CPU checks at first whether the corresponding serial ports of universal asynchronous receiving-transmitting controller is in the permission transmit status, if allow to send, then gets into step 402;
1 byte data that step 402:CPU will send writes universal asynchronous receiving-transmitting controller transmitter register, gets into step 403;
Step 403: the universal asynchronous receiving-transmitting controller with data conversion be serial data after high-speed figure isolating device and interface level switching device send to peripheral hardware, get into step 404;
Step 404: repeating step 401～step 403, all sent up to these frame data.
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