CN104679702B - Multipath high-speed serial interface controller - Google Patents
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Abstract
The present invention relates to a kind of multipath high-speed serial interface controller, multipath high-speed serial interface controller includes front end high-speed universal serial bus, main body control logic and rear end multipath high-speed serial line interface；Rear end multipath high-speed serial line interface accesses front end high-speed universal serial bus by main body control logic.The invention provides a kind of HSSI High-Speed Serial Interface that general high-speed serial bus can be expanded to system custom protocol, improves message transmission rate, increases the multipath high-speed serial interface controller of Central Control Function.
Description
Technical field
The invention belongs to embedded data processing system, is related to a kind of interface controller, more particularly to a kind of multipath high-speed
Serial interface controller.
Background technology
With the continuous development of integrated avionics system, system is to the data exchange between each functional module in its inside
There are higher demand, traditional parallel bus with the speed and scale of data transfer（Such as VME, pci bus）Due to clock
The limitation of frequency and signal lead can not meet the needs of data transfer, so starting to use on a large scale between each module
High-speed serial bus carries out data transmission.Some general high-speed serial bus agreements, such as PCIE, RapidIO and ether
Net, although comparative maturity, the degree of standardization is high, and host-host protocol is also extremely complex, for some specific self-defined letters
The transmission application of single agreement is possible and improper, can lose a part of bandwidth on the contrary, is passed especially for some extensive multichannels
Defeated application, if using PCIE or RapidIO buses, corresponding STD bus network must be just built, using corresponding
Exchange chip, these all bring certain limitation to system design, also bring higher power consumption.So for aviation electricity
Increasing multichannel large-scale data transmission between each module in subsystem, traditional parallel bus and standard high speed serial are total
Line can not all meet to apply needs.
Xilinx companies from Virtex2Pro Series FPGAs product appearance after, Virtex4, Virtex5, Virtex6, with
And the newest serial V7 FPGA of cut-off both provide multipath high-speed serial transceiver, for realizing Ethernet interface, PCIE or
The high speed serial bus interface such as RapidIO.This high speed serialization transceiver can meet the high speed in integrated avionics system
Data transfer demands, while there is very big application flexibility.Both corresponding transmission rate can be realized according to system requirements,
Transmission line number, while hardware identification code can also be write according to demand to realize required self-defined host-host protocol.
The content of the invention
In order to solve above-mentioned technical problem present in background technology, the invention provides it is a kind of can be by general high speed
Extended serial-bus is the HSSI High-Speed Serial Interface of system custom protocol, improves message transmission rate, increases Central Control Function
Multipath high-speed serial interface controller.
The present invention technical solution be：The invention provides a kind of multipath high-speed serial interface controller, its is special
Part is：The multipath high-speed serial interface controller include front end high-speed universal serial bus, main body control logic and
Rear end multipath high-speed serial line interface；The rear end multipath high-speed serial line interface accesses front end universal high speed by main body control logic
Universal serial bus.
Above-mentioned multipath high-speed serial interface controller is also connected including rear end multipath high-speed serial line interface with external equipment
The high speed serialization transceiver connect.
Aforementioned body control logic includes front end local bus interface, the more ways corresponding with rear end local bus interface
According to buffer cell, configuration and transmitting-receiving control register group, interrupt fifo controller and rear end local bus interface；The rear end
Local bus interface accesses front end local bus interface by multichannel data buffer cell；The multichannel buffered data units are delayed
Rush state and access front end high-speed universal serial bus by interrupting fifo controller；The front end local bus interface leads to front end
It is connected with high-speed serial bus；The rear end local bus interface is connected with rear end multipath high-speed serial line interface.
Above-mentioned multipath high-speed serial line interface Zhong Mei roads HSSI High-Speed Serial Interface, which is provided with, to be sent data buffering RAM and connects
Receive data buffering RAM.
Above-mentioned multi-path serial controller is realized by FPGA.
Above-mentioned front end high-speed universal serial bus is entered to the conversion of front end local bus interface by corresponding IP Core
Row is realized.
Above-mentioned front end high-speed universal serial bus is PCI Express or RapidIO high-speed serial bus.
A kind of data transmission method for uplink based on multipath high-speed serial interface controller as described above, its special character exist
In：The data transmission method for uplink comprises the following steps：
1）The data that the pattern specified by user needs to send are written to by controller front end local bus interface will
The hardware of the rear end local bus interface of transmission is sent in buffering area；The pattern that the user specifies is interrupt mode or inquiry mould
Formula；
2）Hardware is sent the data in buffering area and is written to corresponding rear end HSSI High-Speed Serial Interface by main body control logic
In high speed serialization code coding transmitting element；
3）The coding transmitting element of rear end HSSI High-Speed Serial Interface receives the data received after data and encode concurrently
Send.
A kind of data receiver method based on multipath high-speed serial interface controller as described above, its special character exist
In：The data receiver method comprises the following steps：
1）After rear end HSSI High-Speed Serial Interface receives data and decoded, the interface of main body control logic is write data into
In corresponding hardware acceptance buffering area；
2）The state that main body control logic has data Hou Jianggai roads interface in hardware acceptance buffering area is provided with data
It is to be received, and send interrupt signal by interrupting fifo controller forward end local bus interface；
3）Judge current mode of operation, if mode of operation is to interrupt to receive, carry out step 4）；If mode of operation is to look into
Ask and receive, then carry out step 5）；
4）If being currently to interrupt to receive mode of operation, after receiving data interruption to be received, FIFO controls are interrupted in inquiry
Corresponding interrupt status register in device processed, the data received are then read from hardware buffer area, and write data into
In annular software buffering area, user application is then notified；User application call receive API from software buffering area most
The data received are obtained eventually；
5）If being currently inquire-receive mode of operation, the Status register of the continuous cyclic query controller of user application
Device, finding there are reception data to be read in hardware buffer area, then user application sends reception order to drive software, from
The data received are read in hardware buffer area, and are write data into annular software buffering area, user application is adjusted again
The data received are finally obtained from software buffering area with reception API.
The present invention develops a kind of control of multipath high-speed serial line interface using the FPGA with high speed serialization transceiver
Device, the front end of the controller still use the high-speed serial bus of standard（Such as PCIE or RapidIO）To be transmitted control,
Rear end can realize required various HSSI High-Speed Serial Interfaces according to demand, and by buffer RAM and interrupt poll FIFO mechanism
To ensure that each road HSSI High-Speed Serial Interface of rear end accesses the real-time of operation, the harmony of data communication bandwidth.Can be general
High-speed serial bus on expand the HSSI High-Speed Serial Interface of multichannel custom protocol needed for system, both met number in system
According to the needs of transmission, module design difficulty can be reduced again, reduces bandwidth loss, reduced power consumption, improved Embedded Application and open
The flexibility of hair, a kind of new architecture mode is provided for the design of embedded data processing system.Specifically, present invention tool
Have the advantage that：
1st, outside traditional high-speed universal serial bus switch network, a kind of new intermodule is developed all the way to multichannel
The data transfer mode of the HSSI High-Speed Serial Interface of control model, can be expanded on general high-speed serial bus multichannel other
HSSI High-Speed Serial Interface received and dispatched.This controller can extend application oriented customized height according to system requirements
Fast serial line interface, for relatively conventional high-speed universal serial bus switch network, module design difficulty can be reduced, improves number
According to transmission rate, functional circuit power consumption is reduced.
2nd, controller supports a variety of serial bus protocols, and using flexible, function expansibility is strong.Due to controller front end and
Rear end is realized as being easy to the local bus pattern of extension, and front end can expand to various general high-speed serial bus, even
It is that the local bus of processor is controlled；The port number of the HSSI High-Speed Serial Interface of rear end, host-host protocol, transmission rate are all
Realization can be extended according to demand, can also be realized the mixing application model of polytype bus, more can further be increased light
Electric transceiver is converted to optical-path interface, optical-fibre channel communication function is carried out between each functional module, so as to improving universal serial bus
Transmission range.This design pattern make it that controller flexibility is high, and applicable scene is very extensive.
3rd, the interruption poll FIFO mechanism of each road HSSI High-Speed Serial Interface is realized in controller, it is ensured that every road interface of rear end
Data transmit-receive can be handled with identical priority by front end high-speed bus, certain road HSSI High-Speed Serial Interface will not occur
The situation of controller is taken for a long time, while realizes that a large amount of RAM are used as the transmitting-receiving of each road HSSI High-Speed Serial Interface and delayed in controller
Area is rushed, employs blocking and buffering technology, ensure that the stability of data transfer on HSSI High-Speed Serial Interface.
Brief description of the drawings
Fig. 1 is the structured flowchart of the present invention；
Fig. 2 is the hardware buffer area block management schematic diagram of the present invention；
Fig. 3 is the interruption FIFO mechanism principle figures of the present invention；
Fig. 4 is that the annular data of invention software driving design receives and dispatches buffering area fundamental diagram.
Embodiment
This controller is realized that the front end of controller uses on hardware using the FPGA of Xilinx companies for platform
The high-speed serial bus of standard/general controls the data transmit-receive of the multipath high-speed serial line interface of rear end；C languages are used on software
Speech writes driver, the channel management mode to multiplex communication interface using unified standard, by the various resources of communication interface
Standard device form is encapsulated as with information unification, there is provided unified API service, is easy to the calling of application program.
The front end of controller hardware using bridge function Programmable Analog Circuits, by the high speed serialization of standard/general
The general line system of bus or processor chips is local bus in the piece for being more easy to use in FPGA and extending, by Front Side Bus
Read-write operation be mapped as read-write operation on local bus, and support burst access modules to improve readwrite bandwidth.
The core of controller hardware is control logic, and control logic is used for the Front Side Bus and rear end multichannel for being connected controller
Interface, and realize transmit-receive function of the front end to rear end.Control logic all uses with Front Side Bus and being connected for back end interface
Local bus interface inside FPGA, to ensure the independence and isolation between each comprising modules.Control logic is using table tennis
The buffer management mechanism and interruption FIFO mechanism of formula are controlled to the multichannel interface of rear end, and the former can ensure the company of transmission
Continuous property and stability, the latter can ensure rear end each road interface can level be handled by Front Side Bus so that All factors being equal, preference will be give to.
If the rear end of controller hardware is the HSSI High-Speed Serial Interface of main line custom protocol, all it is encapsulated as per road back side bus
One independent design that control is written and read by local bus inside FPGA, is on the one hand easy to mutually hold in the mouth with the control logic of controller
Connect, it is on the other hand mutually independent with the other components of controller, it is easily modified and changes.
Three parts hardware composition part in FPGA to more than is realized and organic by local bus inside FPGA respectively
Ground combines, and is formed the hardware components of controller invention.
The drive software implementation of controller is：1. the channel management mode of unified standard is provided to user application
And API service, to be user-friendly.2. corresponding annular is safeguarded in internal memory for each HSSI High-Speed Serial Interface of controller rear end
Software buffering area, and segmentation buffer technology is taken to ensure the high bandwidth during controller transmitting-receiving.3. for the interruption of hardware
FIFO mechanism writes corresponding interrupt service routine, to make respective handling to the various events of each road interface of controller.4.
Hold inquiry transmitting-receiving and two kinds of mode of operations of interrupt reception and dispatch.5. the state of each HSSI High-Speed Serial Interface in pair rear end carry out unified monitoring and
Management, the criterion to carry out data transmission operation as user application.
Realize that the controller is invented through above software and hardware scheme.The workflow of the controller is as follows：
Send data procedures：
1st, user application calls the API of controller drive software, and the data that will be sent write annular software buffering
Area；
2nd, the pattern that drive software is specified automatically by user（Interrupt mode or query pattern）By in software buffering area
Data are written in the hardware buffer area for the back end interface to be sent by controller Front Side Bus；
3rd, the data in hardware buffer area are written to corresponding rear end automatically and gone here and there at a high speed by the control logic of controller hardware
In line interface；
4th, rear end HSSI High-Speed Serial Interface is encoded and sent after receiving data.
Receive data procedures：
1st, after rear end road HSSI High-Speed Serial Interface receives data and decoded, the interface of control logic is write data into
In corresponding hardware buffer area；
2nd, control logic obtains the state of data Hou Jianggai roads interface to be provided with data to be received, and by interrupting FIFO
Forward end bus sends interruption；
If the 3, drive software currently receives mode of operation to interrupt, drive software receives data interruption to be received
Afterwards, call and interrupt the corresponding interrupt status register of service-seeking, the data received are then read from hardware buffer area, and
Write data into annular software buffering area, then notify user application.User application, which calls, receives API from soft
The data received are finally obtained in part buffering area.
The 4th, if drive software is currently inquire-receive mode of operation, the continuous cyclic query controller of user application
Status register, find there are reception data to be read in hardware buffer area, then user application sends to drive software and connect
Order is received, drive software reads the data received from hardware buffer area, and writes data into annular software buffering area,
User application recalls reception API and the data received is finally obtained from software buffering area.
The present invention is described in further details below.
1. hardware design is realized
Multipath high-speed serial interface controller is realized that as shown in Figure 1, it is mainly formed overall structure in FPGA
For three following parts：
（1）The high-speed universal serial bus IP Core and read and write access functional module of front end；
（2）Main body control logic, realize transmitting-receiving control of the Front Side Bus to rear end multipath high-speed serial line interface；
（3）The multipath high-speed serial line interface of rear end and its corresponding high speed serialization transceiver.
Merogenesis describes in detail later for specific implementation per part.
The high-speed universal serial bus of 1.1 front ends
The high-speed universal serial bus of top is realized using corresponding IP Core in fig. 1, can basis
The demand of system is changed to enter row bus, can generally be come using 8x PCI Express buses or 4x RapidIO buses
Reach higher message transmission rate, or be used as the read-write bus of front end using the local bus of processor.Front end is general
High-speed serial bus can be any type of high-speed serial bus, at present usually using PCIE and Rapidio.
Read-write operation of the high-speed serial bus of front end between the front end local bus interface of control logic is supported
Burst transmission modes, therefore higher message transmission rate can be reached.
The multipath high-speed serial line interface of 1.2 rear ends
The multipath high-speed serial line interface of rear end, encapsulation also is designed using local bus interface, so convenient and control
The local bus interface of logic rear end processed is mutually connected, and encapsulation mode as use, can also be by the high speed serialization of rear end
The realization of interface is preferably kept apart with control logic, is easy to the modification and cutting of multipath high-speed serial line interface, extension personality
It is active preferable.
Because the HSSI High-Speed Serial Interface of rear end takes the encapsulation mode of local bus to be realized, so run thereon
The other parts that host-host protocol can also be customized according to the demand of system without influenceing whole controller.The present invention is specific
A kind of HSSI High-Speed Serial Interface agreement --- the Aurora agreements for having used Xilinx companies to provide when realizing, can also be according to demand
It is changed to other agreements.In addition, optoelectronic transceivers can be extended in high speed serialization transceiver rear end, you can extend optical fiber for module
Communication function.
The realization of 1.3 control logics
In control logic, in addition to being managed to the Link State of each road HSSI High-Speed Serial Interface and mode of operation, also
To be that each road interface realize that the respective buffer RAM that sends and receives is gone forward side by side row buffering management, further need exist for realizing a set of interruption
Mechanism, to ensure the event of each road HSSI High-Speed Serial Interface generation（Reception event is sent, offline event etc. on interface link）All may be used
To timely respond to handle by Front Side Bus, and will not block.Below to buffer management and the reality of interruption FIFO mechanism
Existing method is further described.
1.3.1 buffer management
Two RAM are all distributed per road HSSI High-Speed Serial Interface to come respectively as transmission buffered data area and receive data buffering
Area.Its principle framework is as shown in Figure 2.
It is two Block to send buffering area RAM to be divided to, and Front Side Bus writes data to be sent into two Block successively,
Rear end serial line interface is voluntarily read from two Block to be sent data and is transmitted.When thering are data not send out in two Block
Sending when finishing, Front Side Bus stops write-in and sends data, when the data in some Block are all taken away by rear end serial line interface,
Then forward end, which is sent, sends buffering area ready interrupt to allow Front Side Bus to write new data to be sent.This mechanism ensure that string
The data of line interface send and can be carried out continuously, and improve transmission bandwidth.
Receive buffering area RAM and be also classified into two Block, rear end serial line interface writes into two Block receive successively
The data arrived, Front Side Bus read the reception data cached from two Block successively.It is to be read when having in some Block
Data when, then forward end sends interruption to notify Front Side Bus to be read out.If Front Side Bus is not timely responded to or read
The speed of data receives the speed of data less than serial line interface, it may occur however that the number to be read such as has in two buffering Block
According to situation, now answer rear end serial line interface send receive the non-ready signal of buffering area it is not ready to allow serial line interface to switch to
State, pause receive, to reach the function of flow control.
1.3.2 interrupt FIFO mechanism
Because controller will manage multipath high-speed serial line interface, if using traditional polling mechanism, it is likely that occur
Certain road serial line interface takes the situation of whole controller for a long time, in order to avoid such case occurs, it is ensured that every road of rear end is high
Fast serial line interface can be conducted interviews with identical priority by Front Side Bus, be carried out in the present invention using FIFO mechanism is interrupted
Management, its schematic diagram are shown in accompanying drawing 3.
When multipath high-speed serial line interface has event to need to be handled, multiple bit are had in interrupt source register
For effective status, the administrative mechanism of writing for then interrupting FIFO can be by each effectively bit in interrupt source register separately as one
Individual input item, which is written to, interrupts in FIFO.Interrupt FIFO and export interruption, then Front Side Bus meeting to controller front end in not space-time
Only single effective interrupt status of bit, which is successively read, from interruption FIFO carries out corresponding interrupt processing one by one.This is just protected
The interrupt event demonstrate,proved on each road HSSI High-Speed Serial Interface in rear end can be handled successively with equivalent probability by Front Side Bus.
2. management of the controller drive software to multipath high-speed serial line interface
Channel management mode of the controller drivers design to multiplex communication interface using unified standard, by communication interface
Control register address, transmit/receive buffering area plot, transmit/receive buffer pool size, transmit/receive buffer pointer, mode of operation（Look into
Ask or interrupt）, interrupt resources information, and the resource such as system administration semaphore is uniformly encapsulated as standard device form, there is provided system
One API service, it is easy to the calling of application program.
In addition, the matter of utmost importance that high-speed bus software development faces is exactly the cache management for high band wide data.How
Ensure transmitting/receiving in real time, it is necessary to which interface driver software carefully analyzes the characteristic of bus, software and hardware of making rational planning for money for Large Volume Data
Source, such as bandwidth allocation, buffer pool size and quantity, interrupt control management, operational status information monitoring etc..Controller drive software
Main functional characteristics is as described below.
2.1 annular datas receive and dispatch cache management
Multipath serial bus controller design carries out transmitting/receiving management using soft and hardware level 2 buffering pattern to every road interface.
Illustrate in hardware data simulated acid rain such as prosthomere, using similar to ping-pong operation pattern.Software Cushioning Design uses circle queue
Realize the transmitting-receiving operation service between hardware logic interface and application software interface.The purpose of design of software buffering area is by interface
What hardware logic was completed transmits/receives operation, is peeled away as much as possible by the operation of calling interface service function with application program so that
Hardware logic is not influenceed by upper layer software (applications), maintains data to transmit/receive the continuity of operation, ensures the high bandwidth of universal serial bus
Energy.
The operation principle of loop data buffer is that hardware control logic is engaged with driving layer software interrupt service routine,
The data completed between hardware buffer data field and software annular buffer location are carried, and the tune of buffer circle pointer
It is whole, shown in its operation principle schematic diagram drawings described below 4.
The establishment of annular software buffering area is after device power, when carrying out interface initialization, retains in operating system and deposits
Apply in memory space.What is carried out simultaneously also has the initialization of pointer end to end of buffer circle, the configuration of buffer location size
Deng operation.
2.2 inquiry mode of operations
It is divided into non-obstruction with general interface drive program and blocks as two kinds of communication modes, it is usual interrupts communication modes
Corresponding non-obstruction communication modes, i.e. communication process are not required to take excessive system processing resources, and real-time is stronger；Inquire about mode of operation
Corresponding obstruction communication modes, i.e., in communication process, system also needs to detect the communication state of port, is carried out by corresponding conditionses next
Step operation.
In the case where inquiring about mode of operation, driver sends or connect simply by the working condition for judging hardware control logic
After receipts operating condition is ready（As hardware is sent, buffering area is empty, and hardware acceptance buffering area has the conditions such as data）, then carry out to hardware
Logic circuit sends and receives operation.
Because the driving of interface polls mode of operation is realized simply, but EBI bandwidth is relatively low, therefore the pattern is generally used for
In the case of hardware debugging and the checking of bus path.
The interrupt management mechanism of 2.3FIFO forms
It can ensure that multiple bus passage transmits according to time order and function sequential processes using the interrupt mechanism of form of FIFO to grasp
Make, the real-time of the communication of guarantee, make multichannel that there is equal priority.Multichannel polling mode is avoided by front-end processing, really
Guarantor will not occur certain road HSSI High-Speed Serial Interface and be transmitted occupancy controller for a long time, cause other passages to obtain and provided less than processing
Source, the situation that data buffering overflows.
Drive multichannel interface on layer Software for Design all only right using interruption multiplexing mechanism, the i.e. interrupt event of multi-channel interface
The interrupt source of the side of master port one is answered, therefore devises special interrupt control unit.Interrupt control unit is responsible for all bus
The interrupt event service management of interface, FIFO mechanism, which simplifies, interrupts service interface design, avoids the service wheel in interruption
Ask, ensure that each interruption equal priority service.Polymorphic type is also unified in this way, the serial line interface of multi-quantity is driving
Service form in dynamic program.
The monitoring and management of 2.4 Interface status
Affairs and event type on high-speed serial bus are more, determine the various states information of serial line interface, such as
Bus physical layer status information（Link presence, exception error etc.）, the full empty state of application layer interrupting information, buffering area etc.
Can be by interrupting or inquiry mode obtain by host-side interface, so as to realize the management of driving layer software Deng, information above
Control, and application program carry out data transmission the criterion of operation.
Controller drive software receives and dispatches cache management using annular data, supports the interruption mould of query pattern and form of FIFO
Two kinds of mode of operations of formula, and the monitoring and management of Interface status are provided.
Claims (6)
- A kind of 1. multipath high-speed serial interface controller, it is characterised in that：Before the multipath high-speed serial interface controller includes Hold high-speed universal serial bus, main body control logic and rear end multipath high-speed serial line interface；The rear end multipath high-speed is serial Interface accesses front end high-speed universal serial bus by main body control logic；The multipath high-speed serial interface controller also includes what rear end multipath high-speed serial line interface was attached with external equipment High speed serialization transceiver；The main body control logic includes front end local bus interface, the multichannel data corresponding with rear end local bus interface delays Rush unit, configuration and transmitting-receiving control register group, interrupt fifo controller and rear end local bus interface；The rear end is local EBI accesses front end local bus interface by multichannel data buffer cell；The buffering shape of the multichannel data buffer cell State accesses front end high-speed universal serial bus by interrupting fifo controller；The front end local bus interface and the general height in front end Fast universal serial bus is connected；The rear end local bus interface is connected with rear end multipath high-speed serial line interface；Multipath high-speed serial line interface Zhong Mei roads HSSI High-Speed Serial Interface, which is provided with, sends data buffering RAM and reception number According to buffer RAM；It is two Block that the transmission data buffering RAM, which is divided to, and front end high-speed universal serial bus is write into two Block successively Enter data to be sent, rear end multipath high-speed serial line interface is voluntarily read from two Block to be sent data and be transmitted；Receive data buffering RAM and be also classified into two Block, rear end multipath high-speed serial line interface is write into two Block successively Enter the data received, front end high-speed universal serial bus reads the reception data cached from two Block successively.
- 2. multipath high-speed serial interface controller according to claim 1, it is characterised in that：The multipath high-speed serial interface Mouth controller is realized by FPGA.
- 3. multipath high-speed serial interface controller according to claim 2, it is characterised in that：The front end universal high speed string Row bus are realized to the conversion of front end local bus interface by corresponding IP Core.
- 4. multipath high-speed serial interface controller according to claim 3, it is characterised in that：The front end universal high speed string Row bus are PCI Express or RapidIO high-speed serial bus.
- 5. a kind of data of multipath high-speed serial interface controller based on as described in claim 1-4 any claims are sent Method, it is characterised in that：The data transmission method for uplink comprises the following steps：1) data that the pattern specified by user needs to send are written to and sent by controller front end local bus interface Rear end local bus interface hardware send buffering area in；The pattern that the user specifies is interrupt mode or query pattern；2) data that hardware is sent in buffering area are written to the high speed of corresponding rear end HSSI High-Speed Serial Interface by main body control logic In serial code coding transmitting element；3) the coding transmitting element of rear end HSSI High-Speed Serial Interface receives the data received after data and is encoded and sent.
- A kind of 6. data receiver of the multipath high-speed serial interface controller based on as described in claim 1-4 any claims Method, it is characterised in that：The data receiver method comprises the following steps：1) after rear end HSSI High-Speed Serial Interface receives data and decoded, the interface for writing data into main body control logic is corresponding Hardware acceptance buffering area in；2) main body control logic has the state of data Hou Jianggai roads interface to be provided with data waiting in hardware acceptance buffering area Receive, and interrupt signal is sent by interrupting fifo controller forward end local bus interface；3) judge current mode of operation, if mode of operation is to interrupt to receive, carry out step 4)；Connect if mode of operation is inquiry Receive, then carry out step 5)；If 4) be currently to interrupt to receive mode of operation, after receiving data interruption to be received, fifo controller is interrupted in inquiry Interior corresponding interrupt status register, the data received are then read from hardware buffer area, and write data into annular In software buffering area, user application is then notified；User application calls reception API finally to be obtained from software buffering area The data that must be received；If 5) be currently inquire-receive mode of operation, the status register of the continuous cyclic query controller of user application, It was found that there is reception data to be read in hardware buffer area, then user application sends reception order to drive software, from hard The data received are read in part buffering area, and are write data into annular software buffering area, user application recalls Receive API and the data received are finally obtained from software buffering area.
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| CN105574242A (en) * | 2015-12-11 | 2016-05-11 | 中国航空工业集团公司西安航空计算技术研究所 | Communication interface and simulation application method based on same |
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| CN108650160B (en) * | 2018-04-26 | 2020-07-17 | 西安微电子技术研究所 | Bus bridge based on chain type port and working method thereof |
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