CN102281116B - Method and device for generating GOLD sequence - Google Patents
Method and device for generating GOLD sequence Download PDFInfo
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Abstract
The invention discloses a method for generating a GOLD sequence. The method comprises the following steps of: respectively storing 31 initial bit values of a sequence x1 and a sequence x2 by using two 31-level feedback shift registers; carrying out parallel computation on 31 bits in the sequence x1 in the feedback shift register at a time to obtain 28 follow-up bits of the sequence x1, and carrying out parallel computation on 31 bits of the sequence x2 in the feedback shift register to obtain 28 follow-up bits of the sequence x2; when the acquired length of the sequence x1 and the acquired length of the sequence x2 are more than or equal to NC bit, carrying out parallel xor on the sequence x1 with the digits not less than NC and the sequence x2 with the same digits with the sequence x1, which are stored in the shift registers, to generate corresponding c(n); and respectively storing the acquired high 31bits of the sequence x1 and the sequence x2 to the feedback shift register in sequence. Meanwhile, the invention also discloses a device for generating the GOLD sequence. According to the method and device for generating the GOLD sequence disclosed by the invention, the sequence x1, the sequence x2 and the sequence c(n) are subjected to 28-path parallel computation, and 28 GOLD sequence bits can be generated by one-step computation, therefore the time consumption in computing the GOLD sequence is reduced, and the computation speed of the GOLD sequence is improved.
Description
Technical field
The present invention relates to a kind of mobile communication system technology, it is related specifically in a kind of 3-G (Generation Three mobile communication system) raw
Become the method and device of gold scramble sequence.
Background technology
In mobile communication system it will usually two be entered what information source produced using pseudo-random sequence (referred to as, pn sequence)
Digital massage processed first scrambles, then is transmitted, and the purpose so processing is mainly:
1st, randomness realizes the encryption of communication channel；
The binary digit message that produce information source and the very long pseudo-random sequence exclusive-OR of a cycle, thus may be used
So that former message to be become impenetrable another sequence.Only primary sending could be recovered in receiving terminal using same pseudo-random sequence
Content.
2nd, spread-spectrum CDMA communication is realized according to orthogonality；
According to Shannon channel capacity formula, we can utilize the bandwidth of code expanding communication channel, reach Utopian
Channel capacity.If cross-correlation coefficient very little (nearly orthogonal) between the code resource being used, can achieve and use different orthogonal
Do not interfere with each other between the user of code, so can enable to send many signals in same frequency range simultaneously, realize code division
Multiple access communication.
3rd, disordering data sequence and descrambling
In digital communication system, the distance of swimming (continuous appearance 0 or 1) of continuous appearance 1 or 0 such as in prime information is excessive, then
Bit synchronous foundation will be affected and keep, the anti-interference in the case of this kind will be poor simultaneously.Easily form crosstalk.At this moment we are permissible
The sequence upset prime information sequence and form similar white noise statistical property is transmitted.
Wherein, described pseudo-random sequence has the fundamental characteristics similar to random sequences, is that one kind is seemingly random but actual
On be regular periodic binary sequence.In mobile communication system, the most frequently used pn sequence is greatest length liner code
Sequence (referred to as, m-sequence), is produced by linear feedback shift device, is characterized in thering is periodicity and pseudo-randomness.
Gold sequence is a kind of code sequence based on m-sequence, is usually used in the scrambling processes of mobile communication system, gold sequence
There is more excellent auto-correlation and cross correlation, the sequence number of generation is many.The autocorrelation of gold sequence is not so good as m-sequence, mutually
Dependency is better than m-sequence.
Method for scrambling in mobile communication system is, for each code word, bit stream
(whereinIt is the amount of bits of code word q of physical channel transmission in each subframe) and binary pseudo-random sequence cq
N () is scrambled, generate the bit after scrambling as the following formula
Wherein, n=0,1,2 ... ...,
In lte system, the length for scrambling processes is mpnPseudo-random sequence gold sequence c (n) calculation is as follows:
C (n)=(x1(n+nc)+x2(n+nc))mod2
x1(n+31)=(x1(n+3)+x1(n))mod2
x2(n+31)=(x2(n+3)+x2(n+2)+x2(n+1)+x2(n))mod2
Wherein, ncFor an initial value setting according to demand, x1And x2For two kinds of m-sequence, x1N () is x1The n-th of sequence
Position, x2N () is x2N-th of sequence, n=0,1,2 ... ..., mpn-1.
x1The initial value of sequence is x1(0)=1, x1(n)=0, n=1,2 ..., 30, x2The initial value of sequence can pass throughCalculate and obtain, n=0,1,2 ..., 30, wherein, cinitFor calculating x2The parameter of sequence initial value, this parameter
Value depend on this pseudo-random sequence application.
The method that prior art generates gold sequence is as shown in Figure 1:
1st, first by x1Sequence and x231 initial values of sequence, are sequentially saved in two 31 grades of feedback shift register respectively
In device register1 [30:0] and register2 [30:0], register1 [n]=x1(n), register2 [n]=x2(n), n
=0,1,2 ..., 30；
2nd, judge whether shift count i is more than or equal to nc, if it is, by register1 [0] and register2 [0]
Value carries out the i-th-n that XOR obtains c (n) sequencecPosition；
3rd, the value in the value in register1 [0] and register1 [3] is carried out XOR process；
4th, by each bit right shift in register1 one, the result of step 3 is saved in register1 [30]；
5th, the value in register2 [0] and register2 [1], register2 [2], register2 [3] is carried out different
Or process；
6th, by each bit right shift in register2 one, the result of step 5 is saved in register2 [30]；
8th, repeated execution of steps 2 to 7, until shift count i=mpn-1+nc.
The method that prior art generates gold sequence shifts the bit only calculating c (n) sequence every time, so,
One clock cycle at most can be only generated the bit of c (n) sequence, and will generate whole c (n) sequence and at least need at least
mpn-1+ncThe individual clock cycle, generate whole sequence required time expense excessive.
Content of the invention
In view of this, the invention provides a kind of method and device of generation gold sequence, existed with solving prior art
Sequence generate the excessive problem of time overhead.
The technical scheme is that
A kind of method of generation gold sequence, including,
Step 1, preserve x respectively using two 31 grades of feedback shift registers1Sequence and x231 bits of original of sequence
Value；
Step 2, as acquired x1Sequence and x2Sequence length is more than or equal to ncWhen, by preserve in shift register
Digit is not less than ncX1Sequence and the x of identical bits2The parallel XOR of sequence bits generates corresponding c (n)；
Step 3,31 x utilizing in feedback shift register1Sequence bits parallel computation obtains x1Follow-up 28 of sequence
Bit, using 31 x in feedback shift register2Sequence bits parallel computation obtains x2Follow-up 28 bits of sequence；
Step 4, by acquired x1Sequence and x2High 31 of sequence are sequentially stored in respective feedback shift register respectively
In；
Repeated execution of steps 2～4, until generating mpnIndividual c (n) sequence bits position.
Wherein, described c (n) sequence is the required gold sequence calculating, and the bit of corresponding c (n) sequence is n-nc+k,
K=0...27, wherein, n is x1Sequence and x2The bit of sequence, x1Sequence and x2Sequence is two calculating needed for gold sequence
Individual greatest length liner code sequence, ncFor an initial value setting according to demand, mpnLength for c (n) sequence of required calculating
Degree.
Described step 2 further includes:
If the x preserving in feedback shift register1Sequence and x2Sequence median is higher than ncNumber of bits be less than 28,
By the x preserving in feedback shift register1Sequence and x2Sequence median is higher than ncBit enter row cache respectively；
If the x preserving in feedback shift register1Sequence and x2Sequence median is higher than ncNumber of bits be more than or wait
In 28, by high for feedback shift register 28 x being preserved1Sequence and x2The sequence x with caching respectively1Sequence and x2Sequence is entered
Row splicing, the x that splicing is obtained1Low 28 of sequence and x2Low 28 of sequence carry out parallel XOR and calculate acquisition c (n) sequence
Corresponding positions, spliced x1Sequence and x2Sequence remaining bits enter row cache respectively.
Described step 2 further includes:
If the x preserving in feedback shift register1Sequence and x2Sequence median is higher than ncNumber of bits be less than 28,
By the x preserving in feedback shift register1Sequence and x2Sequence median is higher than ncBit carry out parallel XOR and calculate obtaining c
(n) sequence corresponding positions；
Otherwise by high for feedback shift register 28 x being preserved1Sequence and x2Sequence carries out parallel XOR and calculates acquisition c
(n) sequence corresponding positions.
The present invention additionally provides a kind of device of generation gold sequence simultaneously, comprising:
Two 31 grades of feedback shift register register1 and register2；x1Sequence computing module, x2Sequence calculates mould
Block, c (n) sequence computing module；Buffer 1 and buffer 2；
Wherein, described x1Sequence computing module, x2Sequence computing module, c (n) sequence computing module include respectively 28 different
Or computing unit；
Described register1 is used for preserving x1Sequence, respectively with described x1Sequence computing module is connected with described buffer 1
Connect, send the x preserving in register11Sequence gives described x1Sequence computing module and described buffer 1；
Described register2 is used for preserving x2Sequence, respectively with described x2Sequence computing module is connected with described buffer 2
Connect, send the x preserving in register22Sequence gives described x2Sequence computing module and described buffer 2；
Described x1Sequence computing module carries out the parallel XOR in 28 tunnels and calculates and will calculate knot to the data that register1 sends
Fruit feeds back to described register1；
Described x2Sequence computing module carries out the parallel XOR in 28 tunnels and calculates and will calculate knot to the data that register2 sends
Fruit feeds back to described register2；
Described buffer 1 and described buffer 2 are connected with described c (n) sequence computing module respectively, send x1Sequence and x2
Sequence is to described c (n) sequence computing module；
Described c (n) sequence computing module is by x1Sequence and x2The corresponding bit position of sequence carries out parallel XOR and obtains accordingly
C (n) sequence bits position.
The gold sequence computational methods of the present invention and device employ 28 tunnel parallel computation x1Sequence, x2Sequence and c (n) sequence
Row, once calculate and can generate 28 gold sequence bits, reduce the time overhead calculating gold sequence, improve gold sequence
Calculating speed.
Brief description
Accompanying drawing 1 is that prior art generates gold sequence method schematic diagram
Accompanying drawing 2 is that the present invention generates x1Sequence method schematic diagram
Accompanying drawing 3 is that the present invention generates x2Sequence method schematic diagram
Accompanying drawing 4 is that the present invention generates c (n) sequence method schematic diagram
Accompanying drawing 5 is the method flow diagram that the specific embodiment of the invention 1 generates gold sequence
Accompanying drawing 6 is the method flow diagram that the specific embodiment of the invention 2 generates gold sequence
Accompanying drawing 7 is the structure drawing of device that the present invention generates gold sequence
In figure, 201,301,401 is XOR computing unit.
Specific embodiment
For clear explanation technical scheme, preferred embodiment is given below and is described with reference to the accompanying drawings.
Specific embodiment 1
The method that the present embodiment generates gold sequence is as shown in Figure 5:
1st, by x131 initial value x of sequence1(0)～x1(30) sequentially it is saved in 31 grades of feedback shift registers
In the register1 [0:30] of register1, by x231 bit initial values x of sequence2(0)～x2(30) sequentially it is saved in 31 grades
In the register2 [0:30] of feedback shift register register2；
2nd, as acquired x1Sequence and x2Sequence length is more than or equal to ncWhen, by the digit preserving in shift register
It is not less than ncX1Sequence and identical bits x2The parallel XOR of sequence bits generates corresponding c (n)；In the present embodiment particularly as follows:
Relatively k withSize, ifAnd be about to register1 [n] and register2 [n] carry out different
Or, obtaining low 30- (nc-28 × k) bit data of c (n) sequence, execution step 3, if kAnd be about to
Register1 [n] and register2 [n] carries out XOR, obtains follow-up 28 bit datas of c (n) sequence；Wherein, n=3,4,
5,……,30；Execution step 3, ifExecution step 3, wherein k are that step 4 executes number of times,For rounding downwards
Operation；
The method generating c (n) sequence is as shown in Figure 4；
3rd, judge whether the bit number of acquired c (n) sequence is more than or equal to mpn, if execution step 6, otherwise execute
Step 4；
4 and the value be about in register1 [i] and register1 [i+3] depositor carry out XOR and obtain x1After sequence
Continuous 28 bit datas；And it is about to register2 [i] and register2 [i+1], register2 [i+2], register2 [i+3]
In value carry out XOR, obtain x2Follow-up 28 bit datas of sequence；Wherein, i=0,1,2 ..., 27；
5th, the data order in register1 is moved to right 28, the 28 bit x that this XOR is obtained1Sequence order is deposited
It is put in register1 [3:30]；Data order in register2 is moved to right 28,28 bits that this XOR is obtained
x2Sequence order is stored in register2 [3:30]；Execution step 21；
X is generated in step 4～51The method of sequence is as shown in Fig. 2 generate x2The method of sequence is as shown in figure 3, the present embodiment
In, to x1Sequence and x2Sequence respectively employs 28 XOR computing units to realize 28 x of a parallel generation1Sequence subsequently than
Spy and 28 x2Sequence subsequent bits；
6th, 0～m of c (n) sequence that output obtainspn- 1, complete this and generate gold sequence process.
Specific embodiment 2
The method flow of the generation gold sequence of the present embodiment is as shown in Figure 6:
Step 1 is identical with specific embodiment 1；
Step 2 in the present embodiment particularly as follows:
21st, compare k withSize, ifExecution step 22, ifExecution step 23, such as
ReallyExecution step 3, wherein k are that step 4 executes number of times,For downward floor operation；
22nd, the data in register1 [n] is saved in buffer 1, register2 [n] is saved in buffer 2
In, execution step 3, wherein, n=nc-28 × k ... ..., 30；
23rd, the data in the data and buffer 1 in register1 [n] is spliced, exported spliced data
Low 28 bits, wherein, n=3 ... ..., 30；
Wherein, described joining method is as the low level splicing data using the data preserving in buffer, by register1
Data in [n] is as a high position for splicing data；24th, the data in the data and buffer 2 in register2 [n] is carried out
Splicing, exports low 28 bits of spliced data, wherein, n=3 ... ..., 30；
Wherein, described joining method is as the low level splicing data using the data preserving in buffer, by register1
Data in [n] is as a high position for splicing data.
25 and the same bits position data of each bit data and step 24 output being about to step 23 output carries out XOR,
Calculate corresponding 28 bit c (n) sequences, execution step 3；
The method generating c (n) sequence is as shown in Figure 4；
3rd, judge whether the bit number of acquired c (n) sequence is more than or equal to mpn, if execution step 6, otherwise execute
Step 4；
4 is identical with specific embodiment 1 step 4；
5 is identical with specific embodiment 1 step 5；
X is generated in step 4～51The method of sequence is as shown in Fig. 2 generate x2The method of sequence is as shown in figure 3, the present embodiment
In, to x1Sequence and x2Sequence respectively employs 28 XOR computing units to realize 28 x of a parallel generation1Sequence subsequently than
Spy and 28 x2Sequence subsequent bits；
6th, 0～m of c (n) sequence that output obtainspn- 1, complete this and generate gold sequence process.
Specific embodiment 3
The present embodiment is a kind of preferred implementation that the present invention generates gold sequence device, its apparatus structure such as Fig. 7 institute
Show, comprising:
Two 31 grades of feedback shift register register1 and register2；x1Sequence computing module, x2Sequence calculates mould
Block, c (n) sequence computing module；Buffer 1 and buffer 2；
Wherein, described x1Sequence computing module, x2Sequence computing module, c (n) sequence computing module include respectively 28 different
Or computing unit；
Described register1 is used for preserving x1Sequence, respectively with described x1Sequence computing module is connected with described buffer 1
Connect, send the x preserving in register11Sequence gives described x1Sequence computing module and described buffer 1；
Described register2 is used for preserving x2Sequence, respectively with described x2Sequence computing module is connected with described buffer 2
Connect, send the x preserving in register22Sequence gives described x2Sequence computing module and described buffer 2；
Described x1Sequence computing module carries out the parallel XOR in 28 tunnels and calculates and will calculate knot to the data that register1 sends
Fruit feeds back to described register1；
Described x2Sequence computing module carries out the parallel XOR in 28 tunnels and calculates and will calculate knot to the data that register2 sends
Fruit feeds back to described register2；
Described buffer 1 and described buffer 2 are connected with described c (n) sequence computing module respectively, send x1Sequence and x2
Sequence is to described c (n) sequence computing module；
The x that described buffer 1 and described buffer 2 are sended over by described c (n) sequence computing module1The each bit of sequence
With x2The same bits position of sequence carries out parallel XOR and obtains corresponding c (n) sequence bits position.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention it is clear that those skilled in the art
Member the present invention can be carried out various change and modification without departing from the spirit and scope of the present invention.So, if the present invention
These modifications and modification belong within the scope of the claims in the present invention and its equivalent technologies, then the present invention is also intended to comprise these
Including change and modification.
Claims (4)
1. a kind of method of generation gold sequence is it is characterised in that include:
Step 1, preserve x respectively using two 31 grades of feedback shift registers1Sequence and x231 initial bit value of sequence；
Step 2, as acquired x1Sequence and x2Sequence length is more than or equal to ncWhen, by the digit preserving in shift register
It is not less than ncX1Sequence and identical bits x2The parallel XOR of sequence bits generates correspondingc(n)；
Step 3,31 x utilizing in feedback shift register1Sequence bits parallel computation obtains x1Follow-up 28 ratios of sequence
Spy, using 31 x in feedback shift register2Sequence bits parallel computation obtains x2Follow-up 28 bits of sequence；
Step 4, by acquired x1Sequence and x2High 31 of sequence are sequentially stored in respective feedback shift register respectively；
Repeated execution of steps 2～4, until generating mpnIndividual c (n) sequence bits position；
Wherein, described c (n) sequence is the required gold sequence calculating, and the bit of corresponding c (n) sequence is n-nc+ k, k=
0 ... 27, wherein, n is x1Sequence and x2The bit of sequence, x1Sequence and x2Sequence be calculate gold sequence needed for two
Long length liner code sequence, ncFor an initial value setting according to demand, mpnLength for c (n) sequence of required calculating.
2. a kind of method of generation gold sequence according to claim 1 is it is characterised in that described step 2 includes:
If the x preserving in feedback shift register1Sequence and x2Sequence median is higher than ncNumber of bits be less than 28, will be anti-
The x preserving in feedback shift register1Sequence and x2Sequence median is higher than ncBit enter row cache respectively；
If the x preserving in feedback shift register1Sequence and x2Sequence median is higher than ncNumber of bits be more than or equal to
28, by high for feedback shift register 28 x being preserved1Sequence and x2The sequence x with caching respectively1Sequence and x2Sequence is carried out
Splicing, the x that splicing is obtained1Low 28 of sequence and x2Low 28 of sequence carry out parallel XOR and calculate acquisition c (n) sequence phase
Ying Wei, spliced x1Sequence and x2Sequence remaining bits enter row cache respectively.
3. a kind of method of generation gold sequence according to claim 1 is it is characterised in that described step 2 includes:
If the x preserving in feedback shift register1Sequence and x2Sequence median is higher than ncNumber of bits be less than 28, will be anti-
The x preserving in feedback shift register1Sequence and x2Sequence median is higher than ncBit carry out parallel XOR and calculate obtaining c (n) sequence
Row corresponding positions；
Otherwise by high for feedback shift register 28 x being preserved1Sequence and x2Sequence carries out parallel XOR and calculates acquisition c (n) sequence
Row corresponding positions.
4. a kind of device of generation gold sequence is it is characterised in that include:
Two 31 grades of feedback shift register register1 and register2；x1Sequence computing module, x2Sequence computing module, c
(n) sequence computing module；Buffer 1 and buffer 2；
Wherein, described x1Sequence computing module, x2Sequence computing module, c (n) sequence computing module includes 28 XOR meters respectively
Calculate unit；
Described register1 is used for preserving x1Sequence, respectively with described x1Sequence computing module is connected with described buffer 1, sends out
Send the x preserving in register11Sequence gives described x1Sequence computing module and described buffer 1；
Described register2 is used for preserving x2Sequence, respectively with described x2Sequence computing module is connected with described buffer 2, sends out
Send the x preserving in register22Sequence gives described x2Sequence computing module and described buffer 2；
Described x1Sequence computing module carries out the parallel XOR in 28 tunnels and calculates and result of calculation is anti-to the data that register1 sends
It is fed to described register1；
Described x2Sequence computing module carries out the parallel XOR in 28 tunnels and calculates and result of calculation is anti-to the data that register2 sends
It is fed to described register2；
Described buffer 1 and described buffer 2 are connected with described c (n) sequence computing module respectively, send x1Sequence and x2Sequence
To described c (n) sequence computing module；
The x that described buffer 1 and described buffer 2 are sended over by described c (n) sequence computing module1Sequence and x2Sequence right
Answer bit to carry out parallel XOR and obtain corresponding c (n) sequence bits position.
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| CN102891726B (en) * | 2012-09-10 | 2015-04-08 | 华为技术有限公司 | Method for generating Gold sequence and chip |
| CN103812596B (en) * | 2012-11-09 | 2017-07-04 | 联芯科技有限公司 | The generation method and device of pseudo-random sequence |
| CN108965173B (en) * | 2018-06-12 | 2020-07-31 | 深圳市华星光电技术有限公司 | Descrambling method, descrambling device and readable storage medium |
| CN113922913B (en) * | 2021-09-28 | 2023-08-01 | 中孚信息股份有限公司 | GOLD scrambling code sequence generation method, system and equipment of LTE system |
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Effective date of registration: 20181109 Address after: 201203 Building 1, exhibition hall, 2288 lane, 2288 Chong, road, Zhangjiang hi tech park, Shanghai Patentee after: Zhanxun Communication (Shanghai) Co., Ltd. Address before: 400060 Nanping Road 199, Nanping Street, Nan'an District, Chongqing, 403 Patentee before: Keen (Chongqing) Microelectronics Technology Co., Ltd. |
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