CN102281116A - Method and device for generating GOLD sequence - Google Patents

Abstract

The invention discloses a method for generating a GOLD sequence. The method comprises the following steps of: respectively storing 31 initial bit values of a sequence x1 and a sequence x2 by using two 31-level feedback shift registers; carrying out parallel computation on 31 bits in the sequence x1 in the feedback shift register at a time to obtain 28 follow-up bits of the sequence x1, and carrying out parallel computation on 31 bits of the sequence x2 in the feedback shift register to obtain 28 follow-up bits of the sequence x2; when the acquired length of the sequence x1 and the acquired length of the sequence x2 are more than or equal to NC bit, carrying out parallel xor on the sequence x1 with the digits not less than NC and the sequence x2 with the same digits with the sequence x1, which are stored in the shift registers, to generate corresponding c(n); and respectively storing the acquired high 31bits of the sequence x1 and the sequence x2 to the feedback shift register in sequence. Meanwhile, the invention also discloses a device for generating the GOLD sequence. According to the method and device for generating the GOLD sequence disclosed by the invention, the sequence x1, the sequence x2 and the sequence c(n) are subjected to 28-path parallel computation, and 28 GOLD sequence bits can be generated by one-step computation, therefore the time consumption in computing the GOLD sequence is reduced, and the computation speed of the GOLD sequence is improved.

Description

A kind of method and device that generates the GOLD sequence

Technical field

The present invention relates to a kind of mobile communication system technology, specially refer to the method and the device that generate the GOLD scramble sequence in a kind of 3-G (Generation Three mobile communication system).

Background technology

In mobile communication system, can use pseudo random sequence (being called for short the PN sequence) with the binary digit message elder generation scrambling that information source produces usually, transmit again, the purpose of Chu Liing mainly is like this:

1, randomness realizes the encryption of communication channel;

Binary digit message and the very long pseudo random sequence exclusive-OR of one-period with information source produces so just can become former message impenetrable another sequence.Have only the same pseudo random sequence of use could recover former transmission content at receiving terminal.

2, spread-spectrum and realize CDMA communication according to orthogonality;

According to the shannon capacity formula, we can utilize yard bandwidth of expanding communication channel, have reached Utopian channel capacity.If cross-correlation coefficient very little (nearly orthogonal) between the employed sign indicating number resource then can be realized using between the user of different orthogonal sign indicating number not interfering with each other, on same frequency range, just may realize sending simultaneously many signals like this, the realization CDMA communication.

3, disordering data sequence and descrambling

In the digital communication system, as the distance of swimming (occurring 0 or 1 continuously) of appearance 1 or 0 is excessive continuously in the prime information, then will influence bit synchronous foundation and maintenance, the anti-interference under this kind situation is relatively poor simultaneously.Easily form and crosstalk.At this moment we can upset the prime information sequence and the sequence that forms similar white noise statistical property is transmitted.

Wherein, described pseudo random sequence has the fundamental characteristics of the random sequence of being similar to, and is a kind ofly to seem to be at random but be actually clocklike periodically binary sequence.In mobile communication system, the most frequently used PN sequence is maximum length linear code sequence (being called for short the m sequence), is produced by the linear feedback shift device, is characterized in having periodically and pseudo-randomness.

The GOLD sequence is a kind of sign indicating number sequence based on the m sequence, is usually used in the scrambling process of mobile communication system, and the GOLD sequence has better auto-correlation and their cross correlation, and the sequence number of generation is many.The autocorrelation of Gold sequence is not as the m sequence, and cross correlation is better than m sequence.

Method for scrambling in the mobile communication system is, for each code word, bit stream

(wherein

Be the amount of bits of the code word q of the physical channel transmission on each subframe) and binary pseudo-random sequence c ^q(n) carry out scrambling, press the bit after following formula generates scrambling

${\tilde{b}}^q\left(n\right)=(b^q\left(n\right)+c^q\left(n\right))\mathrm{<figure-callout\; id="2"\; label="mod"\; filenames="HSA00000164259800011.png,HSA00000164259800031.png"\; state="\{\{state\}\}">mod</figure-callout>}2$

Wherein, $n=\mathrm{0,1,2},\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;,M_{\mathrm{bit}}^{\left(q\right)}-1.$

In the LTE system, the length that is used for the scrambling process is M _PNPseudo random sequence GOLD sequence c (n) account form is as follows:

c(n)＝(x ₁(n+N _C)+x ₂(n+N _C))mod2

x ₁(n+31)＝(x ₁(n+3)+x ₁(n))mod2

x ₂(n+31)＝(x ₂(n+3)+x ₂(n+2)+x ₂(n+1)+x ₂(n))mod2

Wherein, N _CBe an initial value of setting according to demand, x ₁And x ₂Be two kinds of m sequences, x ₁(n) be x ₁The n position of sequence, x ₂(n) be x ₂The n position of sequence, n=0,1,2 ..., M _PN-1.

x ₁The initial value of sequence is x ₁(0)=1, x ₁(n)=0, n=1,2 ..., 30, x ₂The initial value of sequence can pass through

Calculate and obtain n-0,1,2 ..., 30, wherein, c _InitFor calculating x ₂The parameter of sequence initial value, the value of this parameter depends on the application of this pseudo random sequence.

The method that prior art generates the GOLD sequence is as shown in Figure 1:

1, at first with x ₁Sequence and x ₂31 initial values of sequence, order is saved in two 31 grades of feedback shift register Register1[30 respectively: 0] and Register2[30: 0] in, Register1[n]=x ₁(n), Register2[n]=x ₂(n), n=0,1,2 ..., 30;

2, judge that whether shift count i is more than or equal to N _C, if, with Register1[0] and Register2[0] in value carry out the i-N that XOR obtains c (n) sequence _CThe position;

3, with Register1[0] in value and Register1[3] in value carry out XOR and handle;

4, each bit among the Register1 is moved to right one, the result of step 3 is saved in Register1[30];

5, with Register2[0] and Register2[1], Register2[2], Register2[3] in value carry out XOR and handle;

6, each bit among the Register2 is moved to right one, the result of step 5 is saved in Register2[30];

8, repeated execution of steps 2 to 7, up to shift count i=M _PN-1+N _C

The bit of a c (n) sequence is only calculated in the each displacement of method of prior art generation GOLD sequence, and like this, a clock cycle can only generate the bit of a c (n) sequence at most, needs M at least at least and will generate whole c (n) sequence _PN-1+N _CThe individual clock cycle, it is excessive to generate whole sequence required time expense.

Summary of the invention

In view of this, the invention provides a kind of method and device of the GOLD of generation sequence, to solve the excessive problem of sequence rise time expense that prior art exists.

Technical scheme of the present invention is:

A kind of method that generates the GOLD sequence comprises,

Step 1, two 31 grades of feedback shift registers of use are preserved x respectively ₁Sequence and x ₂31 bits of original values of sequence;

Step 2, as acquired x ₁Sequence and x ₂Sequence length is more than or equal to N _CThe time, the figure place of preserving in the shift register is not less than N _CX ₁The x of sequence and identical bits ₂The parallel XOR of sequence bits generates corresponding c (n);

Step 3, utilize 31 x in the feedback shift register ₁The sequence bits parallel computation obtains x ₁Follow-up 28 bits of sequence utilize 31 x in the feedback shift register ₂The sequence bits parallel computation obtains x ₂Follow-up 28 bits of sequence;

Step 4, with acquired x ₁Sequence and x ₂High 31 of sequence are stored in the respective feedback shift register respectively in proper order;

Repeated execution of steps 2～4 is up to generating M _PNIndividual c (n) sequence bits position.

Wherein, described c (n) sequence is the GOLD sequence of required calculating, x ₁Sequence and x ₂Sequence is for calculating two required maximum length linear code sequences of GOLD sequence, N _CBe an initial value of setting according to demand, M _PNLength for c (n) sequence of required calculating.

Described step 2 further comprises:

If the x that preserves in the feedback shift register ₁Sequence and x ₂The sequence median is higher than N _CNumber of bits less than 28, with the x that preserves in the feedback shift register ₁Sequence and x ₂The sequence median is higher than N _CBit carry out buffer memory respectively;

If the x that preserves in the feedback shift register ₁Sequence and x ₂The sequence median is higher than N _CNumber of bits more than or equal to 28, with high 28 x that preserved of feedback shift register ₁Sequence and x ₂Sequence respectively with the x of buffer memory ₁Sequence and x ₂Sequence is spliced, the x that splicing is obtained ₁Low 28 and the x of sequence ₂Low 28 XORs that walk abreast of sequence calculate and obtain c (n) sequence corresponding positions, spliced x ₁Sequence and x ₂The sequence remaining bits is carried out buffer memory respectively.

Described step 2 further comprises:

If the x that preserves in the feedback shift register ₁Sequence and x ₂The sequence median is higher than N _CNumber of bits less than 28, with the x that preserves in the feedback shift register ₁Sequence and x ₂The sequence median is higher than N _CThe bit XOR that walks abreast calculate to obtain c (n) sequence corresponding positions;

Otherwise with high 28 x that preserved of feedback shift register ₁Sequence and x ₂The sequence XOR that walks abreast calculate to obtain c (n) sequence corresponding positions.

The present invention also provides a kind of device of the GOLD of generation sequence simultaneously, comprising:

Two 31 grades of feedback shift register Register1 and Register2; x ₁The sequence computing module, x ₂The sequence computing module, c (n) sequence computing module; Buffer 1 and buffer 2;

Wherein, described x ₁The sequence computing module, x ₂The sequence computing module, c (n) sequence computing module comprises 28 XOR computing units respectively;

Described Register1 is used to preserve x ₁Sequence is respectively with described x ₁The sequence computing module is connected with described buffer 1, sends the x that preserves among the Register1 ₁Sequence is given described x ₁Sequence computing module and described buffer 1;

Described Register2 is used to preserve x ₂Sequence is respectively with described x ₂The sequence computing module is connected with described buffer 2, sends the x that preserves among the Register2 ₂Sequence is given described x ₂Sequence computing module and described buffer 2;

Described x ₁The data that the sequence computing module sends Register1 are carried out 28 tunnel parallel XORs calculating and result of calculation are fed back to described Register1;

Described x ₂The data that the sequence computing module sends Register2 are carried out 28 tunnel parallel XORs calculating and result of calculation are fed back to described Register2;

Described buffer 1 is connected with described c (n) sequence computing module respectively with described buffer 2, sends x ₁Sequence and x ₂Sequence is to described c (n) sequence computing module;

Described c (n) sequence computing module is with x ₁Sequence and x ₂The corresponding bit position of the sequence XOR that walks abreast obtains corresponding c (n) sequence bits position.

GOLD sequence computational methods of the present invention and device have adopted 28 tunnel parallel computation x ₁Sequence, x ₂Sequence and c (n) sequence is once calculated and can be generated 28 GOLD sequence bits, has reduced to calculate the time overhead of GOLD sequence, has improved the computational speed of GOLD sequence.

Description of drawings

Accompanying drawing 1 is that prior art generates GOLD sequence method schematic diagram

Accompanying drawing 2 is that the present invention generates x ₁The sequence method schematic diagram

Accompanying drawing 3 is that the present invention generates x ₂The sequence method schematic diagram

Accompanying drawing 4 is that the present invention generates c (n) sequence method schematic diagram

Accompanying drawing 5 is method flow diagrams that the specific embodiment of the invention 1 generates the GOLD sequence

Accompanying drawing 6 is method flow diagrams that the specific embodiment of the invention 2 generates the GOLD sequence

Accompanying drawing 7 is structure drawing of device that the present invention generates the GOLD sequence

Among the figure, 201,301,401 is the XOR computing unit.

Embodiment

For clearly demonstrating technical scheme of the present invention, provide preferred embodiment below and be described with reference to the accompanying drawings.

Specific embodiment 1

The method that present embodiment generates the GOLD sequence is as shown in Figure 5:

1, with x ₁31 initial value x of sequence ₁(0)～x ₁(30) order is saved in the Register1[0 of 31 grades of feedback shift register Register1: 30] in, with x ₂31 bit initial values x of sequence ₂(0)～x ₂(30) order is saved in the Register2[0 of 31 grades of feedback shift register Register2: 30] in;

2, relatively k with

Size, if

Execution in step 3, if

Execution in step 4, if

Execution in step 5, wherein k is that step 6 is carried out number of times, For rounding operation downwards;

3 and be about to Register1[n] and Register2[n] carry out XOR, obtain the low 30-(N of c (n) sequence _C-28 * k) Bit datas, execution in step 5, wherein, n=N _C-28 * k ..., 30;

4 and be about to Register1[n] and Register2[n] carry out XOR, obtain follow-up 28 Bit datas of c (n) sequence; Wherein, n=3,4,5 ..., 30;

The method of generation c (n) sequence as shown in Figure 4;

5, judge that whether the bit number of acquired c (n) sequence is more than or equal to M _PN, if execution in step 8, otherwise execution in step 6;

6 and be about to Register1[i] and Register1[i+3] value in the register carries out XOR and obtains x ₁Follow-up 28 Bit datas of sequence; And be about to Register2[i] and Register2[i+1], Register2[i+2], Register2[i+3] in value carry out XOR, obtain x ₂Follow-up 28 Bit datas of sequence; Wherein, i=0,1,2 ..., 27;

7, the data among the Register1 are moved to right 28 in proper order, with 28 bit x of this XOR acquisition ₁Sequence order is stored in Register1[3: 30] in; Data among the Register2 are moved to right 28 in proper order, with 28 bit x of this XOR acquisition ₂Sequence order is stored in Register2[3: 30] in; Execution in step 2;

Generate x in step 6～7 ₁The method of sequence generates x as shown in Figure 2 ₂The method of sequence as shown in Figure 3, in the present embodiment, to x ₁Sequence and x ₂Sequence has respectively used 28 XOR computing units to realize once parallel 28 x of generation ₁Sequence subsequent bits and 28 x ₂The sequence subsequent bits;

8,0～M of c (n) sequence of output acquisition _PN-1, finish this and generate GOLD sequence process.

Specific embodiment 2

The method flow of the generation GOLD sequence of present embodiment is as shown in Figure 6:

Step 1 is identical with specific embodiment 1;

2, relatively k with

Size, if Execution in step 3, if

Execution in step 4, if Execution in step 7, wherein k is that step 8 is carried out number of times,

For rounding operation downwards;

3, with Register1[n] in data be saved in the buffer 1, Register2[n] be saved in the buffer 2, execution in step 7, wherein, n=N _C-28 * k ..., 30;

4, with Register1[n] in data and the data in the buffer 1 splice, export low 28 bits of spliced data, wherein, n=3 ..., 30;

Wherein, described joining method is for data that will preserve in the buffer low level as the splicing data, with Register1[n] in data as the high position of splicing data.

5, with Register2[n] in data and the data in the buffer 2 splice, export low 28 bits of spliced data, wherein, n=3 ..., 30;

Wherein, described joining method is for data that will preserve in the buffer low level as the splicing data, with Register1[n] in data as the high position of splicing data.

6 and be about to each Bit data of step 4 output and carry out XOR with the same bits bit data that step 5 is exported, calculate corresponding 28 bit c (n) sequences;

The method of generation c (n) sequence as shown in Figure 4;

7, judge that whether the bit number of acquired c (n) sequence is more than or equal to M _PN, if execution in step 10, otherwise execution in step 8;

8, identical with specific embodiment 1 step 6;

9, identical with specific embodiment 1 step 7;

Generate x in step 8～9 ₁The method of sequence generates x as shown in Figure 2 ₂The method of sequence as shown in Figure 3, in the present embodiment, to x ₁Sequence and x ₂Sequence has respectively used 28 XOR computing units to realize once parallel 28 x of generation ₁Sequence subsequent bits and 28 x ₂The sequence subsequent bits;

10,0～M of c (n) sequence of output acquisition _PN-1, finish this and generate GOLD sequence process.

Specific embodiment 3

Present embodiment is a kind of preferred implementation that the present invention generates GOLD sequence device, and its apparatus structure comprises as shown in Figure 7:

Two 31 grades of feedback shift register Register1 and Register2; x ₁The sequence computing module, x ₂The sequence computing module, c (n) sequence computing module; Buffer 1 and buffer 2;

Wherein, described x ₁The sequence computing module, x ₂The sequence computing module, c (n) sequence computing module comprises 28 XOR computing units respectively;

Described Register1 is used to preserve x ₁Sequence is respectively with described x ₁The sequence computing module is connected with described buffer 1, sends the x that preserves among the Register1 ₁Sequence is given described x ₁Sequence computing module and described buffer 1;

Described Register2 is used to preserve x ₂Sequence is respectively with described x ₂The sequence computing module is connected with described buffer 2, sends the x that preserves among the Register2 ₂Sequence is given described x ₂Sequence computing module and described buffer 2;

Described x ₁The data that the sequence computing module sends Register1 are carried out 28 tunnel parallel XORs calculating and result of calculation are fed back to described Register1;

Described x ₂The data that the sequence computing module sends Register2 are carried out 28 tunnel parallel XORs calculating and result of calculation are fed back to described Register2;

Described buffer 1 is connected with described c (n) sequence computing module respectively with described buffer 2, sends x ₁Sequence and x ₂Sequence is to described c (n) sequence computing module;

The x that described c (n) sequence computing module sends over described buffer 1 and described buffer 2 ₁Each bit of sequence and x ₂The same bits position of the sequence XOR that walks abreast obtains corresponding c (n) sequence bits position.

The above is the preferred embodiments of the present invention only, is not limited to the present invention, and obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.

Claims (4)

1. a method that generates the GOLD sequence is characterized in that, comprising:

Step 1, two 31 grades of feedback shift registers of use are preserved x respectively ₁Sequence and x ₂31 bits of original values of sequence;

Step 2, as acquired x ₁Sequence and x ₂Sequence length is more than or equal to N _CThe time, the figure place of preserving in the shift register is not less than N _CX ₁Sequence and identical bits x ₂The parallel XOR of sequence bits generates corresponding c (n);

Step 3, utilize 31 x in the feedback shift register ₁The sequence bits parallel computation obtains x ₁Follow-up 28 bits of sequence utilize 31 x in the feedback shift register ₂The sequence bits parallel computation obtains x ₂Follow-up 28 bits of sequence;

Step 4, with acquired x ₁Sequence and x ₂High 31 of sequence are stored in the respective feedback shift register respectively in proper order;

Repeated execution of steps 2～4 is up to generating M _PNIndividual c (n) sequence bits position.

Wherein, described c (n) sequence is the GOLD sequence of required calculating, x ₁Sequence and x ₂Sequence is for calculating two required maximum length linear code sequences of GOLD sequence, N _CBe an initial value of setting according to demand, M _PNLength for c (n) sequence of required calculating.

2. a kind of method that generates the GOLD sequence according to claim 1 is characterized in that described step 2 comprises:

If the x that preserves in the feedback shift register ₁Sequence and x ₂The sequence median is higher than N _CNumber of bits less than 28, with the x that preserves in the feedback shift register ₁Sequence and x ₂The sequence median is higher than N _CBit carry out buffer memory respectively;

If the x that preserves in the feedback shift register ₁Sequence and x ₂The sequence median is higher than N _CNumber of bits more than or equal to 28, with high 28 x that preserved of feedback shift register ₁Sequence and x ₂Sequence respectively with the x of buffer memory ₁Sequence and x ₂Sequence is spliced, the x that splicing is obtained ₁Low 28 and the x of sequence ₂Low 28 XORs that walk abreast of sequence calculate and obtain c (n) sequence corresponding positions, spliced x ₁Sequence and x ₂The sequence remaining bits is carried out buffer memory respectively.

3. a kind of method that generates the GOLD sequence according to claim 1 is characterized in that described step 2 comprises:

If the x that preserves in the feedback shift register ₁Sequence and x ₂The sequence median is higher than N _CNumber of bits less than 28, with the x that preserves in the feedback shift register ₁Sequence and x ₂The sequence median is higher than N _CThe bit XOR that walks abreast calculate to obtain c (n) sequence corresponding positions;

Otherwise with high 28 x that preserved of feedback shift register ₁Sequence and x ₂The sequence XOR that walks abreast calculate to obtain c (n) sequence corresponding positions.

4. a device that generates the GOLD sequence is characterized in that, comprising:

Two 31 grades of feedback shift register Register1 and Register2; x ₁The sequence computing module, x ₂The sequence computing module, c (n) sequence computing module; Buffer 1 and buffer 2;

Wherein, described x ₁The sequence computing module, x ₂The sequence computing module, c (n) sequence computing module comprises 28 XOR computing units respectively;

Described Register1 is used to preserve x ₁Sequence is respectively with described x ₁The sequence computing module is connected with described buffer 1, sends the x that preserves among the Register1 ₁Sequence is given described x ₁Sequence computing module and described buffer 1;

Described Register2 is used to preserve x ₂Sequence is respectively with described x ₂The sequence computing module is connected with described buffer 2, sends the x that preserves among the Register2 ₂Sequence is given described x ₂Sequence computing module and described buffer 2;

Described x ₁The data that the sequence computing module sends Register1 are carried out 28 tunnel parallel XORs calculating and result of calculation are fed back to described Register1;

Described x ₂The data that the sequence computing module sends Register2 are carried out 28 tunnel parallel XORs calculating and result of calculation are fed back to described Register2;

Described buffer 1 is connected with described c (n) sequence computing module respectively with described buffer 2, sends x ₁Sequence and x ₂Sequence is to described c (n) sequence computing module;

The x that described c (n) sequence computing module sends over described buffer 1 and described buffer 2 ₁Sequence and x ₂The corresponding bit position of the sequence XOR that walks abreast obtains corresponding c (n) sequence bits position.

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