CN102193870B

CN102193870B - Memory management and write-in method, memory controller and memory storage system

Info

Publication number: CN102193870B
Application number: CN201010129216.XA
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2010-03-09
Filing date: 2010-03-09
Publication date: 2014-06-25
Anticipated expiration: 2030-03-09
Also published as: CN102193870A

Abstract

The invention discloses a memory management and write-in method, a memory controller and a memory storage system. The memory management and write-in method is used for managing a memory module. The memory module comprises a plurality of memory units and a plurality of data input/output buses corresponding to the memory units respectively. The method comprises the following steps of: configuring a plurality of logic units; partitioning each logic unit into a plurality of logic parts corresponding to the data input/output buses respectively; and mapping the logic part of each logic unit to entity blocks of the memory units respectively. The method further comprises the following steps of: establishing a mapping table corresponding to each input/output bus respectively; and writing data from a host computer system into a corresponding memory unit by using one input/output bus according to the mapping table corresponding to the input/output bus. By adopting the method, the data write-in speed can be increased effectively.

Description

Memory management and wiring method, Memory Controller and storage system

Technical field

The invention relates to a kind of memory management and wiring method, and relate to especially a kind of for managing memory management and the wiring method of duplicative nonvolatile memory and using Memory Controller and the storage system of the method.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years, and consumer is also increased rapidly to the demand of medium.Because duplicative nonvolatile memory (rewritable non-volatilememory) has that data are non-volatile, the little characteristic with machinery-free structure etc. of power saving, volume, be applicable to portable applications, the most applicable being used on the battery-powered product of this class Portable.Solid state hard disc is exactly a kind of memory storage using duplicative nonvolatile memory as medium.Because duplicative nonvolatile memory volume low capacity is large, so be widely used in the storage of individual significant data.Therefore, duplicative nonvolatile memory industry becomes a ring quite popular in electronic industry in recent years.

Memory storage taking flash memory module as medium is example, the memory cell of flash memory module has multiple physical blocks (physical block), and each physical blocks has multiple physical page (physical page), wherein must be according to the order of physical page data writing in order when data writing in physical blocks.In addition the physical page being written into, also needs could again be written into after first being erased.Particularly, physical blocks is the least unit of erasing, and physical page is the sequencing minimum unit of (also claiming to write).Therefore,, in the management of flash memory module, physical blocks can be divided into data field and spare area.The physical blocks of data field is the data of storing in order to host system.And the physical blocks of spare area is the physical blocks of rotating in data field.Therefore, the physical blocks in spare area is empty or spendable unit, i.e. no record data or be labeled as invalid data useless.That is to say, the physical blocks of data field and spare area is the data that the mode of rotating is carried out memory storage that host system writes to.For example, in the time that data are write to memory storage by host computer system wish, the memory management circuitry of memory storage can be identified in wants the physical blocks that is updated in data field, and from spare area, extracts physical blocks and carry out data writing to replace this physical blocks of wanting to be updated.Specifically, the memory management circuitry of memory storage can be copied to the valid data in the physical blocks of wanting to be updated at this in extracted physical blocks, the data of wanting to write are write in extracted physical blocks, and the physical blocks of written data is associated to data field.In addition the physical blocks of, wanting to be updated can be performed erases running and is associated to spare area.

Particularly, have in multiple memory cells and these memory cells example with data input/output bus (Data Input/Output Bus) transmission data independently at flash memory module, the physical blocks of memory cell can be grouped into solid element and manage taking solid element as unit.Specifically, solid element is made up of a correspondent entity block of each memory cell respectively.For example, have in the example of first memory unit and second memory unit at flash memory module, correspondent entity block of first memory unit and a correspondent entity block of second memory unit can be grouped into a solid element regularly.And physical blocks being grouped into the running of above-mentioned data field and spare area and writing in running, memory management circuitry is to carry out taking solid element as unit, reduces thus the required resource of diode-capacitor storage module.In addition, also can effectively promote writing speed by the multiple physical blocks in multiple data input/output bus while data writing to solid element.

Along with the progress of manufacture of semiconductor, in physical blocks, the capacity of each physical page is increasing.But, in the application of the Primary Hard Drive using solid state hard disc as host computer system, the size of the continuous data that host computer system writes is often less than a physical page, therefore in the time that execution writes instruction, memory management circuitry need spend the longer above-mentioned running that copies valid data of time execution, and affects the usefulness of memory storage.

In addition, the indegree of writing of physical blocks is limited.But in the above-mentioned management framework taking solid element as unit, when host computer system is only in one of them physical blocks at a solid element when data writing, Memory Management Unit still need be carried out erasing of data taking solid element as unit.Base this, the writing indegree and can increase rapidly because carrying out the above-mentioned valid data that copy of physical blocks, so that shorten the life-span of memory storage.

Summary of the invention

The invention provides a kind of memory management and wiring method, it can shorten execution and writes the time of instruction and extend the life-span of memory module.

The invention provides a kind of Memory Controller, it can shorten execution and writes the time of instruction and extend the life-span of memory module.

The invention provides a kind of storage system, it can shorten execution and writes the time of instruction and extend the life-span of memory module.

The present invention proposes a kind of memory management and wiring method, for managing a memory module.This memory module comprises first memory unit, the first input/output bus for first memory unit, second memory unit and the second input/output bus for second memory unit, and wherein first memory unit and second memory unit have multiple physical blocks.This memory management and wiring method comprise the multiple logical blocks of configuration, and each logical block is divided into the first logic section of corresponding the first input/output bus and the second logic section to should the second input/output bus.This memory management and wiring method also comprise at least a portion to the physical blocks of first memory unit and second memory unit by these logical unit mappings, and wherein the second logic section of one of them and each logical block of the physical blocks of the first logic section mapping first memory unit of each logical block is shone upon one of them of those physical blocks of second memory unit.This memory management also comprises that with wiring method the first mapping table of setting up corresponding the first input/output bus is to record the first mapping relations between the first logic section of logical block and the physical blocks of first memory unit, and the second mapping table of setting up corresponding the second input/output bus is to record the second mapping relations between the second logic section of logical block and the physical blocks of second memory unit.This memory management and wiring method also comprise receiving and write instruction and write the data of instruction with corresponding this, and wherein these data want to be written into one of them of the first logic section of logical block.This memory management also comprises according to the first mapping table of corresponding the first input/output bus and only uses the first input/output bus so that the corresponding data that this writes instruction are write in first memory unit with wiring method.

The embodiment of the present invention proposes a kind of Memory Controller, and it comprises memory interface, memory management circuitry and host interface unit.Memory interface unit is electrically connected to memory management circuitry, and in order to be electrically connected to above-mentioned memory module.Host interface is electrically connected to memory management circuitry and in order to be electrically connected to host computer system.Memory management circuitry unit is in order to carry out at least one step of above-mentioned memory management and wiring method.

The embodiment of the present invention proposes a kind of storage system, and it comprises connector, above-mentioned memory module and is electrically connected the so far Memory Controller of memory module.At this, this Memory Controller is in order to carry out at least one step of above-mentioned memory management and wiring method.

Based on above-mentioned, the memory management of the embodiment of the present invention and wiring method can operate each physical blocks that maps to same logical block independently, can shorten thus and carry out the time of copying valid data, the life-span of Bing and prolongation memory module.

For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.

Brief description of the drawings

Figure 1A is the host computer system that uses memory storage apparatus shown in first embodiment of the invention.

Figure 1B is the schematic diagram of the computer shown in the embodiment of the present invention, input/output device and memory storage apparatus.

Fig. 1 C is the schematic diagram of the host computer system shown in another embodiment of the present invention and memory storage apparatus.

Fig. 2 is the summary calcspar of the duplicative nonvolatile memory memory storage shown in Figure 1A.

Fig. 3 is the summary calcspar of the Memory Controller shown in first embodiment of the invention and memory module.

Fig. 4 and Fig. 5 are the schematic diagram of the diode-capacitor storage module shown in first embodiment of the invention.

Fig. 6 and Fig. 7 are the embodiment of logical block-physical blocks mapping table of the corresponding data input/output bus shown in first embodiment of the invention.

Fig. 8～Figure 10 is the embodiment of the data writing shown in first embodiment of the invention to memory module.

Figure 11 A and Figure 11 B are another embodiment of logical block-physical blocks mapping table of the corresponding data input/output bus shown in first embodiment of the invention.

Figure 12 is the process flow diagram of the memory management shown in first embodiment of the invention and wiring method.

Figure 13 is the summary calcspar of the memory storage apparatus shown in second embodiment of the invention.

Figure 14 is the process flow diagram of the memory management shown in second embodiment of the invention and wiring method.

Figure 15 is the summary calcspar of the memory storage apparatus shown in third embodiment of the invention.

Figure 16 is the process flow diagram of the memory management shown in third embodiment of the invention and wiring method.

Figure 17 is the summary calcspar of the memory storage apparatus shown in fourth embodiment of the invention.

Figure 18 is the process flow diagram of the memory management shown in fourth embodiment of the invention and wiring method.

Main element symbol description:

1000: host computer system 1100: computer

1102: microprocessor 1104: random access memory

1106: input/output device 1108: system bus

1110: data transmission interface 1202: mouse

1204: keyboard 1206: display

1208: printer 1212: Portable disk

1214: memory card 1216: solid state hard disc

1310: digital camera 1312:SD card

1314:MMC card 1316: memory stick

1318:CF card 1320: embedded memory storage

100,1300,1500,1700: storer 102: connector

Memory storage

104: Memory Controller 106: memory module

202: memory management circuitry 204: host interface

206: memory interface 252: memory buffer

254: electric power management circuit 256: bug check and correcting circuit

302: first memory unit 312: second memory unit

352: 354: the first control buss of wafer activation pin

364: the second control buss of 356: the first data input/output bus

366: the second data input/output bus 402: data field

404: spare area 406: system region

408: replace district 510 (0)～510 (H): logical block

612: the second logic section-physical blocks mapping tables of 602: the first logic section-physical blocks mapping tables

1302: memory management circuitry 1304: Memory Controller

1352: the first wafer activation pins 1354: control bus

1362: the second wafer activation pins of 1356: the first data input/output bus

1366: the second data input/output bus 1502: memory management circuitry

1504: Memory Controller 1552: wafer activation pin

1554: 1556: the first data input/output bus of control bus

1566: the second data input/output bus 1702: memory management circuitry

1704: 1752: the first wafer activation pins of Memory Controller

1756: the first data input/output bus of 1754: the first control buss

1764: the second control buss of 1762: the second wafer activation pins

1766: the second data input/output bus

304 (0)～304 (R), 314 (0)～314 (R): physical blocks

S1201, S1203, S1205, S1207, S1209, S1211, S1213, S1215, S1217, S1219, S1221: the step of memory management and wiring method

S1401, S1403, S1405, S1407, S1409, S1411, S1413, S1415, S1417, S1419, S1421: the step of memory management and wiring method

S1601, S1603, S1605, S1607, S1609, S1611, S1613, S1615, S1617, S1619, S1621: the step of memory management and wiring method

S1801, S1803, S1805, S1807, S1809, S1811, S1813, S1815, S1817, S1819, S1821: the step of memory management and wiring method

Embodiment

Generally speaking, memory storage apparatus (also claiming storage system) comprises memory module and controller (also claiming control circuit).Conventionally memory storage apparatus can use together with host computer system, so that host computer system can write to data memory storage apparatus or reading out data from memory storage apparatus.In addition, also having memory storage apparatus is to comprise in-line memory and can be executed in host computer system using the software as the controller of this in-line memory substantially.

The first embodiment

Please refer to Figure 1A, host computer system 1000 generally comprises computer 1100 and I/O (input/output; Hereinafter to be referred as: I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (random access memory; Hereinafter to be referred as: RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Figure 1B, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.

In embodiments of the present invention, memory storage apparatus 100 is to be electrically connected by data transmission interface 1110 and other elements of host computer system 1000.Data can be write to memory storage apparatus 100 or reading out data from memory storage apparatus 100 by microprocessor 1102, random access memory 1104 with the processing of input/output device 1106.For example, memory storage apparatus 100 can be Portable disk 1212, memory card 1214 or solid state hard disc (Solid StateDrive as shown in Figure 1B; Hereinafter to be referred as: SSD) 1216.

Generally speaking, host computer system 1000 can be substantially for storing any system of data.Though but in the present embodiment, host computer system 1000 is to explain with computer system, still, in another embodiment of the present invention, host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player.For example, be digital camera (video camera) 1310 o'clock in host computer system, memory storage apparatus is its SD card 1312 using, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded memory storage 1320 (as shown in Figure 1 C).Embedded memory storage 1320 comprises embedded multi-media card (EmbeddedMMC; Hereinafter to be referred as: eMMC).It is worth mentioning that, embedded multi-media card is to be directly electrically connected on the substrate of host computer system.

Please refer to Fig. 2, memory storage apparatus 100 comprises connector 102, Memory Controller 104 and memory module 106.

In the present embodiment, connector 102 is advanced annex (the Serial AdvancedTechnology Attachment of sequence; Hereinafter to be referred as: SATA) connector.But, it must be appreciated, the invention is not restricted to this, connector 102 can also be universal serial bus (Universal SerialBus; Hereinafter to be referred as: USB) connector, Institute of Electrical and Electric Engineers (Institute ofElectrical and Electronic Engineers; Hereinafter to be referred as: IEEE) 1394 connectors, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express; Hereinafter to be referred as: PCI Express) connector, safe digital (Secure Digital; Hereinafter to be referred as: SD) interface connector, memory stick (Memory Stick; Hereinafter to be referred as: MS) interface connector, multimedia storage card (Multi Media Card; Hereinafter to be referred as: MMC) interface connector, compact flash (CompactFlash; Hereinafter to be referred as: CF) interface connector, integrated driving electrical interface (Integrated DeviceElectronics; Hereinafter to be referred as: IDE) connector or other applicable connectors.

Memory Controller 104 is multiple logic locks or the steering order with hardware pattern or firmware pattern implementation in order to execution, and in memory module 106, carries out the runnings such as writing, read and erase of data according to the instruction of host computer system 1000.Particularly, Memory Controller 104 is in order to carry out according to data access mechanism and the memory management mechanism of the present embodiment.

Memory module 106 is to be electrically connected to Memory Controller 104, and the data that write in order to host system 1000.At this, memory module 106 is duplicative nonvolatile memory.For example, memory module 106 is a multilayer memory cell (Multi Level Cell; Hereinafter to be referred as: MLC) NAND flash memory module.But, the invention is not restricted to this, also individual layer memory cell (Single Level Cell of memory module 106; Hereinafter to be referred as: SLC) NAND flash memory module, other flash memory modules or other have the memory module of identical characteristics.

Please refer to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.

Memory management circuitry 202 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 202 has multiple steering orders, and in the time that memory storage apparatus 100 operates, these steering orders can be performed with the data access mechanism according to the present embodiment carrys out diode-capacitor storage module 106 with memory management mechanism.These data access mechanism will elaborate in the following accompanying drawing that coordinates with memory management mechanism.

In the present embodiment, the steering order of memory management circuitry 202 is to carry out implementation with a firmware pattern.For example, memory management circuitry 202 has a microprocessor unit (not shown) and a ROM (read-only memory) (not shown), and these steering orders are by imprinting so far in ROM (read-only memory).In the time that memory storage apparatus 100 operates, these steering orders can have been carried out data access mechanism and the memory management mechanism according to the embodiment of the present invention by microprocessor unit.

In another embodiment of the present invention, the steering order of memory management circuitry 202 can also procedure code pattern for example be stored in, in the specific region (, being exclusively used in the system region of storage system data in memory module) of memory module 106.In addition, memory management circuitry 202 has a microprocessor unit (not shown), a ROM (read-only memory) (not shown) and a random access memory (not shown).Particularly, this ROM (read-only memory) has a driving code section, and in the time that Memory Controller 104 is enabled, microprocessor unit can first be carried out this and drive code section that the steering order being stored in memory module 106 is loaded in the random access memory of memory management circuitry 202, reruns afterwards these steering orders to carry out data access mechanism and the memory management mechanism of the embodiment of the present invention.In addition,, in another embodiment of the present invention, the steering order of memory management circuitry 202 can also a hardware pattern be carried out implementation.

Host interface 204 is instruction and the data that are electrically connected to memory management circuitry 202 and transmit in order to reception and identification host computer system 1000.That is to say, the instruction that host computer system 1000 transmits and data can be sent to memory management circuitry 202 by host interface 204.In the present embodiment, host interface 204 is that corresponding connector 102 is SATA interface.But, it must be appreciated and the invention is not restricted to this, host interface 204 can also be PATA interface, USB interface, IEEE 1394 interfaces, PCI Express interface, SD interface, MS interface, MMC interface, CF interface, ide interface or other applicable data transmission interfaces.

Memory interface 206 is to be electrically connected to memory management circuitry 202 and in order to access memory module 106.That is to say, the data of wanting to write to memory module 106 can be converted to 106 receptible forms of memory module via memory interface 206.

In an embodiment of the present invention, Memory Controller 104 also comprises memory buffer 252.Memory buffer 252 is to be electrically connected to memory management circuitry 202 and in order to the temporary data that come from the data and instruction of host computer system 1000 or come from memory module 106.

In an embodiment of the present invention, Memory Controller 104 also comprises electric power management circuit 254.Electric power management circuit 254 is to be electrically connected to memory management circuitry 202 and the power supply in order to control store memory storage 100.

In an embodiment of the present invention, Memory Controller 104 also comprises bug check and correcting circuit 256.Bug check and correcting circuit 256 are to be electrically connected to memory management circuitry 202 and in order to carry out a bug check and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives while writing instruction from host computer system 1000, bug check can produce corresponding bug check and correcting code (Error Checking and Correcting Code for the corresponding data that this writes instruction with correcting circuit 256; Hereinafter to be referred as: ECC Code), and memory management circuitry 202 can write to corresponding these data that write instruction in memory module 106 with corresponding error-correcting code.Afterwards, when memory management circuitry 202 can read bug check corresponding to these data and correcting code when reading out data from memory module 106 simultaneously, and bug check and correcting circuit 256 can be according to this bug check and correcting code to read data execution error correction programs.

Memory module 106 comprises first memory unit 302 and second memory unit 312.Specifically, first memory unit 302 is to be electrically connected to memory interface 206 via wafer activation pin (Chip EnablePin) 352, the first control bus (Control Bus) 354 and the first data input/output bus (DataInput/Output Bus) 356.In addition, second memory unit 312 is to be electrically connected to memory interface 206 via wafer activation pin 352, the second control bus 364 and the second data input/output bus 366.In the present embodiment, control bus can comprise RE (read enable) pin, WE (write enable) pin, CLE (command latchenable) pin, ALE (address latch enable) pin, WP (write protect) pin and R/B (ready/busy output) pin position.In addition, it must be appreciated, in the present embodiment, memory module 106 comprises 2 memory cells, but the invention is not restricted to this.In another embodiment of the present invention, the number of the memory cell of memory module 106 can be any proper number.Wherein, what deserves to be explained is that memory cell can be a memory chips in an embodiment of the present invention, and each memory chips can have the naked crystalline substance of at least one storer.

First memory unit 302 has multiple physical blocks respectively with second memory unit 312.Each physical blocks has respectively a plurality of pages, wherein can independently write and erase simultaneously corresponding to the page of same physical blocks.In more detail, physical blocks is the least unit of erasing.That is, the memory cell of being erased in the lump that each physical blocks contains minimal amount.Each physical blocks has several physical page, and the physical page minimum unit that is sequencing.In other words, physical page is the minimum unit of data writing or reading out data.Each physical page generally includes user data field and redundant area.User data field is in order to store user's data, and redundant area for example, in order to the data (, bug check and correcting code) of storage system.

It must be appreciated, in the time that this describes the running of physical blocks of memory module 106, carrying out application entity block with words such as " extraction ", " exchange ", " grouping ", " rotating " is concept in logic.That is to say, the physical location of the physical blocks of memory module 106 is not changed, but in logic the physical blocks of memory module 106 is operated.

Please refer to Fig. 4, memory management circuitry 202 can logically be grouped into the physical blocks of first memory unit 302 304 (0)～304 (R) and the physical blocks 314 (0)～314 (R) of second memory unit 312 data field 402, spare area 404, system region 406 and replace district 408.

Data field 402 is the data that come from host computer system 1000 in order to storage with the physical blocks of spare area 404.Specifically, data field 402 is the physical blocks of having stored data, and the physical blocks of spare area 404 is the physical blocks in order to replacement data district 402.Therefore, the physical blocks of spare area 404 is empty or spendable physical blocks, i.e. no record data or be labeled as invalid data useless.That is to say, the physical blocks in spare area has been performed the running of erasing, or can be performed when the physical blocks in spare area is extracted for storing the physical blocks of extracting before data the running of erasing.Therefore, the physical blocks of spare area is the physical blocks that can be used.It is worth mentioning that, in the present embodiment, memory management circuitry 202 is to carry out management entity block according to data input/output bus.Therefore, the physical blocks that belongs to first memory unit 302 in spare area 404 is only in data field 402, to belong to the physical blocks of first memory unit 302 in order to replace, and the physical blocks that belongs to second memory unit 312 in spare area 404 is only in order to replace the physical blocks that belongs to second memory unit 312 in data field 402.In another embodiment, the physical blocks in spare area 404 can share for first memory unit 302 and second memory unit 312 arbitrarily.

Belong in logic the physical blocks of system region 406 in order to register system data, wherein this system data comprises physical blocks number, the physical page number of each physical blocks etc. about the manufacturer of memory cell and model, memory cell.

Belonging in logic the physical blocks replacing in district 408 is to substitute physical blocks.For example, memory module 106 or memory cell can be reserved 4% physical blocks and use as changing in the time dispatching from the factory.That is to say, in the time that data field 402, spare area 404 are damaged with the physical blocks in system region 406, the physical blocks of reserving in replacing district 408 is in order to replacing damaged physical blocks (, bad physical blocks (bad block)).Therefore,, if replace when still having normal physical blocks in district 408 and physical blocks damage occurring, memory management circuitry 202 can be extracted normal physical blocks and change the physical blocks of damage from replace district 408.If when replacing in district 408 without normal physical blocks and physical blocks damage occurring, memory management circuitry 202 can be declared as write protection (write protect) state by memory storage apparatus 100, and data writing again.

Particularly, the quantity of the physical blocks in data field 402, spare area 404, system region 406 and replacement district 408 can be different according to different storer specifications.In addition, it must be appreciated, in the running of memory storage apparatus 100, the grouping relation that physical blocks is associated to data field 402, spare area 404, system region 406 and replacement district 408 can dynamically change.For example, in the time that physical blocks in spare area 404 is damaged and the physical blocks that is substituted district 408 while replacing, the physical blocks that originally replaces district 408 can be associated to spare area 404.

Please refer to Fig. 5, as mentioned above, data field 402 is that the mode of rotating is carried out the data that host system 1000 writes with the physical blocks of spare area 404.In the present embodiment, memory management circuitry 202 configuration logic access addresses are beneficial to carry out data access in the physical blocks of storing data in the above-mentioned mode of rotating to host computer system 1000.Particularly, memory management circuitry 202 can be grouped into logical block 510 (0)～510 (H) by provided logical bit access location, and each logical block is divided into the first logic section of corresponding the first data input/output bus 356 and the second logic section of corresponding the second data input/output bus 366.That is to say, the logical address of logical block can be arranged according to the order of input/output bus.For example, formed (by 8 logic access addresses in each logical block, logical block 510 (0) is made up of 0～7 of logic access address, logical block 510 (1) is made up of 8～15 of logical addresses, and in example by that analogy), in logical block 510 (0), the first logic section of corresponding the first data input/output bus 356 is logic access address 0～3, in logical block 510 (0), the second logic section of corresponding the second data input/output bus 366 is for being logic access address 4～7, in logical block 510 (1), the first logic section of corresponding the first data input/output bus 356 is logic access address 8～11, in logical block 510 (1), the second logic section of corresponding the second data input/output bus 366 is logic access address 12～15, and by that analogy.

In addition, memory management circuitry 202 can map to the physical blocks that belongs to first memory unit 302 in data field 402 by the first logic section of logical block, and the second logic section of logical block is mapped to the physical blocks that belongs to second memory unit 312 in data field 402.For example, for example, in the time that memory storage apparatus 100 is initialised (, format), the first logic section of logical block 510 (0)～510 (H) and the second logic section can be mapped to the physical blocks of data field 402 respectively.That is to say, logical block can be shone upon physical blocks of first memory unit 302 and a physical blocks of second memory unit.At this, memory management circuitry 202 can be that the first data input/output bus 356 is set up the first logic section-physical blocks mapping table (logical part-physical block mapping table) 602 (as shown in Figure 6), and be that the second data input/output bus 366 is set up the second logic section-physical blocks mapping table 612 (as shown in Figure 7), to record the mapping relations between logical block and physical blocks.At this, the first logic section-physical blocks mapping table is also called the first mapping table, and the second logic section-physical blocks mapping table is also called the second mapping table.

Referring to Fig. 8～Figure 10, for example, if under the mapping status shown in Fig. 6 and Fig. 7, write instruction and want data writing when belonging to the logic access address of the first logic section of logical block 510 (0) when Memory Controller 104 receives from host computer system 1000, memory management circuitry 202 can be to map to physical blocks 304 (0) and from spare area 404, extract physical blocks 304 (D+1) the physical blocks physical blocks 304 (0) of rotating as an alternative that belongs to first memory unit 302 according to the first logic section of the first logic section-physical blocks mapping table 602 recognition logic unit 510 (0) at present.But, in the time that new data is write to physical blocks 304 (D+1) by memory management circuitry 202, memory management circuitry 202 can not moved all valid data in physical blocks 304 (0) to physical blocks 304 (D+1) and the physical blocks 304 (0) of erasing at once.Specifically, (memory management circuitry 202 can write physical page valid data before by wanting in physical blocks 304 (0), the 0th physical page and the 1st physical page) be copied to physical blocks 304 (D+1) (as shown in Figure 8), and new data is write to the 2nd physical page and the 3rd physical page (as shown in Figure 9) of physical blocks 304 (D+1).Now, memory management circuitry 202 completes the running writing.For example, because the valid data in physical blocks 304 (0) likely in next operation (, write instruction) in become invalidly, therefore at once all valid data in physical blocks 304 (0) are moved to physical blocks 304 (D+1) and may be caused meaningless moving.In addition, data must write to the physical page in physical blocks in order, and therefore memory management circuitry 202 only can first be moved and want to write physical page valid data before.

In the present embodiment, temporarily maintain these mother and sons' transient state relations (, physical blocks 304 (0) and physical blocks 304 (D+1)) running be called unlatching (open) mother and child blocks, and former physical blocks is called female physical blocks and replaces physical blocks and be called fructification block.

Afterwards, in the time physical blocks 304 (0) really need to being merged with the content of physical blocks 304 (D+1), memory management circuitry 202 just can, by whole the data of physical blocks 304 (0) and physical blocks 304 (D+1) and to a physical blocks, promote the service efficiency of physical blocks thus.At this, the running that merges mother and child blocks is called closes (close) mother and child blocks.For example, as shown in figure 10, in the time closing mother and child blocks, memory management circuitry 202 can be by remaining valid data in physical blocks 304 (0) (, the 4th physical page～the K physical page) be copied to and replace physical blocks 304 (D+1), but after physical blocks 304 (0) is erased and is associated to spare area 404, meanwhile, physical blocks 304 (D+1) is associated to data field 402.That is to say, memory management circuitry 202 can remap logical block 510 (0) to physical blocks 304 (D+1) (as shown in Figure 11 A) in the first logic section-physical blocks mapping table 602.In addition, in the present embodiment, memory management circuitry 202 can be set up spare area physical blocks table (not shown) and record the physical blocks that is associated at present spare area.It is worth mentioning that, in the time opening mother and child blocks, memory management circuitry 202 need be carried out storage administration parameter with the storage space of more memory buffer 252, to record more detailed store status.For example, the valid data that these management parameters can record the first logic section that belongs to logical block 510 (0) are dispersed in which physical page that is stored in physical blocks 304 (0) and physical blocks 304 (D+1) (as shown in Figure 9).Base this, during memory storage apparatus 100 running, the group number of mother and child blocks is limited.Therefore, when memory storage apparatus 100 receive come from host computer system 1000 write instruction time, if having opened the group number of mother and child blocks reaches in limited time, memory management circuitry 202 need be closed at least one group of mother and child blocks of having opened at present (, carry out and close mother and child blocks running) and be write instruction to carry out this.

In the running shown in Fig. 8～Figure 10, memory management circuitry 202 only needs start the first data input/output bus 356 to transmit data, and completes the writing with valid data of physical blocks that belongs to first memory unit 302 and copy.Specifically, in the present embodiment, memory interface 206 is to be electrically connected to first memory unit 302 and second memory unit 312 via same wafer activation pin 352.When memory management circuitry 202 wishs, first memory unit 302 is assigned when writing instruction and assigning wafer activation instruction with activation first memory unit 302 via wafer activation pin 352, second memory unit 312 can be enabled simultaneously.Now, memory management circuitry 202 can only be assigned and write instruction and transmit data via the first data input/output bus 356 via the first control bus 354.Because the second control bus 364 and the second data input/output bus 366 can be by starts, although therefore second memory unit 312 can not carried out any running by while activation.

Similarly, under the mapping status shown in Figure 11 A and Fig. 7, write instruction and want data writing when belonging to the logic access address of the second logic section of logical block 510 (1) when Memory Controller 104 receives from host computer system 1000, memory management circuitry 202 can be to map to physical blocks 314 (1) and from spare area 404, extract physical blocks 314 (D+1) the physical blocks physical blocks 314 (1) of rotating as an alternative that belongs to second memory unit 312 according to the second logic section of the second logic section-physical blocks mapping table 612 recognition logic unit 510 (1) at present.And after mother and child blocks running is closed in execution, memory management circuitry 202 can remap logical block 510 (1) to 314 (D+1) (as shown in Figure 11 B) in the second logic section-physical blocks mapping table 612.And, writing in the process of instruction carrying out this, memory management circuitry 202 only needs start the second data input/output bus 366 to transmit data, and completes the writing with valid data of physical blocks that belongs to second memory unit 312 and copy.Same, in this process, memory management circuitry 202 can be assigned wafer activation instruction with activation second memory unit 312 via wafer activation pin 352, and first memory unit 302 also can be enabled simultaneously simultaneously.Now, memory management circuitry 202 can only be assigned and write instruction and transmit data via the second data input/output bus 366 via the second control bus 364.Because the first control bus 354 and the first data input/output bus 356 can be by starts, although therefore first memory unit 302 can not carried out any running by while activation.

Particularly, all logical block-physical blocks mapping tables (for example can be stored in memory module 106, belong to the physical blocks of system region) in, and in the time needing access memory unit, corresponding logical block-physical blocks mapping table just can be loaded in memory buffer 252 in order to reading and upgrading.

Although memory management circuitry 202 is to come diode-capacitor storage unit independently according to different data input/output bus.But multiple data input/output bus also can operate simultaneously, to promote the usefulness of memory storage apparatus 100.

For example, write instruction and want data writing when belonging to the logic access address of the first logic section of logical block 510 (0) when Memory Controller 104 receives from host computer system 1000, memory management circuitry 202 can judge whether first need in the physical blocks of first memory unit 302, carry out valid data and copy (for example, the above-mentioned mother and child blocks of closing operates).Particularly, in the time that memory management circuitry 202 judges that first need carry out valid data in the physical blocks of first memory unit 302 copies, memory management circuitry 202 can also judge that in the physical blocks of second memory unit 312, whether needing to carry out valid data copies.Copy if need to carry out valid data in the physical blocks of second memory unit 312, memory management circuitry 202 can be carried out synchronous operation, copies to carry out valid data in first memory unit 302 and second memory unit 312.

Specifically, in this synchronous operation, first, memory management circuitry 202 can be via wafer activation pin 352 activation first memory unit 302 and second memory unit 312 simultaneously.Then, memory management circuitry 202 can be assigned the first steering order to first memory unit 302 via the first control bus 354, assigns the second steering order to second memory unit 312 via the second control bus 364 simultaneously.Afterwards, valid data copy and can in first memory unit 302 and second memory unit 312, be performed with the method for synchronization.For example, in the time that execution valid data copy, belong to respectively first memory unit 302 and transfer to memory buffer 252 via the first data input/output bus 356 and the second data input/output bus 366 discriminably with the valid data of second memory unit 312, and be written into again corresponding physical page afterwards.

Please refer to Figure 12, when receiving from host computer system 1000 when writing instruction and writing the data of instruction with corresponding this, in step S1201, memory management circuitry 202 can write the logic access address that instruction comprises according to this and identify corresponding logical block and logic section.And, in step S1203 memory management circuitry 202 according to the logical block of identifying and logic section be written into corresponding logical block-physical blocks mapping table with related management parameter to identify corresponding memory cell and data input/output bus.

Afterwards, in step S1205, memory management circuitry 202 can judge whether that needing first between the physical blocks of corresponding memory cell, to carry out valid data copies.If when first carrying out valid data between the physical blocks of corresponding memory cell and copy, in step S1207, memory management circuitry 202 can be via wafer activation pin (, wafer activation pin 352) assign wafer activation instruction, and assign steering order via corresponding control bus.Afterwards, in step S1209, memory management circuitry 202 only transmits with corresponding data input/output bus the data of wanting to write.

If while judging that in step S1205 needing first to carry out valid data between the physical blocks of corresponding memory cell copies, in step S1211, memory management circuitry 202 can judge that whether needing to be performed valid data between the physical blocks of other memory cells copies.

If when also needing to be performed valid data copy between the physical blocks of other memory cells, in step S1213, memory management circuitry 202 can be written into logical block-physical blocks mapping table and the related management parameter of corresponding other memory cells.Afterwards, in step S1215, memory management circuitry 202 can be assigned wafer activation instruction via wafer activation pin (, wafer activation pin 352).Then, in step S1217, memory management circuitry 202 can be assigned steering order via different control buss respectively and copies synchronously to carry out valid data in multiple memory cells, and step S1207 can be performed afterwards.

If when being performed valid data and copying, in step S1219, memory management circuitry 202 can be assigned wafer activation instruction via wafer activation pin (, wafer activation pin 352) between the physical blocks of other memory cells.And in step S1221, memory management circuitry 202 can be assigned steering order via corresponding control bus and copies to carry out valid data in corresponding memory cell, and step S1207 can be performed afterwards.

The second embodiment

The memory storage apparatus of the second embodiment is the memory storage apparatus that is same as the first embodiment in essence, below will describe for difference part.

Please refer to Figure 13, memory storage apparatus 1300 comprises connector 102, Memory Controller 1304 and memory module 106.

Memory Controller 1304 can be carried out multiple logic locks or the steering order with hardware pattern or firmware pattern implementation, and in memory module 106, carries out the runnings such as writing, read and erase of data according to the instruction of host computer system 1000.Particularly, Memory Controller 1304 is in order to carry out according to data access mechanism and the memory management mechanism of the present embodiment.

Memory Controller 1304 comprises memory management circuitry 1302, host interface 204, memory interface 206, memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.

In the present embodiment, the first memory unit 302 of memory module 106 is to be electrically connected to memory interface 206 via the first wafer activation pin 1352, control bus 1354 and the first data input/output bus 1356.In addition, the second memory unit 312 of memory module 106 is to be electrically connected to memory interface 206 via the second wafer activation pin 1362, control bus 1354 and the second data input/output bus 1366.

Memory management circuitry 1302 is in order to the overall operation of control store controller 1304.Specifically, memory management circuitry 1302 has multiple steering orders, and in the time that memory storage apparatus 1300 operates, these steering orders can be performed with the data access mechanism according to the present embodiment carrys out diode-capacitor storage module 106 with memory management mechanism.

In the present embodiment, memory management circuitry 1302 also can execution graph 4～Figure 10 and Figure 11 A and 11B shown in running carry out diode-capacitor storage module 106.But, because memory module 106 and the electric connection mode of Memory Controller 1304 are different from the first embodiment, base this, memory management circuitry 1302 can be assigned instruction in a different manner to complete the running shown in Fig. 4～Figure 10 and Figure 11 A and Figure 11 B.

For example, in the running shown in execution graph 8～Figure 10, memory management circuitry 1302 also only needs start the first data input/output bus 1356 to transmit data, and completes the writing with valid data of physical blocks that belongs to first memory unit 302 and copy.But memory management circuitry 1302 is first to assign the first wafer activation instruction with activation first memory unit 302 via the first wafer activation pin 1352.Afterwards, memory management circuitry 1302 can be assigned steering order via control bus 1354.At this, memory interface 206 is to be electrically connected to first memory unit 302 and second memory unit 312 via same control bus 1354, and the steering order therefore assigned can be transferred to first memory unit 302 and second memory unit 312 simultaneously.But because second memory unit 312 is not enabled, therefore this steering order can be to the 312 generation effects of second memory unit.Now, memory management circuitry 1302 can be only transmitted data to complete the instruction that writes for the physical blocks of first memory unit 302 via the first data input/output bus 1356.

In addition,, in the time that above-mentioned synchronous operation is performed, first, memory management circuitry 1302 can be assigned the first wafer activation instruction and assign the second wafer activation instruction via the second wafer activation pin 1362 via the first wafer activation pin 1352.Then, memory management circuitry 1302 can be assigned identical steering order to first memory unit 302 and second memory unit 312 via control bus 1354.Afterwards, valid data copy and can in first memory unit 302 and second memory unit 312, be performed with the method for synchronization.For example, in the time that execution valid data copy, belong to respectively first memory unit 302 and transfer to memory buffer 252 via the first data input/output bus 1356 and the second data input/output bus 1366 discriminably with the valid data of second memory unit 312, and be written into again corresponding physical page afterwards.

Please refer to Figure 14, when receiving from host computer system 1000 when writing instruction and writing the data of instruction with corresponding this, in step S1401, memory management circuitry 1302 can write the logic access address that instruction comprises according to this and identify corresponding logical block and logic section.And, in step S1403 memory management circuitry 1302 according to the logical block of identifying and logic section be written into corresponding logical block-physical blocks mapping table with related management parameter to identify corresponding memory cell and data input/output bus.

Afterwards, in step S1405, memory management circuitry 1302 can judge whether that needing first between the physical blocks of corresponding memory cell, to carry out valid data copies.If when first carrying out valid data between the physical blocks of corresponding memory cell and copy, in step S1407, memory management circuitry 1302 can be assigned wafer activation instruction via corresponding wafer activation pin, and assign steering order via control bus (, control bus 1354).Afterwards, in step S1409, memory management circuitry 1302 only transmits with corresponding data input/output bus the data of wanting to write.

If while judging that in step S1405 needing first to carry out valid data between the physical blocks of corresponding memory cell copies, in step S1411, memory management circuitry 1302 can judge that whether needing to be performed valid data between the physical blocks of other memory cells copies.

If when also needing to be performed valid data copy between the physical blocks of other memory cells, in step S1413, memory management circuitry 1302 can be written into logical block-physical blocks mapping table and the related management parameter of corresponding other memory cells.Afterwards, in step S1415, memory management circuitry 1302 can be assigned wafer activation instruction via different wafer activation pins respectively and need be performed with activation the memory cell that valid data copy.Then, in step S1417, memory management circuitry 1302 can be via control bus (, control bus 1354) assign same steering order and copy synchronously to carry out valid data in multiple memory cells, and step S1407 can be performed afterwards.

If when being performed valid data and copying, in step S1419, memory management circuitry 1302 can be assigned the memory cell of wafer activation instruction with corresponding this host command of activation via corresponding wafer activation pin between the physical blocks of other memory cells.And in step S1421, memory management circuitry 1302 can be assigned steering order via control bus (, control bus 1354) and copies to carry out valid data in corresponding memory cell, and step S1407 can be performed afterwards.

The 3rd embodiment

The memory storage apparatus of the 3rd embodiment is the memory storage apparatus that is same as the first embodiment in essence, below will describe for difference part.

Please refer to Figure 15, memory storage apparatus 1500 comprises connector 102, Memory Controller 1504 and memory module 106.

Memory Controller 1504 can be carried out multiple logic locks or the steering order with hardware pattern or firmware pattern implementation, and in memory module 106, carries out the runnings such as writing, read and erase of data according to the instruction of host computer system 1000.Particularly, Memory Controller 1504 is in order to carry out according to data access mechanism and the memory management mechanism of the present embodiment.

Memory Controller 1504 comprises memory management circuitry 1502, host interface 204, memory interface 206, memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.

In the present embodiment, the first memory unit 302 of memory module 106 is to be electrically connected to memory interface 206 via wafer activation pin 1552, control bus 1554 and the first data input/output bus 1556.In addition, the second memory unit 312 of memory module 106 is to be electrically connected to memory interface 206 via wafer activation pin 1552, control bus 1554 and the second data input/output bus 1566.

Memory management circuitry 1502 is in order to the overall operation of control store controller 1504.Specifically, memory management circuitry 1502 has multiple steering orders, and in the time that memory storage apparatus 1500 operates, these steering orders can be performed with the data access mechanism according to the present embodiment carrys out diode-capacitor storage module 106 with memory management mechanism.

In the present embodiment, memory management circuitry 1502 also can execution graph 4～Figure 10 and Figure 11 A and Figure 11 B shown in running carry out diode-capacitor storage module 106.But, because memory module 106 and the electric connection mode of Memory Controller 1504 are different from the first embodiment, base this, memory management circuitry 1502 can be assigned instruction in a different manner to complete the running shown in Fig. 4～Figure 10 and Figure 11 A and Figure 11 B.

For example, in the running shown in execution graph 8～Figure 10, memory management circuitry 1502 also only needs start the first data input/output bus 1556 to transmit data, and completes the writing with valid data of physical blocks that belongs to first memory unit 302 and copy.But memory management circuitry 1502 is first to assign wafer activation instruction with activation first memory unit 302 via wafer activation pin 1552.Now, this wafer activation instruction also can activation second memory unit 312.Afterwards, memory management circuitry 1502 can be assigned steering order via control bus 1554.Now, this steering order also can be sent to second memory unit 312.Then, memory management circuitry 1502 can be transmitted data to complete the instruction that writes for the physical blocks of first memory unit 302 via the first data input/output bus 1556, and transmits empty data so that second memory unit is carried out to invalid writing via the second data input/output bus 1566.In the present embodiment, empty data can be one and are all " 1 " data stream, maybe can allow memory management circuitry 1502 regard as insignificant Data Styles.

In addition,, in the time that above-mentioned synchronous operation is performed, first, memory management circuitry 1502 can be assigned wafer activation instruction with while activation first memory unit 302 and second memory unit 312 via wafer activation pin 1552.Then, memory management circuitry 1502 can be assigned same steering order to first memory unit 302 and second memory unit 312 via control bus 1554.Afterwards, valid data copy and can in first memory unit 302 and second memory unit 312, be performed with the method for synchronization.For example, in the time that execution valid data copy, belong to respectively first memory unit 302 and transfer to memory buffer 252 via the first data input/output bus 1556 and the second data input/output bus 1566 discriminably with the valid data of second memory unit 312, and be written into again corresponding physical page afterwards.

Please refer to Figure 16, when receiving from host computer system 1000 when writing instruction and writing the data of instruction with corresponding this, in step S1601, memory management circuitry 1502 can write the logic access address that instruction comprises according to this and identify corresponding logical block and logic section.And, in step S1603 memory management circuitry 1502 according to the logical block of identifying and logic section be written into corresponding logical block-physical blocks mapping table with related management parameter to identify corresponding memory cell and data input/output bus.

Afterwards, in step S1605, memory management circuitry 1502 can judge whether that needing first between the physical blocks of corresponding memory cell, to carry out valid data copies.If when first carrying out valid data between the physical blocks of corresponding memory cell and copy, in step S1607, memory management circuitry 1502 can be via wafer activation pin (, wafer activation pin position 1552) assign wafer activation instruction, Bing and assign steering order via control bus (, control bus 1554).Afterwards, in step S1609, memory management circuitry 1502 only transmits with corresponding data input/output bus the data of wanting to write, and in other data input/output bus, transmits empty data to carry out invalid writing.

If while judging that in step S1605 needing first to carry out valid data between the physical blocks of corresponding memory cell copies, in step S1611, memory management circuitry 1502 can judge that whether needing to be performed valid data between the physical blocks of other memory cells copies.

If when also needing to be performed valid data copy between the physical blocks of other memory cells, in step S1613, memory management circuitry 1502 can be written into logical block-physical blocks mapping table and the related management parameter of corresponding other memory cells.Afterwards, in step S1615, memory management circuitry 1502 can be assigned wafer activation instruction via wafer activation pin (, wafer activation pin position 1552).But after, in step S1617, memory management circuitry 1502 can be via control bus (, control bus 1554) assign steering order and copy synchronously to carry out valid data in multiple memory cells, and step S1607 can be performed afterwards.

If when being performed valid data and copying, in step S1619, memory management circuitry 1502 can be assigned wafer activation instruction via wafer activation pin (, wafer activation pin position 1552) between the physical blocks of other memory cells.And, in step S1621, memory management circuitry 1502 can be via control bus (, control bus 1554) valid data copy and in other memory cells, carry out invalid access to carry out in corresponding memory cell to assign steering order, and step S1607 can be performed afterwards.

The 4th embodiment

The memory storage apparatus of the 4th embodiment is the memory storage apparatus that is same as the first embodiment in essence, below will describe for difference part.

Please refer to Figure 17, memory storage apparatus 1700 comprises connector 102, Memory Controller 1704 and memory module 106.

Memory Controller 1704 can be carried out multiple logic locks or the steering order with hardware pattern or firmware pattern implementation, and in memory module 106, carries out the runnings such as writing, read and erase of data according to the instruction of host computer system 1000.Particularly, Memory Controller 1704 is in order to carry out according to data access mechanism and the memory management mechanism of the present embodiment.

Memory Controller 1704 comprises memory management circuitry 1702, host interface 204, memory interface 206, memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.

In the present embodiment, the first memory unit 302 of memory module 106 is to be electrically connected to memory interface 206 via the first wafer activation pin 1752, the first control bus 1754 and the first data input/output bus 1756.In addition, the second memory unit 312 of memory module 106 is to be electrically connected to memory interface 206 via the second wafer activation pin 1762, the second control bus 1764 and the second data input/output bus 1766.

Memory management circuitry 1702 is in order to the overall operation of control store controller 1704.Specifically, memory management circuitry 1702 has multiple steering orders, and in the time that memory storage apparatus 1700 operates, these steering orders can be performed with the data access mechanism according to the present embodiment carrys out diode-capacitor storage module 106 with memory management mechanism.

In the present embodiment, memory management circuitry 1702 also can execution graph 4～Figure 10 and Figure 11 A and Figure 11 B shown in running carry out diode-capacitor storage module 106.But, because memory module 106 and the electric connection mode of Memory Controller 1704 are different from the first embodiment, base this, memory management circuitry 1702 can be assigned instruction in a different manner to complete the running shown in Fig. 4～Figure 10 and Figure 11 A and Figure 11 B.

For example, in the running shown in execution graph 8～Figure 10, memory management circuitry 1702 also only needs start the first data input/output bus 1756 to transmit data, and completes the writing with valid data of physical blocks that belongs to first memory unit 302 and copy.But memory management circuitry 1702 is first to assign the first wafer activation instruction with activation first memory unit 302 via the first wafer activation pin 1752.Afterwards, memory management circuitry 1702 can be assigned steering order via the first control bus 1754.Now, memory management circuitry 1702 can be only transmitted data to complete the instruction that writes for the physical blocks of first memory unit 302 via the first data input/output bus 1756.

In addition,, in the time that above-mentioned synchronous operation is performed, first, memory management circuitry 1702 can be assigned the first wafer activation instruction and assign the second wafer activation instruction via the second wafer activation pin 1762 via the first wafer activation pin 1752.Then, memory management circuitry 1702 can be assigned steering order to first memory unit 302 and via the second control bus 1764 and second memory unit 312 via the first control bus 1754.Afterwards, valid data copy and can in first memory unit 302 and second memory unit 312, be performed with the method for synchronization.For example, in the time that execution valid data copy, belong to respectively first memory unit 302 and transfer to memory buffer 252 via the first data input/output bus 1756 and the second data input/output bus 1766 discriminably with the valid data of second memory unit 312, and be written into again corresponding physical page afterwards.

Please refer to Figure 18, when receiving from host computer system 1000 when writing instruction and writing the data of instruction with corresponding this, in step S1801, memory management circuitry 1702 can write the logic access address that instruction comprises according to this and identify corresponding logical block and logic section.And, in step S1803 memory management circuitry 1702 according to the logical block of identifying and logic section be written into corresponding logical block-physical blocks mapping table with related management parameter to identify corresponding memory cell and data input/output bus.

Afterwards, in step S1805, memory management circuitry 1702 can judge whether that needing first between the physical blocks of corresponding memory cell, to carry out valid data copies.If when first carrying out valid data between the physical blocks of corresponding memory cell and copy, in step S1807, memory management circuitry 1702 can be assigned wafer activation instruction via corresponding wafer activation pin, and assigns steering order via corresponding control bus.Afterwards, in step S1809, memory management circuitry 1702 only transmits with corresponding data input/output bus the data of wanting to write.

If while judging that in step S1805 needing first to carry out valid data between the physical blocks of corresponding memory cell copies, in step S1811, memory management circuitry 1702 can judge that whether needing to be performed valid data between the physical blocks of other memory cells copies.

If when also needing to be performed valid data copy between the physical blocks of other memory cells, in step S1813, memory management circuitry 1702 can be written into logical block-physical blocks mapping table and the related management parameter of corresponding other memory cells.Afterwards, in step S1815, memory management circuitry 1702 can be assigned wafer activation instruction via different wafer activation pins respectively and need be performed with activation the memory cell that valid data copy.Then, in step S1817, memory management circuitry 1702 can be assigned steering order via different control buss respectively and copies synchronously to carry out valid data in multiple memory cells, and step S1807 can be performed afterwards.

If when being performed valid data and copying, in step S1819, memory management circuitry 1702 can be assigned the memory cell of wafer activation instruction with corresponding this host command of activation via corresponding wafer activation pin between the physical blocks of other memory cells.And in step S1821, memory management circuitry 1702 can be assigned steering order via corresponding control bus and copies to carry out valid data in corresponding memory cell, and step S1807 can be performed afterwards.

In sum, the embodiment of the present invention is to carry out according to data input/output bus the configuration mapping table and management parameter that management entity block Bing is corresponding.Therefore, the multiple physical blocks that map to same logical block can operate independently, can shorten thus and carry out the above-mentioned time of copying valid data, promote the usefulness of memory storage.In addition, physical page is performed the above-mentioned number of times that copies valid data and can significantly reduces, and extends thus the life-span of memory storage.

Although the present invention discloses as above with embodiment; but it is not in order to limit the present invention, any affiliated those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended claim person of defining.

Claims

1. a memory management and wiring method, be used for managing a memory module, wherein said memory module comprises a first memory unit, one first input/output bus for described first memory unit, a second memory unit and one second input/output bus for described second memory unit, described first memory unit and described second memory unit have multiple physical blocks, and described memory management and wiring method comprise:

Configure multiple logical blocks, and each logical block is divided into corresponding one first logic section of described the first input/output bus and one second logic section of corresponding described the second input/output bus;

At least a portion by described multiple logical unit mappings to described multiple physical blocks of described first memory unit and described second memory unit, described the second logic section that wherein described first logic section of each logical block is shone upon one of them and each logical block of described multiple physical blocks of described first memory unit is shone upon one of them of described multiple physical blocks of described second memory unit;

Set up one first mapping table of corresponding described the first input/output bus to record one first mapping relations between described multiple first logic section of described multiple logical blocks and described multiple physical blocks of described first memory unit;

Set up one second mapping table of corresponding described the second input/output bus to record one second mapping relations between described multiple second logic section of described multiple logical blocks and described multiple physical blocks of described second memory unit;

Receive data that write instruction and corresponding said write instruction, wherein said data want to be written into one of them of described multiple the first logic section of described multiple logical blocks; And

Described the first mapping table according to corresponding described the first input/output bus only uses described the first input/output bus the data of corresponding said write instruction are write in described first memory unit;

Judge whether need be between described multiple physical blocks of described first memory unit copy data;

If need be between described multiple physical blocks of described first memory unit when copy data, judge whether need be between described multiple physical blocks of described second memory unit copy data; And

If need be between described multiple physical blocks of described second memory unit when copy data, according to described the first mapping table at copy data between described multiple physical blocks of described first memory unit simultaneously according to described the second mapping table copy data between described multiple physical blocks of described second memory unit.

2. memory management according to claim 1 and wiring method, wherein only uses described the first input/output bus to comprise with the step that the data of corresponding said write instruction are write in described first memory unit according to described first mapping table of corresponding described the first input/output bus:

Assign a wafer activation instruction, first memory unit and described second memory unit described in wherein said wafer activation instruction activation simultaneously;

Assign one first steering order to described first memory unit; And

According to described first mapping table of corresponding described the first input/output bus via described the first input/output bus so that the data of corresponding said write instruction are write in described first memory unit.

3. memory management according to claim 1 and wiring method wherein comprises according to the step of described the second mapping table copy data between described multiple physical blocks of described second memory unit at copy data between described multiple physical blocks of described first memory unit according to described the first mapping table simultaneously:

According to described the first mapping table assign one first steering order give described first memory unit with copy data between the described multiple physical blocks in described first memory unit; And

According to described the second mapping table assign one second steering order give described second memory unit with copy data between the described multiple physical blocks in described second memory unit.

4. memory management according to claim 3 and wiring method, also comprises:

If during without copy data between described multiple physical blocks of described second memory unit, assign described wafer activation instruction, and according to described the first mapping table assign described the first steering order give described first memory unit with copy data between the described multiple physical blocks in described first memory unit.

5. memory management according to claim 1 and wiring method, wherein only uses described the first input/output bus to comprise with the step that the data of corresponding said write instruction are write in described first memory unit according to described first mapping table of corresponding described the first input/output bus:

Assign one first wafer activation instruction to described first memory unit;

Assign a steering order, wherein said steering order is sent to described first memory unit and described second memory unit simultaneously; And

6. memory management according to claim 1 and wiring method wherein comprises according to the step of described the second mapping table copy data between described multiple physical blocks of described second memory unit at copy data between described multiple physical blocks of described first memory unit according to described the first mapping table simultaneously:

Assign one first wafer activation instruction to described first memory unit; Assign one second wafer activation instruction to described second memory unit; And assign a steering order with copy data between the described multiple physical blocks in described first memory unit and between described multiple physical blocks of described second memory unit according to described the first mapping table and described the second mapping table, wherein said steering order is sent to described first memory unit and described second memory unit simultaneously.

7. memory management according to claim 6 and wiring method, also comprises:

If during without copy data between described multiple physical blocks of described second memory unit, assign described the first wafer activation instruction give described first memory unit, and according to described the first mapping table assign described steering order give described first memory unit with copy data between the described multiple physical blocks in described first memory unit.

8. memory management according to claim 1 and wiring method, wherein only uses described the first input/output bus to comprise with the step that the data of corresponding said write instruction are write in described first memory unit according to described first mapping table of corresponding described the first input/output bus:

According to described first mapping table of corresponding described the first input/output bus via described the first input/output bus so that the data of corresponding said write instruction are write in described first memory unit, and transmitted data to described second memory unit to carry out invalid writing.

9. memory management according to claim 1 and wiring method wherein comprises according to the step of described the second mapping table copy data between described multiple physical blocks of described second memory unit at copy data between described multiple physical blocks of described first memory unit according to described the first mapping table simultaneously:

Assign a wafer activation instruction, first memory unit and described second memory unit described in wherein said wafer activation instruction activation simultaneously; And

Assign a steering order with copy data between the described multiple physical blocks in described first memory unit and between described multiple physical blocks of described second memory unit according to described the first mapping table and described the second mapping table, wherein said steering order is sent to described first memory unit and described second memory unit simultaneously.

10. memory management according to claim 9 and wiring method, also comprises:

If during without copy data between described multiple physical blocks of described second memory unit, assign described wafer activation instruction, and assign described steering order with copy data between the described multiple physical blocks in described first memory unit and in described second memory unit, carry out an invalid access according to described the first mapping table.

11. memory management according to claim 1 and wiring methods, wherein only use described the first input/output bus to comprise with the step that the data of corresponding said write instruction are write in described first memory unit according to described first mapping table of corresponding described the first input/output bus:

Assign one first wafer activation instruction to described first memory unit;

Assign one first steering order to described first memory unit; And

12. memory management according to claim 1 and wiring methods wherein comprise according to the step of described the second mapping table copy data between described multiple physical blocks of described second memory unit at copy data between described multiple physical blocks of described first memory unit according to described the first mapping table simultaneously:

Assign one first wafer activation instruction to described first memory unit;

Assign one second wafer activation instruction to described second memory unit;

According to described the first mapping table assign one first steering order give described first memory unit with copy data between the described multiple physical blocks in described first memory unit; And according to described the second mapping table assign one second steering order give described second memory unit with copy data between the described multiple physical blocks in described second memory unit.

13. memory management according to claim 12 and wiring methods, also comprise:

If during without copy data between described multiple physical blocks of described second memory unit, assign described the first wafer activation instruction give described first memory unit, and according to described the first mapping table assign described the first steering order give described first memory unit with copy data between the described multiple physical blocks in described first memory unit.

14. 1 kinds of memory managements and writing system, be used for managing a memory module, wherein said memory module comprises a first memory unit, one first input/output bus for described first memory unit, a second memory unit and one second input/output bus for described second memory unit, described first memory unit and described second memory unit have multiple physical blocks, and described memory management and writing system comprise:

One first module, in order to configure multiple logical blocks, and divides into corresponding one first logic section of described the first input/output bus and one second logic section of corresponding described the second input/output bus by each logical block;

One second module, in order at least a portion to described multiple physical blocks of described first memory unit and described second memory unit by described multiple logical unit mappings, described the second logic section that wherein described first logic section of each logical block is shone upon one of them and each logical block of described multiple physical blocks of described first memory unit is shone upon one of them of described multiple physical blocks of described second memory unit;

One the 3rd module, in order to one first mapping table of setting up corresponding described the first input/output bus to record one first mapping relations between described multiple first logic section of described multiple logical blocks and described multiple physical blocks of described first memory unit;

One four module, in order to one second mapping table of setting up corresponding described the second input/output bus to record one second mapping relations between described multiple second logic section of described multiple logical blocks and described multiple physical blocks of described second memory unit;

One the 5th module, in order to receive data that write instruction and corresponding said write instruction, wherein said data want to be written into one of them of described multiple the first logic section of described multiple logical blocks;

One the 6th module, in order to only to be used described the first input/output bus the data of corresponding said write instruction are write in described first memory unit according to described first mapping table of corresponding described the first input/output bus;

One the 7th module, in order to judge whether need be between described multiple physical blocks of described first memory unit copy data;

One the 8th module, if in order to need be between described multiple physical blocks of described first memory unit when copy data, judge whether need be between described multiple physical blocks of described second memory unit copy data; And

One the 9th module, if in order to need be between described multiple physical blocks of described second memory unit when copy data, according to described the first mapping table at copy data between described multiple physical blocks of described first memory unit simultaneously according to described the second mapping table copy data between described multiple physical blocks of described second memory unit.

15. memory management according to claim 14 and writing systems,

Wherein said the 6th module is assigned a wafer activation instruction, first memory unit and described second memory unit described in wherein said wafer activation instruction activation simultaneously,

Wherein said the 6th module assign one first steering order to described first memory unit and according to described first mapping table of corresponding described the first input/output bus via described the first input/output bus so that the data of corresponding said write instruction are write in described first memory unit.

16. memory management according to claim 14 and writing systems,

Wherein said the 9th module is assigned a wafer activation instruction, according to described the first mapping table assign one first steering order to described first memory unit with copy data between the described multiple physical blocks in described first memory unit and according to described the second mapping table assign one second steering order to described second memory unit with copy data between the described multiple physical blocks in described second memory unit, first memory unit and described second memory unit described in wherein said wafer activation instruction activation simultaneously.

17. memory management according to claim 16 and writing systems, also comprise:

The tenth module, if when without copy data between described multiple physical blocks of described second memory unit, assign described wafer activation instruction, and according to described the first mapping table assign described the first steering order give described first memory unit with copy data between the described multiple physical blocks in described first memory unit.

18. memory management according to claim 14 and writing systems,

Wherein said the 6th module is assigned one first wafer activation instruction to described first memory unit and is assigned a steering order, and wherein said steering order is sent to described first memory unit and described second memory unit simultaneously,

Wherein said the 6th module according to described first mapping table of described the first input/output bus of correspondence via described the first input/output bus so that the data of corresponding said write instruction are write in described first memory unit.

19. memory management according to claim 14 and writing systems,

Wherein said the 9th module is assigned one first wafer activation instruction to described first memory unit, assign one second wafer activation instruction to described second memory unit, and assign a steering order with copy data between the described multiple physical blocks in described first memory unit and between described multiple physical blocks of described second memory unit according to described the first mapping table and described the second mapping table, wherein said steering order is sent to described first memory unit and described second memory unit simultaneously.

20. memory management according to claim 19 and writing systems, also comprise:

The 11 module, if when without copy data between described multiple physical blocks of described second memory unit, assign described the first wafer activation instruction give described first memory unit, and according to described the first mapping table assign described steering order give described first memory unit with copy data between the described multiple physical blocks in described first memory unit.

21. memory management according to claim 14 and writing systems,

Wherein said the 6th module is assigned a steering order, and wherein said steering order is sent to described first memory unit and described second memory unit simultaneously,

Wherein said the 6th module according to described first mapping table of described the first input/output bus of correspondence via described the first input/output bus so that the data of corresponding said write instruction are write in described first memory unit, and transmitted data to described second memory unit to carry out invalid writing.

22. memory management according to claim 14 and writing systems,

Wherein said the 9th module is assigned a wafer activation instruction, and assign a steering order with copy data between the described multiple physical blocks in described first memory unit and between described multiple physical blocks of described second memory unit according to described the first mapping table and described the second mapping table, first memory unit and described second memory unit and described steering order are sent to described first memory unit and described second memory unit simultaneously described in wherein said wafer activation instruction while activation.

23. memory management according to claim 22 and writing systems, also comprise:

The 12 module, if when without copy data between described multiple physical blocks of described second memory unit, assign described wafer activation instruction, and assign described steering order with copy data between the described multiple physical blocks in described first memory unit and in described second memory unit, carry out an invalid access according to described the first mapping table.

24. memory management according to claim 14 and writing systems,

Wherein said the 6th module is assigned one first wafer activation instruction to described first memory unit, assign one first steering order to described first memory unit, and according to described first mapping table of corresponding described the first input/output bus via described the first input/output bus so that the data of corresponding said write instruction are write in described first memory unit.

25. memory management according to claim 14 and writing systems,

Wherein said the 9th module is assigned one first wafer activation instruction to described first memory unit, assign one second wafer activation instruction to described second memory unit, according to described the first mapping table assign one first steering order give described first memory unit with copy data between the described multiple physical blocks in described first memory unit, and according to described the second mapping table assign one second steering order give described second memory unit with copy data between the described multiple physical blocks in described second memory unit.

26. memory management according to claim 25 and writing systems, also comprise:

The 13 module, if when without copy data between described multiple physical blocks of described second memory unit, assign described the first wafer activation instruction give described first memory unit, and according to described the first mapping table assign described the first steering order give described first memory unit with copy data between the described multiple physical blocks in described first memory unit.