CN102148604B - Signal processing circuit and method thereof - Google Patents
Signal processing circuit and method thereof Download PDFInfo
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- CN102148604B CN102148604B CN 201010128828 CN201010128828A CN102148604B CN 102148604 B CN102148604 B CN 102148604B CN 201010128828 CN201010128828 CN 201010128828 CN 201010128828 A CN201010128828 A CN 201010128828A CN 102148604 B CN102148604 B CN 102148604B
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Abstract
The invention discloses a signal processing circuit and method. The signal processing circuit comprises a signal receiving circuit, an analogue/digital (A/D) converter, a signal analysis circuit and a base frequency circuit, wherein the signal receiving circuit is used for receiving a radio frequency (RF) signal, adjusting the RF signal according to a gain value, and converting the RF signal into an analogue signal; the analogue/digital (A/D) converter is coupled to the signal receiving circuit and used for converting the analogue signal into a digital signal; the signal analysis circuit is coupled to the A/D converter and the signal receiving circuit and used for producing the gain value and a reference value according to the digital signal; and the base frequency circuit is coupled to the A/D converter and the signal analysis circuit and used for performing a carrier frequency offset compensation on the digital signal according to the reference value.
Description
Technical field
The invention relates to a kind of signal processing circuit and method thereof, particularly carrier frequency shift compensating circuit and the method thereof of relevant a kind of signal processing circuit.
Background technology
In wireless transmission, because transmission end is different apart from distance from receiving terminal, cause receiving terminal likely to receive the signal that energy varies in size, therefore need by automatic gain control circuit (auto-gain control, AGC) adjust the gain of receiving terminal, can correctly receive the signal that energy varies in size.
Fig. 1, for the functional block diagram of existing signal processing circuit 10, comprising: signal receiving circuit 120, analog/digital converter (analog-to-digital convertor, ADC) 140, automatic gain control circuit 160 and baseband circuit 180.Automatic gain control circuit 160 comprises signal deteching circuit 164.Baseband circuit 180 comprises carrier frequency shift compensating circuit 184.Fig. 2 is corresponding existing signal processing method flow chart, please reference in the lump.
If signal is still saturation condition, enter step 240, automatic gain control circuit 160 reduces gain, then gets back to step 230, and whether automatic gain control circuit 160 detection signal again is saturated.Repeat above-mentioned steps until signal has reached the unsaturation state, enter step 260, whether signal deteching circuit 164 detection signals are the echo signal that wish receives.If not the echo signal that wish receives is got back to step 210, wait for the next signal that receives.If the echo signal that wish receives, enter the radio frequency stable state of step 270 and can close automatic gain control circuit 160 to save the energy.Follow step 280, carrier frequency shift compensating circuit 184 detected carrier frequency offsets (carrier frequency offset, CFO).Step 290, carrier frequency shift compensating circuit 184 carries out the carrier frequency offset compensation.Wherein carrier frequency shift compensating circuit 184 is bases
carry out the detected carrier frequency offset and carry out the carrier frequency shift compensation, wherein r (t) is for receiving signal, and N is the cycle that receives signal.
The sequential that Fig. 3 is IEEE 802.11a/g/n wireless network protocol is utilized schematic diagram.For the signal that can receive that energy varies in size, automatic gain control circuit 160 is default is made as maximum by the receiving terminal gain, when running into the little signal of energy, because automatic gain control circuit 160 is default, is that gain is made as to maximum, so can correctly receive signal.When running into the large signal of energy, because automatic gain control circuit 160 is default, be that gain is made as to maximum, so the signal of receiving can present saturated situation, once signal is saturated, can allow the source that receiving terminal can't resoluting signal, so automatic gain control circuit 160 need to slowly reduce gain, until just do input when unsaturated, this step can be used up a lot of time, if the signal all too is large, and script sequential t
1to t
7the signal analysis time can be used for not doing automatic gain adjustment and input, and then affect the estimation of 184 pairs of carrier frequency offsets of carrier frequency shift compensating circuit.
Therefore, very eagerly need to develop a kind ofly can have more time to process saturation signal, also can simultaneously correct demodulation with signal processing circuit and the method thereof of carrier frequency offset signal.
Summary of the invention
One of purpose of the present invention is to provide a kind of can have more time to process saturation signal, also correctly demodulation with signal processing circuit and the method thereof of carrier frequency offset signal.
The present invention proposes a kind of signal processing circuit, comprising: a signal receiving circuit, and in order to receive a radiofrequency signal, according to a yield value, adjust this radiofrequency signal, and this radiofrequency signal is converted to an analog signal; One analog/digital converter, be coupled to this signal receiving circuit, in order to being a digital signal by this analog signal conversion; One signal evaluation circuit, be coupled to this analog/digital converter and this signal receiving circuit, in order to according to this digital signal to produce this yield value and a reference value; And a baseband circuit, be coupled to this analog/digital converter and this signal evaluation circuit, in order to according to this reference value, this digital signal is carried out to a carrier frequency shift compensation.
The present invention also proposes a kind of signal processing method, comprising: receive a signal; Detect this signal and take and judge the echo signal whether this signal receives as wish, and produce a reference value simultaneously; And according to this reference value, this signal is carried out to a carrier frequency shift compensation.
The present invention compared to the useful technique effect of prior art is: signal processing circuit of the present invention and method thereof can be saved the time of carrier frequency offset estimation, and can have more time to process saturation signal, also correctly demodulation with the carrier frequency offset signal; In addition, because the error of more cheap oscillator carrier frequencies side-play amount is larger, therefore, the present invention can also reduce production costs.
In order to enable further to understand feature of the present invention and technology contents, refer to following about detailed description of the present invention and accompanying drawing, yet accompanying drawing only provide with reference to and explanation, not be used for the present invention is limited.
The accompanying drawing explanation
The present invention must, by following accompanying drawing and explanation, can obtain a more deep understanding:
Fig. 1 is the functional block diagram of existing signal processing circuit.
Fig. 2 is existing signal processing method flow chart.
The sequential that Fig. 3 is IEEE 802.11a/g/n wireless network protocol is utilized schematic diagram.
The functional block diagram that Fig. 4 is signal processing circuit of the present invention.
The signal processing method flow chart of Fig. 5 for illustrating according to one embodiment of the invention.
The thin section functional block diagram of the signal processing circuit that Fig. 6 illustrates for the first preferred embodiment according to the present invention.
The thin section functional block diagram of the signal processing circuit that Fig. 7 illustrates for the second preferred embodiment according to the present invention.
The signal processing method flow chart of Fig. 8 for illustrating according to another embodiment of the present invention.
Embodiment
The functional block diagram that Fig. 4 is signal processing circuit 40 of the present invention comprises: signal receiving circuit 420, analog/digital converter 440, signal evaluation circuit 460 and baseband circuit 480.The flow chart that Fig. 5 is corresponding signal processing method, please reference in the lump.
In step 520, signal receiving circuit 420 receives a radiofrequency signal, and the yield value produced according to signal evaluation circuit 460 is adjusted this radiofrequency signal, and radiofrequency signal is converted to analog signal.Then analog signal is converted to digital signal r (t) by analog/digital converter 440, signal evaluation circuit 460 produces a yield value according to digital signal r (t) and adjusts radiofrequency signal; Furtherly, if digital signal r (t) can not analyze, the signal that representative is received is still in saturation condition, and now signal evaluation circuit 460 needs to reduce yield value until digital signal r (t) can analyze.
The thin section functional block diagram of the signal processing circuit 60 that Fig. 6 illustrates for the first preferred embodiment according to the present invention comprises: signal receiving circuit 420, analog/digital converter 440, signal evaluation circuit 660 and baseband circuit 680.Signal evaluation circuit 660 comprises: yield value produces circuit 662 and signal deteching circuit 664.Baseband circuit 680 comprises: phase calculation unit 682 and carrier frequency shift compensating circuit 684.For example, signal evaluation circuit 660 can be an automatic gain control circuit.Fig. 8 is corresponding signal processing method flow chart, please reference in the lump.
If digital signal r now (t) can not analyze, the signal that representative is received is still in saturation condition, enter step 840, signal deteching circuit 664 can produce a judgment value, and to carry out index signal be in saturation condition, and yield value produces circuit 662 just can reduce gain according to this judgment value.Then get back to step 830, whether signal deteching circuit 664 detection signal again is saturated.
If digital signal r now (t) can analyze, the signal that representative is received is not in saturation condition, enter step 860, when signal deteching circuit 664 comes detection signal whether to be the echo signal of wish reception according to above-mentioned calculating formula 1, can obtain complex values
and this complex values namely step 880 and 890 carrier frequency shift compensating circuit 684 detected carrier frequency offset compensations and carry out carrier frequency shift needed information of when compensation, the namely existing carrier frequency shift compensating circuit 184 detected carrier frequency offset compensations of Fig. 1 and needed information while carrying out the carrier frequency shift compensation.
More particularly, in this embodiment, when signal evaluation circuit 660 receives the signal echo signal whether for this reason the system wish receives in judgement, needed information when producing carrier frequency shift compensating circuit 684 detected carrier frequency offset compensations and carrying out the carrier frequency shift compensation, therefore carrier frequency shift compensating circuit 684 need to be after system not be judged and is received the signal echo signal that the system wish receives for this reason, more additionally takes time and resource is carried out the detected carrier frequency offset compensation and carried out the carrier frequency shift compensation.
If not the echo signal that wish receives is got back to step 810, wait for the next signal that receives.If the echo signal that wish receives, enter the radio frequency stable state of step 870 and optionally shutdown signal analysis circuit 660 save the energy.
The thin section functional block diagram of the signal processing circuit 70 that Fig. 7 illustrates for the second preferred embodiment according to the present invention comprises: signal receiving circuit 420, analog/digital converter 440, signal evaluation circuit 760 and baseband circuit 780.Signal evaluation circuit 760 comprises: yield value produces circuit 762, signal deteching circuit 764 and phase calculation unit 766.Baseband circuit 780 comprises carrier frequency shift compensating circuit 784.For example, signal evaluation circuit 760 can utilize automatic gain control circuit to realize.Earlier figures 8 also can be the corresponding signal processing method flow chart of Fig. 7, please reference in the lump.
If digital signal r now (t) can not analyze, the signal that representative is received is still in saturation condition, enter step 840, signal deteching circuit 764 can produce a judgment value, and to carry out index signal be in saturation condition, and yield value produces circuit 762 just can reduce gain according to this judgment value.Then get back to step 830, whether signal deteching circuit 764 detection signal again is saturated.
If digital signal r now (t) can analyze, the signal that representative is received is not in saturation condition, enter step 860, when signal deteching circuit 764 comes detection signal whether to be the echo signal of wish reception according to above-mentioned calculating formula 1, can obtain complex values
phase calculation unit 766 calculates phase place according to this complex values, and this phase place namely step 880 and 890 carrier frequency shift compensating circuit 784 detected carrier frequency offset compensations and needed information while carrying out the carrier frequency shift compensation.
More particularly, in this embodiment, when signal evaluation circuit 760 receives the signal echo signal whether for this reason the system wish receives in judgement, needed information when producing carrier frequency shift compensating circuit 784 detected carrier frequency offset compensations and carrying out the carrier frequency shift compensation, therefore carrier frequency shift compensating circuit 784 need to be after system not be judged and is received the signal echo signal that the system wish receives for this reason, more additionally takes time and resource is carried out the detected carrier frequency offset compensation and carried out the carrier frequency shift compensation.
Therefore, in the available circuit of Fig. 1, baseband circuit 180 in system judge receive the signal echo signal that the system wish receives for this reason after calculated complex value voluntarily again
then carry out the detected carrier frequency offset compensation according to complex values again and carry out the carrier frequency shift compensation, this consuming time and shortcoming cost source just can improve.
If not the echo signal that wish receives is got back to step 810, wait for the next signal that receives.If the echo signal that wish receives, enter the radio frequency stable state of step 870 and optionally shutdown signal analysis circuit 760 save the energy.
In sum, the present invention proposes a kind ofly can have more time to process saturation signal, therefore also can correct demodulation with signal processing circuit and the method thereof of carrier frequency offset signal, can save the time of carrier frequency shift compensation estimation, and can have the more time to process saturated signal, the signal that also correctly demodulation compensates with carrier frequency shift.In addition, because the error of more cheap its carrier frequency shift of oscillator is larger, therefore, the present invention can also reduce production costs.
Although the present invention discloses as above with preferred embodiment, yet it is not in order to limit the present invention.Anyly be familiar with this operator, without departing from the spirit and scope of the present invention, when making the various changes that are equal to or replacement, protection scope of the present invention is when looking accompanying being as the criterion that the application's claim scope defines.
Claims (11)
1. a signal processing circuit, is characterized in that, comprising:
One signal receiving circuit, in order to receive a radiofrequency signal, adjust this radiofrequency signal according to a yield value, and this radiofrequency signal be converted to an analog signal;
One analog/digital converter, be coupled to this signal receiving circuit, in order to being a digital signal by this analog signal conversion;
One signal evaluation circuit, be coupled to this analog/digital converter and this signal receiving circuit, in order to according to this digital signal to adjust this yield value, detect this digital signal and take and judge the echo signal whether this digital signal receives as wish and produce a reference value simultaneously; And
One baseband circuit, be coupled to this analog/digital converter and this signal evaluation circuit, in order to according to this reference value, this digital signal is carried out to a carrier frequency shift compensation.
2. circuit according to claim 1, is characterized in that, this signal evaluation circuit comprises:
One yield value produces circuit, is coupled to this analog/digital converter and this signal receiving circuit, in order to analyze this digital signal to produce this yield value; And
One signal deteching circuit, be coupled to this analog/digital converter, this yield value generation circuit and this baseband circuit, in order to produce a judgment value and this reference value according to this digital signal;
Wherein, whether this yield value generation circuit system continues to adjust this yield value according to this judgment value with decision.
3. circuit according to claim 2, is characterized in that, this reference value is a complex values.
4. circuit according to claim 2, is characterized in that, this baseband circuit comprises:
One phase calculation unit, be coupled to this signal evaluation circuit, in order to according to this reference value, to calculate a phase place; And
One carrier frequency shift compensating circuit, be coupled to this analog/digital converter and this phase calculation unit, in order to according to this phase place, this digital signal is carried out to this carrier frequency shift compensation.
5. circuit according to claim 2, is characterized in that, it is an automatic gain control circuit that this yield value produces circuit.
6. circuit according to claim 1, is characterized in that, this signal evaluation circuit comprises:
One yield value produces circuit, is coupled to this analog/digital converter and this signal receiving circuit, in order to analyze this digital signal to produce this yield value;
One signal deteching circuit, be coupled to this analog/digital converter and this yield value and produce circuit, in order to produce a judgment value and a complex values according to this digital signal; And
One phase calculation unit, be coupled to this signal deteching circuit and this baseband circuit, in order to according to this complex values, to calculate this reference value;
Wherein, whether this yield value generation circuit continues to adjust this yield value according to this judgment value with decision.
7. circuit according to claim 6, is characterized in that, this reference value is a phase place.
8. circuit according to claim 6, is characterized in that, this baseband circuit comprises:
One carrier frequency shift compensating circuit, be coupled to this analog/digital converter and this phase calculation unit, in order to according to this reference value, this digital signal is carried out to this carrier frequency shift compensation.
9. circuit according to claim 6, is characterized in that, it is an automatic gain control circuit that this yield value produces circuit.
10. a signal processing method, is characterized in that, comprising:
Receive a signal, according to a yield value, adjust this signal;
Detect this signal and take and judge the echo signal whether this signal receives as wish, and produce a reference value simultaneously;
Produce the whether judgment value in saturation condition of this signal of indication according to this signal, and adjust this yield value according to this judgment value;
Calculate a phase place according to this reference value; And
According to this phase place, this signal is carried out to the carrier frequency shift compensation.
11. method according to claim 10, is characterized in that, this reference value is a complex values.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010128828 CN102148604B (en) | 2010-02-10 | 2010-02-10 | Signal processing circuit and method thereof |
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|---|---|---|---|
| CN 201010128828 CN102148604B (en) | 2010-02-10 | 2010-02-10 | Signal processing circuit and method thereof |
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| CN102148604A CN102148604A (en) | 2011-08-10 |
| CN102148604B true CN102148604B (en) | 2013-12-18 |
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| CN 201010128828 Expired - Fee Related CN102148604B (en) | 2010-02-10 | 2010-02-10 | Signal processing circuit and method thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1694364A (en) * | 2004-05-04 | 2005-11-09 | 因芬尼昂技术股份公司 | Device and method for down-mixing of a radio-frequency signal, which has been received by radio, to baseband |
| CN101150295A (en) * | 2007-11-06 | 2008-03-26 | 哈尔滨工程大学 | Controllable gain general frequency converter for multiplication digital/analog converter |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7099642B2 (en) * | 2001-11-09 | 2006-08-29 | Qualcomm, Incorporated | Method and apparatus for matching receiver carrier frequency |
| JP3715606B2 (en) * | 2002-09-10 | 2005-11-09 | 株式会社東芝 | Wireless communication apparatus and control method thereof |
| US8509355B2 (en) * | 2008-06-30 | 2013-08-13 | Medtronic, Inc. | Method and apparatus for low power simultaneous frequency, automatic gain control and timing acquisition in radio receivers |
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2010
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1694364A (en) * | 2004-05-04 | 2005-11-09 | 因芬尼昂技术股份公司 | Device and method for down-mixing of a radio-frequency signal, which has been received by radio, to baseband |
| CN101150295A (en) * | 2007-11-06 | 2008-03-26 | 哈尔滨工程大学 | Controllable gain general frequency converter for multiplication digital/analog converter |
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