CN102130694A - Circuit for parallelly encoding quasi-cyclic low-density parity check code - Google Patents

Circuit for parallelly encoding quasi-cyclic low-density parity check code Download PDF

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CN102130694A
CN102130694A CN2011100474803A CN201110047480A CN102130694A CN 102130694 A CN102130694 A CN 102130694A CN 2011100474803 A CN2011100474803 A CN 2011100474803A CN 201110047480 A CN201110047480 A CN 201110047480A CN 102130694 A CN102130694 A CN 102130694A
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parity check
density parity
circuit
cyclic
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沈海斌
张雷雷
陈武
李袁鑫
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Zhejiang University ZJU
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Abstract

The invention discloses a circuit for parallelly encoding a quasi-cyclic low-density parity check code. The circuit comprises one or more encoding circuit units; each of the encoding circuit units comprises a first register group 1, an AND-gate array 2, an exclusive or (XOR) gate group 3 and a second register group 4; both the first register group and the second register group consist of L registers according to a dimension L of a cyclic permutation matrix; the XOR gate group consists of L XOR gates according to the dimension L of the cyclic permutation matrix; the output end of the first register group is connected with the input end of the AND-gate array; the output end of the AND-gate array is connected with the input end of the XOR gate group; the output end of the XOR gate group is connected with the input end of the second register group; and the output end of the second register group is connected with the input end of the XOR gate group. By the circuit for parallelly encoding the quasi-cyclic low-density parity check code, the parallel encoding of the quasi-cyclic low-density parity check code is realized; the encoding complexity is low and the encoding speed is high; the sequence and the dimension of the cyclic permutation matrix cannot be restrained, so a parallel factor is not restrained; therefore, the circuit has the advantages of high flexibility and small area.

Description

A kind of quasi-cyclic low-density parity check codes parallel encoding circuit
Technical field
The present invention relates to coding circuit, relate in particular to a kind of quasi-cyclic low-density parity check codes parallel encoding circuit.
Background technology
Gallager has proposed low density parity check code invention in 1962, but people just slowly recognize its function admirable and have great practical value up to date.Low density parity check code is the linear block codes that a class has premium properties, the low density parity check code of particular configuration can obtain the excellent properties near shannon limit, make its focus that becomes current research and application, all can see its figure in communication and field of storage.The check matrix of low density parity check code is made of sparse matrix, make low density parity check code have decoding algorithm efficiently, adopt the decoding complexity and the code length of belief propagation algorithm linear, overcome the huge decoding complexity problem that block code is faced when code length is longer, yet higher encoder complexity is one of its shortcoming always.The H check matrix of low density parity check code is configured with dual mode: a kind of is the randomization structure, mainly is that check matrix is set restriction, as long girth value of minimum ring or node degree distribution etc., utilizes computer search to generate the H matrix of requirement at random again; Another kind is a structured configurations, utilizes how much tool configuration H of algebraical sum matrix, makes it have regular texture, is convenient to coding.Low density parity check code can adopt linear block codes universal coding mode to encode, and the H check matrix is adopted Gaussian elimination method, produces lower triangular matrix, adopts elementary transformation to obtain H=[P| then I] form, by G=[ I| P T] obtain generator matrix, and encode by c=mG and to obtain corresponding codewords.Although the H matrix of low density parity check code is sparse, its generator matrix G may be not sparse, adopts the universal coding mode to need O (n 2) hardware complexity, n is a code length, when code length surpasses 10 3The time, complexity allows the people be difficult to accept.
One of use key issue that low density parity check code ran into is that it has higher encoder complexity and coding time delay, and as the quasi-cyclic low-density parity check codes of one of low density parity check code classification, has the uniform enconding complexity, be more conducive to hardware and realize having very important using value.At first because its generator matrix G has loop structure, this makes it can adopt linear displacement feedback register (LFSR) and finish coding in linear session, thereby reduces encoder complexity greatly; Secondly its decoding can be adopted the counter addressing, and can realize parallel organization, thereby improves the decoding throughput greatly.No matter the quasi-cyclic low-density parity check codes of appropriate design is the error rate at aspect of performance, and frame error rate still is a wrong flat bed etc., all is similar to the low density parity check code of random configuration.Therefore quasi-cyclic low-density parity check codes has obtained more application in hard-wired low density parity check code error correction scheme.
The check matrix of quasi-cyclic low-density parity check codes
Figure 2011100474803100002DEST_PATH_IMAGE001
Form is as follows:
Figure 994782DEST_PATH_IMAGE002
By c* tIndividual cyclic permutation (permutation) matrix
Figure 2011100474803100002DEST_PATH_IMAGE003
Form, c, tBe positive integer, and c＜ t, submatrix
Figure 527843DEST_PATH_IMAGE004
For L* LSquare formation,
Figure 2011100474803100002DEST_PATH_IMAGE005
Expression LDimension unit matrix I cyclic shift
Figure 600841DEST_PATH_IMAGE006
The cyclic permutation matrices that obtains after inferior, and
Figure 378916DEST_PATH_IMAGE006
=0 o'clock, P 0Be unit matrix,
Figure 475048DEST_PATH_IMAGE006
During=∞, P ∞Be null matrix.To own
Figure 248969DEST_PATH_IMAGE006
Extract and be configured to s-matrix, claim that s-matrix is the translocation factor index matrix:
Figure 2011100474803100002DEST_PATH_IMAGE007
The method that a lot of structure index matrixs are arranged is according to pursuit
Figure 927206DEST_PATH_IMAGE001
Long or the maximum code of maximum girth ring apart from etc. different target can adopt different index matrix makes.After constructing index matrix, corresponding matrix
Figure 128381DEST_PATH_IMAGE001
Also structure finishes.
People's labors such as Lin Shu the efficient coding of quasi-cyclic low-density parity check codes, proposition is sought out the method for systemic circulation shape generator matrix by the H matrix, and has proposed three kinds of coding circuits based on SRAA (shift-register-adder-accumulator) based on generator matrix: based on SRAA serial code structure, based on SRAA parallel organization and two-layer configuration.Wherein first kind of structure is serial structure, and hardware costs is little, but the periodicity that the coding required time need equate with message length, speed is slower; Though second kind of structure speed is very fast, need be ready to all information bits in advance, the storage cost that brings thus is very big, when message length is long more so; Also there is the requirement that need be ready to all information bits in advance in the third structure, need H matrix full rank simultaneously, but quasi-cyclic low-density parity check codes in fact
Figure 524858DEST_PATH_IMAGE001
Matrix is full rank not generally.Therefore the sum of ranks dimension that is necessary to design a kind of cyclic permutation matrices is unrestricted, ready message position in advance, and can carry out the quasi-cyclic low-density parity check codes coding circuit of parallel encoding.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of quasi-cyclic low-density parity check codes parallel encoding circuit is provided.
Quasi-cyclic low-density parity check codes parallel encoding circuit comprises one or more coding circuits unit, the coding circuit unit comprise first registers group 1, with gate array 2, XOR gate group 3 and second registers group 4; Described first registers group and second registers group are according to the dimension of cyclic permutation matrices LBy LIndividual register constitutes; Described XOR gate group is according to the dimension of cyclic permutation matrices LBy LIndividual XOR gate constitutes; The output of described first registers group be connected with the input of gate array, be connected with the input of XOR gate group with the output of gate array, the output of XOR gate group is connected with the input of second registers group, and the output of second registers group is connected with the input of XOR gate group.
Compared with prior art, the invention has the beneficial effects as follows: (1) has realized the parallel encoding circuit of quasi-cyclic low-density parity check codes, compares the serial code circuit, and speed is promoted greatly; (2) the sum of ranks dimension of cyclic permutation matrices is unrestricted, and the parallel factor is unrestricted, the flexibility ratio height; (3) need not be ready to information bit in advance, storage cost is little.
In sum, quasi-cyclic low-density parity check codes parallel encoding circuit of the present invention: encoder complexity is low, and by parallel mode, speed is fast, the sum of ranks dimension of cyclic permutation matrices LUnrestricted, the parallel factor pUnrestricted, the flexibility ratio height, and have the little advantage of area concurrently.
Description of drawings
Fig. 1 is a quasi-cyclic low-density parity check codes parallel encoding circuit block diagram;
Fig. 2 is the implementation figure of the present invention's first registers group;
The circuit block diagram that Fig. 3 forms for a plurality of coding circuits of the present invention unit.
Embodiment
Describe the present invention in detail below in conjunction with accompanying drawing.
As shown in Figure 1, quasi-cyclic low-density parity check codes parallel encoding circuit is characterized in that comprising one or more coding circuits unit, the coding circuit unit comprise first registers group 1, with gate array 2, XOR gate group 3 and second registers group 4; Described first registers group 1 and second registers group 4 are according to the dimension of cyclic permutation matrices LBy LIndividual register constitutes; Described XOR gate group 3 is according to the dimension of cyclic permutation matrices LBy LIndividual XOR gate constitutes; The output of described first registers group 1 is connected with input with gate array 2, be connected with the input of XOR gate group 3 with the output of gate array 2, the output of XOR gate group 3 is connected with the input of second registers group 4, and the output of second registers group 4 is connected with the input of XOR gate group 2.
Relevant mathematical derivation is described simply, by
Figure 836891DEST_PATH_IMAGE001
Can construct corresponding , following systemic circulation form is generally arranged:
Figure 2011100474803100002DEST_PATH_IMAGE009
(1)
Make the information bit vector be
Figure 944972DEST_PATH_IMAGE010
, code word
Figure 2011100474803100002DEST_PATH_IMAGE011
Have the systematic code form:
Figure 888133DEST_PATH_IMAGE012
, wherein
Figure 2011100474803100002DEST_PATH_IMAGE013
Be verification unit.By
Figure 692272DEST_PATH_IMAGE014
And (1) formula, obtain
Figure 2011100474803100002DEST_PATH_IMAGE015
(2)
Wherein 1≤ j≤ cBy the character of cyclic permutation matrices as can be known, order
Figure 594369DEST_PATH_IMAGE016
For
Figure 888078DEST_PATH_IMAGE008
Submatrix in the matrix
Figure 2011100474803100002DEST_PATH_IMAGE017
First the row, then Other the row all can by Ring shift right obtains, and also claims first row
Figure 479706DEST_PATH_IMAGE016
For generating son.Order
Figure 193584DEST_PATH_IMAGE018
For
Figure 114267DEST_PATH_IMAGE016
Move to right
Figure 322525DEST_PATH_IMAGE020
The position obtains, and is obtained by (2) formula
Figure 2011100474803100002DEST_PATH_IMAGE021
(3)
Know that by (2) formula and (3) formula verification unit can be calculated as follows: each
Figure 767192DEST_PATH_IMAGE022
All resolve into earlier , and
Figure 730600DEST_PATH_IMAGE023
Each cycle of coding circuit can obtain with the XOR that adds up again with the elder generation of the displacement that generates son by each bit of information bit vector, if can realize in (3) formula p Sum so just can realize parallel encoding.
Below introduce each basic function of forming among Fig. 1.Because this coding circuit adopts iterative manner to carry out, therefore order rBe rThe clock cycle of individual iteration.
At first introduce the implementation of first registers group 1: first method is will need each clock cycle Be input in first registers group 1.The second way is to adopt feedback shift register form shown in Figure 2, if first registers group 1 is by D 1, D 2..., D L-1 , D L Altogether LIndividual register is formed, and their connected mode is: D 1Output and D p+ 1 Input connect D 2Output and D p+ 2 Input connect ..., D p-1 Output and D 2 p-1 Input connect D p Output and D 2 p Input connect D p+ 1 Output and D 2 p+ 1 Input connect D p+ 2 Output and D 2 p+ 2 Input connect ..., D L- p+ 1 Output and D 1Input connect D L- p+ 2 Output and D 2Input connect ..., D L-1 Output and D p-1 Input connect D L Output and D p Input connect, in brief, promptly the iIndividual register D i Output and it be separated by pOf individual sequence number i+ pThe input of individual register connects, and carries out cyclic shift by feedback form.After connecting in such a way, only need first clock input
Figure 947266DEST_PATH_IMAGE016
, by the storage that is shifted of feedback shift register form, so just import new in the time afterwards without each cycle
Figure 412883DEST_PATH_IMAGE026
The preferred second kind of implementation of the present invention can effectively reduce control complexity and storage cost.
With gate array 2 be in order to realize rDuring individual clock cycle in (3) formula pThe item AND-operation comprises
Figure 2011100474803100002DEST_PATH_IMAGE027
,
Figure 544262DEST_PATH_IMAGE028
..., Operation as required can realize the output of the corresponding input information position and first registers group 1 and gate array as being connected with the input of gate array.
Second registers group 4 by LIndividual common register is formed, and is mainly used in the median when keeping in iterative computation , after the required time of encoding operation finished, the value of second registers group, 4 storages was the checking symbol position
Figure 910969DEST_PATH_IMAGE022
XOR gate group 3 is for will be by producing with gate array p
Figure 247404DEST_PATH_IMAGE027
,
Figure 739565DEST_PATH_IMAGE028
...,
Figure 528661DEST_PATH_IMAGE029
Be stored in the median of second registers group 4 before
Figure 131680DEST_PATH_IMAGE030
All " addition ", to produce iteration median next time:
Figure 2011100474803100002DEST_PATH_IMAGE031
。
According to Fig. 1, operation is described below:
Step 1: initialization, at first with generation of correspondence
Figure 647588DEST_PATH_IMAGE016
Be deposited in first registers group, 1 corresponding each register, the initialization of register of second registers group 4 is zero.
Step 2:
Period 1, will be before pThe bit information position is input to generation with 1 storage of gate array 2, the first registers group Also be input to and gate array 2, can finish
Figure 587042DEST_PATH_IMAGE032
,
Figure 2011100474803100002DEST_PATH_IMAGE033
..., Operation.To generate with gate array
Figure 852250DEST_PATH_IMAGE032
,
Figure 230754DEST_PATH_IMAGE033
...,
Figure 446971DEST_PATH_IMAGE034
Value outputs to the XOR gate group, simultaneously the storing value of second registers group 4
Figure 2011100474803100002DEST_PATH_IMAGE035
Also be input to XOR gate group 3, carry out
Figure 204843DEST_PATH_IMAGE036
Operation deposits income value in second registers group 4 then and finishes
Figure 619644DEST_PATH_IMAGE030
Renewal:
Figure 2011100474803100002DEST_PATH_IMAGE037
Operation.First registers group 1 is upgraded and is obtained simultaneously Value.
Second round is with second pThe bit information position is input to generation with 1 storage of gate array 2, the first registers group Also be input to and gate array 2, can finish
Figure DEST_PATH_IMAGE039
, ...,
Figure DEST_PATH_IMAGE041
Operation.To generate with gate array
Figure 204898DEST_PATH_IMAGE039
,
Figure 115085DEST_PATH_IMAGE040
..., Value outputs to the XOR gate group, simultaneously the storing value of second registers group 4
Figure 139990DEST_PATH_IMAGE042
Also be input to XOR gate group 3, carry out
Figure DEST_PATH_IMAGE043
Operation deposits income value in second registers group 4 then to finish
Figure 339503DEST_PATH_IMAGE030
Renewal: promptly carry out
Figure 436903DEST_PATH_IMAGE044
Operation.First registers group 1 is upgraded and is obtained simultaneously
Figure DEST_PATH_IMAGE045
Value.
And the like need be total to
Figure 724796DEST_PATH_IMAGE046
Cycleoperation is to calculate
Figure 549532DEST_PATH_IMAGE023
Value, wherein "
Figure DEST_PATH_IMAGE047
" represent to round up.Pay special attention to May not by
Figure DEST_PATH_IMAGE049
Divide exactly, thus the effective information position of last input clock cycle may less than , only use input benefit " 0 " to get final product to non-effective information position, can not influence coding result.
Step 3: according to (3) formula, coding generates one
Figure 709359DEST_PATH_IMAGE022
Need
Figure 88519DEST_PATH_IMAGE050
Individual
Figure 186925DEST_PATH_IMAGE023
, and step 2 only calculates one
Figure 626127DEST_PATH_IMAGE023
, therefore need repeating step two altogether
Figure 75563DEST_PATH_IMAGE050
Inferior.
Figure DEST_PATH_IMAGE051
After the individual clock cycle, EO generates one
Figure 52222DEST_PATH_IMAGE022
Because the verification unit of a set of code words comprises
Figure 21446DEST_PATH_IMAGE013
Total cIndividual
Figure 880818DEST_PATH_IMAGE022
On coding circuit of the present invention basis, can there be two kinds to realize obtaining with reference to mode : first kind of mode as shown in Figure 3, by cIndividual coding circuit of the present invention is combined into new encoder, and each coding module input is corresponding
Figure 538512DEST_PATH_IMAGE016
Generate son and information bit,
Figure 362243DEST_PATH_IMAGE051
The individual clock cycle can be finished the coding of one group of information bit; The second way is need provide extra storage, only with a coding circuit of the present invention, whenever
Figure 392516DEST_PATH_IMAGE051
The individual clock cycle can be finished one
Figure 322205DEST_PATH_IMAGE022
Calculating, then will with extra storage
Figure 830547DEST_PATH_IMAGE022
Store, need altogether The individual clock cycle can be finished the coding of one group of information bit.The preferred first kind of implementation of the present invention can improve speed.
The foregoing description is to be used for the present invention that explains, rather than limits the invention, and in the protection range of spirit of the present invention and claim, any modification and change to the present invention makes all fall into protection scope of the present invention.

Claims (1)

1. a quasi-cyclic low-density parity check codes parallel encoding circuit is characterized in that comprising one or more coding circuits unit, the coding circuit unit comprise first registers group (1), with gate array (2), XOR gate group (3) and second registers group (4); Described first registers group (1) and second registers group (4) are according to the dimension of cyclic permutation matrices LBy LIndividual register constitutes; Described XOR gate group (3) is according to the dimension of cyclic permutation matrices LBy LIndividual XOR gate constitutes; The output of described first registers group (1) is connected with input with gate array (2), be connected with the input of XOR gate group (3) with the output of gate array (2), the output of XOR gate group (3) is connected with the input of second registers group (4), and the output of second registers group (4) is connected with the input of XOR gate group (2).
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102843149A (en) * 2012-09-27 2012-12-26 苏州威士达信息科技有限公司 LDPC (Quasi-Cyclic Low-Density Parity-Check) encoder and encoding method based on summation array in near field communication
CN102857236A (en) * 2012-09-27 2013-01-02 苏州威士达信息科技有限公司 China mobile multimedia broadcasting (CMMB) low density parity check (LDPC) encoder based on summation array and coding method
CN105356968A (en) * 2015-06-24 2016-02-24 深圳大学 Network coding method and system based on circulant permutation matrix
CN113422611A (en) * 2021-05-19 2021-09-21 上海大学 Highly parallel encoding method of QC-LDPC encoder

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CN1787415A (en) * 2004-12-08 2006-06-14 中兴通讯股份有限公司 Apparatus for realizing false random code phase deviation and method for forming false random code
CN1976238A (en) * 2006-12-21 2007-06-06 复旦大学 Method for constituting quasi-circulating low-density parity check code based on block fill algorithm
CN101689866A (en) * 2007-07-12 2010-03-31 松下电器产业株式会社 Low-density parity check convolution code (ldpc-cc) encoder and ldpc-cc decoder

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Publication number Priority date Publication date Assignee Title
CN1787415A (en) * 2004-12-08 2006-06-14 中兴通讯股份有限公司 Apparatus for realizing false random code phase deviation and method for forming false random code
CN1976238A (en) * 2006-12-21 2007-06-06 复旦大学 Method for constituting quasi-circulating low-density parity check code based on block fill algorithm
CN101689866A (en) * 2007-07-12 2010-03-31 松下电器产业株式会社 Low-density parity check convolution code (ldpc-cc) encoder and ldpc-cc decoder

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102843149A (en) * 2012-09-27 2012-12-26 苏州威士达信息科技有限公司 LDPC (Quasi-Cyclic Low-Density Parity-Check) encoder and encoding method based on summation array in near field communication
CN102857236A (en) * 2012-09-27 2013-01-02 苏州威士达信息科技有限公司 China mobile multimedia broadcasting (CMMB) low density parity check (LDPC) encoder based on summation array and coding method
CN102857236B (en) * 2012-09-27 2016-03-09 中国传媒大学 Based on LDPC encoder and coding method in the CMMB of sum array
CN102843149B (en) * 2012-09-27 2016-03-09 苏州威士达信息科技有限公司 Based on LDPC encoder and coding method in the near-earth communication of sum array
CN105356968A (en) * 2015-06-24 2016-02-24 深圳大学 Network coding method and system based on circulant permutation matrix
CN105356968B (en) * 2015-06-24 2018-11-16 深圳大学 The method and system of network code based on cyclic permutation matrices
CN113422611A (en) * 2021-05-19 2021-09-21 上海大学 Highly parallel encoding method of QC-LDPC encoder

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Application publication date: 20110720