CN102116841B - Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model - Google Patents
Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model Download PDFInfo
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Abstract
The invention belongs to the electronic technology field, and in particular relates to a method for evaluating a FPGA (Field Programmable Gata Array) interconnection structure based on the quantization of a model. With the adoption of the method, the key factors capable of influencing the FPGA interconnection structure are quantitatively modeled, and an evaluation index based on average jumping number statistics is proposed on the basis of the model. Through the method, a large-scale FPGA interconnection structure space can be transversely searched within the short time, which is ensured to be basically consistent with the evaluation result obtained by the complete CAD process within the large scope.
Description
Technical field
The invention belongs to electronic technology field, relate to the design of FPGA interconnect architecture, be specifically related to the FPGA interconnect architecture appraisal procedure quantizing based on model.
Technical background
The hardware configuration of modern FPGA is increasingly sophisticated, the performance index of passing judgment on a fpga chip are also varied, the object of FPGA evaluating system is in order to assess the quality of various FPGA Design of Hardware Architectures under the optimization aim of appointment, and finally with this, guides Design of Hardware Architecture and improved direction.
Traditional FPGA interconnect architecture appraisal procedure generally has two kinds, and a kind of is to rely on designer's experience to be accepted or rejected, another kind of be that one group of standard testing circuit is mapped to and on object construction, is observed performance by complete CAD flow process.Two kinds of methods have obvious shortcoming, and the former cannot search for and excavate potential FPGA interconnect architecture fully, and conclusion is comparatively subjective; Although the latter is accurate, time cost is very large, in reality, unlikely searches on a large scale.Therefore the method accepting can to assess on a large scale in the time FPGA interconnect architecture has been proposed to requirement.
Summary of the invention
The object of the invention is to propose a kind of time cost that can reduce the assessment of FPGA interconnect architecture, and on a large scale, guarantee the FPGA interconnect architecture appraisal procedure of Evaluation accuracy.
The FPGA interconnect architecture appraisal procedure that the present invention proposes, overall plan is as follows: extract the key parameter that affects FPGA interconnect architecture: interconnection line kind, interconnecting channels width, interconnectedness, integrated, FPGA interconnect architecture is carried out to comprehensive modeling, obtain that signal once jumps, the distribution plan of twice jump, the logical block that can cover of jumping for three times, and obtain the signal permission throughput of each logical block covering.On the basis of this model, extract the index quantizing and be used for evaluating interconnect architecture.This index must cover and distinguish the impact that the difference of interconnected gauze kind, interconnecting channels width, interconnectedness in different structure is brought performance.
Model is described below: for any one model, evaluate the quality of interconnect architecture, all must embody the impact that following factor is brought interconnected performance:
1 interconnection line kind.Comprise single times of traditional line, 2 times of lines, 6 times of lines etc., and the various various lines that turn of introducing for strengthening interconnected ability;
2 interconnecting channels width.The configuration radical that comprises every kind of interconnection line;
The design of 3 general interconnect matrixes.Comprise interconnectedness and driving relationship between various interconnection lines.
In our model, above several factors have been carried out to organic integration, can quicklook obtain a comprehensive evaluation index.
First, to the embodiment of interconnection line kind, can illustrate in patterned mode.The symmetrical diagonal angle interconnect architecture that is similar to Xilinx Virtex5 series of take is below example, as shown in Figure 1.A square in figure represents a basic programmable logic cells (CLB).The circular CLB of take in scheming sets out as initial point, and according to given interconnection line kind, the CLB that can traverse through once jump (HOP) marks with square.Similarly, the rhombus in figure and star CLB represent respectively the CLB that jumps and can traverse through twice and three times.Obviously, if the combination of given different interconnection line kind, so from red CLB, an its HOP set, twice HOP set, three HOP set distribution is in the plane all different, and rate of propagation and the ability of signal in different interconnect architectures expressed in this distribution intuitively.
Secondly, the configuration radical of every kind of interconnection line also can exert an influence for the performance of interconnect architecture.In superincumbent planimetric map, only embodied the position that signal jumps and can arrive respectively through several times from source point, but can not embody " bandwidth " that signal arrives this position, the capacity that the signal that this kind of interconnect architecture can provide in this position passes through.In order to embody this point, we increase one dimension on the basis of planimetric map, represent " bandwidth ", as shown in Figure 2.
Finally, interconnectedness also can be embodied in our model.By the formation of further segmentation " bandwidth ", we can reflect the Connection Density between various gauzes and driving relationship.What interconnectedness reflected in essence is transfer ability, therefore take once to jump and be relayed to twice jump as example, we can tracer signal arrive current C LB through which kind of gauze, and by interconnectedness, calculate direction and the circuit that signal can walk on and distribute, thereby obtain the bandwidth after corresponding secondary jumps.So, the impact of interconnecting channels width and interconnectedness can be unified in " bandwidth " and embody.
There is above model, just for extracting various quantizating index evaluations, provide possibility.
The FPGA interconnect architecture appraisal procedure quantizing based on model of the present invention, concrete steps can be summarized as follows:
1) extract the key parameter that affects FPGA interconnect architecture
FPGA interconnect architecture is described by unified form, comprises interconnection line kind in form, interconnecting channels width, these three key parameters of interconnectedness;
2) FPGA interconnect architecture is carried out to patterned modeling
According to interconnection line kind, calculate from certain programmable logic cells, by once, other programmable logic cells set of jumping and can cover respectively for twice, three times.On this basis, according to interconnecting channels width and interconnectedness, calculate the signal maximum throughput that arrives arbitrary unit in set.Wherein:
The method of calculating number of skips is, adds up the logical block position that all interconnected gauzes can be radiated, and those positions that can be once radiated are the set of once jumping; In like manner, from the logical block of once jumping set, then the statistics position that once all interconnected gauzes can be radiated, be secondary jump set, the like.The account form of signal maximum throughput is, for each logical block position, all quantity summations that can be radiated the interconnected gauze of this position;
3) definition quantizating index
On model basis, can customize quantizating index, the satisfied condition of this index is: must cover and distinguish the impact that the difference of interconnected gauze kind, interconnecting channels width, interconnectedness in different structure is brought performance." average number of skips " index that we propose of take is example, just can meet well above condition;
4) by selected interconnected gauze kind, we can automatically travel through and enumerate all possible gauze array mode, thereby obtain large batch of FPGA interconnect architecture.Then for each structure repeating step 1) ~ 3), the score according to the index defining in step 3) as every kind of structure, then sorts, thereby filters out the structure of comparatively optimizing, and instructs more detailed Networking Design of later stage.
In said method, adopt unified parametrization mode to be described described in step 1) to FPGA interconnect architecture, parameter at least comprises interconnection line kind, interconnecting channels width, interconnectedness.
In said method, step 2) described carries out three-dimensional modeling to FPGA interconnect architecture, wherein XY plane reflection once, the programmable logic cells that jumps and can arrive for twice, three times, Z axis reflects the permission semaphore of this unit of arrival.
In said method, the quantizating index extracting from model described in step 3) is self-defining.
In said method, step 4) is to utilize average number of skips index to screen on a large scale FPGA interconnect architecture.
Technique effect: the inventive method has greatly been accelerated the assessment of FPGA interconnect architecture, time cost with by traditional complete CAD flow process, compare negligiblely, guaranteed the accuracy of assessment simultaneously.
Accompanying drawing explanation
Fig. 1 signal number of skips model schematic diagram.
Fig. 2 " bandwidth " model schematic diagram.
Fig. 3 watch window weighting function schematic diagram.
Fig. 4 theoretical model and measured data variation tendency.
Embodiment
The statistics of " average number of skips " of take below is further set forth the present invention as example, but is not construed as limiting the invention
As its name suggests, " average number of skips " (
averageHop) refer in certain area, signal arrives the weighted mean value of the needed number of skips of arbitrary CLB in this region.This index has included three variable elements, and formula is as follows:
Wherein:
First parameter be " watch window radius " (
), refer to the size of regional extent, adjust this parameter and can adjust our range of value to interconnect architecture performance quality, because the performance advantage that different interconnect architectures embodies is different in different scopes, some possibility localities are fine, being good at of having is interspersed, so evaluate under different watch windows, is convenient to analyze the merits and demerits of interconnect architecture.
Second parameter be " test signal amount " (
), for testing the number of the signal of interconnected performance.The choosing of semaphore should be put into according to actual benchmark after FPGA the representative value of signal throughput on passage.If semaphore is too little, can not reflect the degree of tightness of different bandwidth everywhere, if semaphore is too large, cause overcrowdingly, do not meet with actual conditions.
The 3rd parameter be " weighting function " (
), i.e. the weight of the number of skips of certain CLB of the interior arrival of reflecting regional in overall average number of times.Because after the optimization of actual CAD flow process, each CLB that gauze gives off is always placed in close position as much as possible, so when evaluating interconnected performance, we are always interested in interconnected Local Property,
In order to set up a justice, effectively contrast platform, for above three parameters, we adopt theoretical direction to carry out prudent choosing in conjunction with the mode of statistical experiment:
For watch window, first consider that the gauze radiation scope of different examples is different.If watch window choose much larger than or much smaller than the gauze average radiation scope of benchmark, the performance of model index reflection is far by the performance departing from after practical layout wiring so.Therefore, the average gauze radiation scope of a collection of benchmark has determined choosing of watch window, is also in fact so because a kind of quality of interconnect architecture definitely objective standard not, and and for the benchmark testing, have very large correlativity.We have chosen medium 20 circuit bigger than normal as the test circuit in our experiment from the general MCNC standard testing circuit of academia.By observing the statistics that these 20 MCNC test circuits are carried out after layout, can find, its gauze average radiation length is 4.98.Therefore the radius that we choose watch window is 5, and horizontal vertical is all in-5～5 interval.(herein and hereinafter relevant length, all represents Manhattan distance).
For test signal amount, in order to reflect as far as possible truly the throughput of signal in side circuit, consider in our CLB model containing two SLICE, each SLICE comprises two 4 input LUT, therefore from the maximum data signal amount of CLB to CLB, be 16, add control signal and the possible signal of passing by one's way, we choose test signal amount is 20.
For weighting function, we wish that this function is along with the expansion of scope is the trend of Fast Convergent, because it is more inessential for interconnected performance to arrive the ability of the CLB of outer ring, its weight is because reducing rapidly.Therefore we have designed as shown in Figure 3, the weighting function of stepped decline, and its horizontal ordinate represents the distance with watch window center origin, ordinate is weighted value.
According to above-described parameter value, we have chosen at random several interconnect architectures and have calculated average number of skips index, wherein every kind of structure different types of gauze combination (such as L1L4 represents single times of line and four times of lines collocation, L3L8 represents three times of lines and the collocation of octuple line) of all having arranged in pairs or groups.As a comparison, we test the performance of these several interconnect architectures by complete CAD flow process simultaneously, and the desired value drawing with our model after test result normalization contrasts, as shown in Figure 4.
The curve that in Fig. 4, square forms is the relative variation of every kind of structural behaviour obtaining of model index, the relative variation of every kind of structural behaviour that the curve that diamond block forms obtains for actual measurement.We can find, the data that obtain by above-mentioned two kinds of diverse modes have shown good consistance at evaluation structure aspect of performance, the structure in rank prostatitis in theoretical model, the result of its actual test shows excellence too, this explanation is used our theoretical model can promptly from potential interconnect architecture set, filter out a collection of structure of optimizing, and instructs detailed design further.
Gauze average radiation length after table 1:BenchMarks layout
。
Claims (1)
1. the FPGA interconnect architecture appraisal procedure quantizing based on model, is characterized in that concrete steps are:
1) extract the key parameter that affects FPGA interconnect architecture;
FPGA interconnect architecture is described by unified form, must comprises interconnection line kind in form, interconnecting channels width, these three key parameters of interconnectedness;
2) FPGA interconnect architecture is carried out to three-dimensional picture modeling
According to interconnection line kind, calculate from certain programmable logic cells, by once, other programmable logic cells set of jumping and can cover respectively for twice, three times; On this basis, according to interconnecting channels width and interconnectedness, calculate the signal maximum throughput that arrives arbitrary unit in set;
3) definition quantizating index
Self-defined quantizating index on model basis, the satisfied condition of this index is: must cover and distinguish the impact that the difference of interconnected gauze kind, interconnecting channels width, interconnectedness in different structure is brought performance;
4) by selected interconnected gauze kind, traversal enumerates all possible gauze array mode automatically, thereby obtains large batch of FPGA interconnect architecture; Then for each structure repeating step 1) ~ step 3), the score according to the index defining in step 3) as every kind of structure, then sorts, thereby filters out the structure of comparatively optimizing, and instructs more detailed Networking Design of later stage;
Wherein, step 2) described carries out three-dimensional modeling to FPGA interconnect architecture, wherein XY plane reflection once, the programmable logic cells that jumps and can arrive for twice, three times, Z axis reflects the permission semaphore of this unit of arrival;
The method of described calculating number of skips is: add up the logical block position that all interconnected gauzes can be radiated, those positions that can be once radiated are the set of once jumping; In like manner, from the logical block of once jumping set, then the statistics position that once all interconnected gauzes can be radiated, be secondary jump set, the like; The account form of signal maximum throughput is: for each logical block position, all quantity summations that can be radiated the interconnected gauze of this position;
Described self-defined quantizating index adopts average number of skips index; Step 4) is to utilize average number of skips index to screen on a large scale FPGA interconnect architecture, and its formula is as follows:
Wherein:
First parameter be " watch window radius " (
), refer to the size of regional extent, adjust this parameter and can adjust our range of value to interconnect architecture performance quality;
Second parameter be " test signal amount " (
), for testing the number of the signal of interconnected performance;
The 3rd parameter be " weighting function " (
), i.e. the weight of the number of skips of certain CLB of the interior arrival of reflecting regional in overall average number of times;
For above three parameters, the mode of choosing is:
For watch window radius, choose 5, horizontal vertical is all in-5～5 interval;
For test signal amount, be chosen for 20;
For weighting function, choose the weighting function of stepped decline, shown in See Figure, its horizontal ordinate represents the distance with watch window center origin, ordinate is weighted value,
。
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| CN103412253B (en) * | 2013-08-05 | 2016-01-20 | 电子科技大学 | Interconnect architecture modeling method and interconnect resources configuration vector automatic generation method |
| CN105677525B (en) * | 2016-01-12 | 2019-05-03 | 复旦大学 | The part FPGA interconnection resources automated testing method based on repeatable configuration unit |
| CN106776250B (en) * | 2016-11-29 | 2020-04-07 | 中国电子产品可靠性与环境试验研究所 | Single alternating current parameter high-performance evaluation method and device of FPGA device |
| CN106599556B (en) * | 2016-11-29 | 2019-10-18 | 中国电子产品可靠性与环境试验研究所 | The comprehensive performance evaluation method and apparatus of integrated circuit |
| CN108595748B (en) * | 2018-03-09 | 2022-08-09 | 电子科技大学 | Three-dimensional topological structure of antifuse Field Programmable Gate Array (FPGA) |
| CN114757448B (en) * | 2022-06-09 | 2022-08-16 | 华北电力大学 | Manufacturing inter-link optimal value chain construction method based on data space model |
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