CN102116841A - Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model - Google Patents
Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model Download PDFInfo
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Abstract
The invention belongs to the electronic technology field, and in particular relates to a method for evaluating a FPGA (Field Programmable Gata Array) interconnection structure based on the quantization of a model. With the adoption of the method, the key factors capable of influencing the FPGA interconnection structure are quantitatively modeled, and an evaluation index based on average jumping number statistics is proposed on the basis of the model. Through the method, a large-scale FPGA interconnection structure space can be transversely searched within the short time, which is ensured to be basically consistent with the evaluation result obtained by the complete CAD process within the large scope.
Description
Technical field
The invention belongs to electronic technology field, relate to the design of FPGA interconnect architecture, be specifically related to the FPGA interconnect architecture appraisal procedure that quantizes based on model.
Technical background
The hardware configuration of modern FPGA is increasingly sophisticated, the performance index of passing judgment on a fpga chip also are varied, the purpose of FPGA evaluating system is the quality for the various FPGA hardware configuration designs of assessment under the optimization aim of appointment, and finally guides hardware configuration design and improved direction with this.
Traditional FPGA interconnect architecture appraisal procedure generally has two kinds, and a kind of is to rely on designer's experience to be accepted or rejected, and is another kind of then be one group of standard testing circuit to be mapped to by complete CAD flow process observe performance on the object construction.Two kinds of methods all have significant disadvantages, and the former can't search for and excavate potential FPGA interconnect architecture fully, and conclusion is comparatively subjective; Though the latter is accurate, time cost is very big, unlikely searches on a large scale in the reality.Therefore to having proposed requirement in the method that can accept to assess on a large scale in the time FPGA interconnect architecture.
Summary of the invention
The objective of the invention is to propose a kind of time cost that can reduce the assessment of FPGA interconnect architecture, and on a large scale, guarantee the FPGA interconnect architecture appraisal procedure of assessment precision.
The FPGA interconnect architecture appraisal procedure that the present invention proposes, overall plan is as follows: extract the key parameter that influences the FPGA interconnect architecture: the interconnection line kind, the interconnecting channels width, interconnectedness, integrated, the FPGA interconnect architecture is carried out comprehensive modeling, obtain that signal once jumps, the distribution plan of twice jump, the logical block that can cover of jumping for three times, and obtain the signal permission throughput of each logical block that covers.On this model based, extract the index that quantizes and be used to estimate interconnect architecture.This index must cover with distinguish different structure in the different influences that performance is brought of interconnected gauze kind, interconnecting channels width, interconnectedness.
Model is described below: for any one model, estimate the quality of interconnect architecture, all must embody the influence that following factor is brought interconnected performance:
1 interconnection line kind.Comprise single times of traditional line, 2 times of lines, 6 times of lines etc., and various for strengthening the various lines that turn that interconnected ability is introduced;
2 interconnecting channels width.The configuration radical that comprises every kind of interconnection line;
The design of 3 general interconnect matrixes.Comprise interconnectedness and driving relationship between the various interconnection lines.
In our model, above Several Factors has been carried out organic integration, can quicklook obtain a comprehensive evaluation index.
At first, the embodiment to the interconnection line kind can illustrate in patterned mode.Be example with a symmetrical diagonal angle interconnect architecture that is similar to Xilinx Virtex5 series below, as shown in Figure 1.A square among the figure is represented a basic programmable logic cells (CLB).With CLB circular in scheming is that initial point sets out, and according to given interconnection line kind, the CLB that can traverse through once jump (HOP) marks with square.Similarly, rhombus among the figure and star CLB represent the CLB that jumps and can traverse through twice and three times respectively.Obviously, if the combination of given different interconnection line kind, so from red CLB, an its HOP set, twice HOP set, three HOP set distributions in the plane all are different, and rate of propagation and the ability of signal in different interconnect architectures expressed in this distribution intuitively.
Secondly, the configuration radical of every kind of interconnection line also can exert an influence for the performance of interconnect architecture.In the superincumbent planimetric map, only embodied signal from the position that source point jumps and can arrive respectively through several times, but can not embody " bandwidth " that signal arrives this position, be i.e. the capacity that passes through of this kind interconnect architecture signal that can provide in this position.In order to embody this point, we increase one dimension on the basis of planimetric map, represent " bandwidth ", as shown in Figure 2.
At last, interconnectedness also can obtain embodying in our model.By the formation of further segmentation " bandwidth ", we can reflect Connection Density between the various gauzes and driving relationship.What interconnectedness reflected in essence is the transfer ability, therefore being relayed to twice jump once to jump is example, we can tracer signal arrive current C LB through which kind of gauze, and calculate direction and the circuit that signal can walk on by interconnectedness and distribute, thereby obtain bandwidth after corresponding secondary jumps.So, the influence of interconnecting channels width and interconnectedness can be unified in " bandwidth " and embody.
Above model has been arranged, just provide possibility for extracting various quantizating index evaluations.
The FPGA interconnect architecture appraisal procedure that quantizes based on model of the present invention, concrete steps can be summarized as follows:
1) extracts the key parameter that influences the FPGA interconnect architecture
The FPGA interconnect architecture is described with unified form, comprises the interconnection line kind in form, interconnecting channels width, these three key parameters of interconnectedness;
2) the FPGA interconnect architecture is carried out patterned modeling
According to the interconnection line kind, calculate from certain programmable logic cells, by once, other programmable logic cells set of jumping for twice, three times and can cover respectively.On this basis, according to interconnecting channels width and interconnectedness, calculate the signal maximum throughput that arrives arbitrary unit in the set.Wherein:
The method of calculating number of skips is, adds up the logical block position that all interconnected gauzes can be radiated, and those positions that can once be radiated are the set of once jumping; In like manner, the logical block from the set of once jumping is added up once the position that all interconnected gauzes can be radiated again, is secondary jump set, and the like.The account form of signal maximum throughput is for each logical block position, can be radiated the quantity summation of the interconnected gauze of this position to all;
3) definition quantizating index
Can self-defined quantizating index on the model basis, the condition that this index satisfies is: must cover with the differentiation different structure in the different influences that performance is brought of interconnected gauze kind, interconnecting channels width, interconnectedness." average number of skips " index that proposes with us is an example, just can satisfy above condition well;
4) by selected interconnected gauze kind, we can travel through automatically and enumerate all possible gauze array mode, thereby obtain large batch of FPGA interconnect architecture.Then at each structure repeating step 1) ~ 3), according to the score of the index that defines in the step 3), sort then, thereby filter out the structure of comparatively optimizing as every kind of structure, instruct more detailed interconnected design of later stage.
In the said method, step 1) is described to adopt unified parametrization mode to be described to the FPGA interconnect architecture, and parameter comprises the interconnection line kind at least, interconnecting channels width, interconnectedness.
In the said method, step 2) described the FPGA interconnect architecture is carried out three-dimensional modeling, wherein the XY plane reflection once, the programmable logic cells that jumps and can arrive for twice, three times, the Z axle reflects the permission semaphore of this unit of arrival.
In the said method, the described quantizating index that extracts from model of step 3) is self-defining.
In the said method, step 4) is to utilize average number of skips index to screen the FPGA interconnect architecture on a large scale.
Technique effect: the inventive method has greatly been accelerated the assessment of FPGA interconnect architecture, time cost with compare and can ignore by traditional complete CAD flow process, guaranteed the accuracy of assessment simultaneously.
Description of drawings
Fig. 1 signal number of skips model synoptic diagram.
Fig. 2 " bandwidth " model synoptic diagram.
Fig. 3 watch window weighting function synoptic diagram.
Fig. 4 theoretical model and measured data variation tendency.
Embodiment
Statistics with " average number of skips " is that example is further set forth the present invention below, but is not construed as limiting the invention
As its name suggests, " average number of skips " (
AverageHop) be meant that signal arrives the weighted mean value of the needed number of skips of arbitrary CLB in this zone in certain zone.This index has included three variable elements, and formula is as follows:
Wherein:
First parameter be " watch window radius " (
), refer to the size of regional extent, adjust this parameter and can adjust our range of value interconnect architecture performance quality, because the performance advantage that different interconnect architectures embodies is different in different scopes, the possible locality that has is fine, then being good at of having is interspersed, so estimate under different watch windows, is convenient to analyze the merits and demerits of interconnect architecture.
Second parameter be " test signal amount " (
), promptly be used to test the number of the signal of interconnected performance.The choosing of semaphore should be put into behind the FPGA representative value of signal throughput on the passage according to the benchmark of reality.If semaphore is too little, then can not reflect the degree of tightness of different bandwidth everywhere, if semaphore is too big, then cause overcrowdingly, do not meet with actual conditions.
The 3rd parameter be " weighting function " (
), i.e. the weight of number of skips in the overall average number of times of certain CLB of the interior arrival of reflecting regional.Because through after the optimization of actual CAD flow process, each CLB that gauze gives off always is placed in close position as much as possible, so when estimating interconnected performance, we are always interested in interconnected local performance,
Effectively contrast platform in order to set up a justice, for above three parameters, we adopt theoretical direction to carry out prudent choosing in conjunction with the mode of statistical experiment:
For watch window, consider that at first the gauze radiation scope of different examples is different.If watch window choose much larger than or much smaller than the gauze average radiation scope of benchmark, the performance of the model index reflection performance that will depart from after the practical layout wiring is far so.Therefore, the average gauze radiation scope of a collection of benchmark has determined choosing of watch window, in fact also is so, because a kind of quality of interconnect architecture does not have absolute objective standard, and with the benchmark that is used to test very big correlativity is arranged.We have chosen medium 20 circuit bigger than normal as the test circuit in our experiment from the general MCNC standard testing circuit of academia.Can find that by observing the statistics that these 20 MCNC test circuits are carried out after the layout its gauze average radiation length is 4.98.Therefore our radius of choosing watch window is 5, and promptly horizontal vertical is all in-5～5 interval.(reach relevant hereinafter length herein, all represent the Manhattan distance).
For the test signal amount, in order to reflect the throughput of signal in the side circuit as far as possible truly, consider in our the CLB model and contain two SLICE, each SLICE comprises two 4 input LUT, therefore the maximum data signal amount from CLB to CLB is 16, add control signal and the possible signal of passing by on one's way, we choose the test signal amount is 20.
For weighting function, we wish this function along with the expansion of scope is quick convergent trend, because it is inessential more for interconnected performance to arrive the ability of the CLB of outer ring, its weight is because of reducing rapidly.Therefore we have designed as shown in Figure 3, the weighting function of stepped decline, and its horizontal ordinate is represented the distance with the watch window center origin, ordinate is a weighted value.
According to above-described parameter value, our picked at random several interconnect architectures calculated average number of skips index, wherein every kind of structure different types of gauze combination (represent single times of line and four times of lines collocation such as L1L4, L3L8 represents three times of lines and the collocation of octuple line) of all having arranged in pairs or groups.As a comparison, we test the performance of these several interconnect architectures with complete CAD flow process simultaneously, and the desired value that draws with our model after the test result normalization contrasts, as shown in Figure 4.
The relative variation of every kind of structural behaviour that the relative variation of every kind of structural behaviour that the curve that square constitutes among Fig. 4 obtains for the model index, the curve that diamond block constitutes obtain for actual measurement.We can find, the data that obtain by above-mentioned two kinds of diverse modes have shown good consistance at the evaluation structure aspect of performance, the structure in rank prostatitis in theoretical model, its practical test result shows excellence too, this explanation uses our theoretical model promptly to filter out a collection of structure of optimizing from potential interconnect architecture set, instructs detailed design further.
Gauze average radiation length after the table 1:BenchMarks layout
Claims (4)
1. based on the FPGA interconnect architecture appraisal procedure of model quantification, it is characterized in that concrete steps are:
1) extracts the key parameter that influences the FPGA interconnect architecture;
The FPGA interconnect architecture is described in form necessary interconnection line kind, interconnecting channels width, these three key parameters of interconnectedness with unified form;
2) the FPGA interconnect architecture is carried out patterned modeling
According to the interconnection line kind, calculate from certain programmable logic cells, by once, other programmable logic cells set of jumping for twice, three times and can cover respectively; On this basis, according to interconnecting channels width and interconnectedness, calculate the signal maximum throughput that arrives arbitrary unit in the set;
3) definition quantizating index
The condition that self-defined quantizating index on the model basis, this index satisfy is: must cover with the differentiation different structure in the different influences that performance is brought of interconnected gauze kind, interconnecting channels width, interconnectedness;
4) by selected interconnected gauze kind, traversal enumerates all possible gauze array mode automatically, thereby obtains large batch of FPGA interconnect architecture; Then at each structure repeating step 1) ~ step 3), according to the score of the index that defines in the step 3), sort then, thereby filter out the structure of comparatively optimizing as every kind of structure, instruct more detailed interconnected design of later stage.
2. by the described FPGA interconnect architecture appraisal procedure that quantizes based on model of claim 1, it is characterized in that step 2) described the FPGA interconnect architecture is carried out three-dimensional modeling, wherein the XY plane reflection once, the programmable logic cells that jumps for twice, three times and arrive, the Z axle reflects the permission semaphore of this unit of arrival.
3. by the described FPGA interconnect architecture appraisal procedure that quantizes based on model of claim 2, its feature
Be step 2) in, the method for calculating number of skips is: add up the logical block position that all interconnected gauzes can be radiated, those positions that can once be radiated are the set of once jumping; In like manner, the logical block from the set of once jumping is added up once the position that all interconnected gauzes can be radiated again, is secondary jump set, and the like; The account form of signal maximum throughput is: for each logical block position, can be radiated the quantity summation of the interconnected gauze of this position to all.
4. by the described FPGA interconnect architecture appraisal procedure that quantizes based on model of claim 1, it is characterized in that self-defined quantizating index adopts average number of skips index; Step 4) is to utilize average number of skips index to screen the FPGA interconnect architecture on a large scale, and its formula is as follows:
Wherein:
First parameter be " watch window radius " (
), refer to the size of regional extent, adjust this parameter and can adjust our range of value interconnect architecture performance quality;
Second parameter be " test signal amount " (
), promptly be used to test the number of the signal of interconnected performance;
The 3rd parameter be " weighting function " (
), i.e. the weight of number of skips in the overall average number of times of certain CLB of the interior arrival of reflecting regional;
For above three parameters, the mode of choosing is:
For the watch window radius, choose 5, promptly horizontal vertical is all in-5～5 interval;
For the test signal amount, be chosen for 20;
For weighting function, choose the weighting function of stepped decline, shown in the See Figure, its horizontal ordinate is represented the distance with the watch window center origin, ordinate is a weighted value,
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| CN106776250B (en) * | 2016-11-29 | 2020-04-07 | 中国电子产品可靠性与环境试验研究所 | Single alternating current parameter high-performance evaluation method and device of FPGA device |
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