CN102096579A - Composition and structure of embedded self-adaptive fuzzy microprocessor - Google Patents
Composition and structure of embedded self-adaptive fuzzy microprocessor Download PDFInfo
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- CN102096579A CN102096579A CN2009102271878A CN200910227187A CN102096579A CN 102096579 A CN102096579 A CN 102096579A CN 2009102271878 A CN2009102271878 A CN 2009102271878A CN 200910227187 A CN200910227187 A CN 200910227187A CN 102096579 A CN102096579 A CN 102096579A
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Abstract
The invention provides a circuit structure and operating method of an embedded self-adaptive fuzzy microprocessor. The microprocessor is formed by the combination of a fuzzy logic functional part and a two-valued logic function part. The circuit structure mainly comprises related function parts, such as a self-adaptive arithmetical logic operator, a general/dedicated register group, a controller, a time/counter, a Cache (or EPRON (Erasable Programmable Read Only Memory)), a program counter, a digital-to-analogue converter, a discrimination register, a comparer, a control gate and pulse source/on-off/frequency dividing circuit, and the like. The embedded self-adaptive fuzzy microprocessor can be used for carrying out addition and subtraction arithmetic operations on any R-scale data, directly carrying out logic operation on any R-scale data, and also directly carrying out addition and subtraction operations and logical operation on any analog signal.
Description
[technical field]
The present invention relates to the composition and the structure of the fuzzy microprocessor of a kind of inlaid self-adaptive, and required self-adaptation arithmetic and logic unit and some basic fuzzy logic circuit, more particularly relate to adapt to the method for arbitrary carry system addition, subtraction operation.
[background technology]
Present general micro controller, employing all be two-valued function, and outside input mostly be non-two-value coded signal, as decimal data signal and simulating signal etc.Non-two-value coded signal need be converted to just can be sent into microprocessor behind the two-value coded signal and handle, and the two-value coded signal after microprocessor processes is converted to the signal output that meets outside need again.Like this, signal is changed repeatedly needs the time, has not only reduced the work efficiency of microprocessor, and some application problem uses two-valued function to be not easy to solve.As the thinking activities of the mankind in real world more is to make rational judgement in the environment of uncertain fuzzy message, and two-valued function is difficult to describe and handle the object of many ambiguities in the real world.Carry out work in order to make microprocessor can imitate the human law of thought better, functions such as more objective easy realization artificial intelligence, pattern-recognition, speech recognition and process control just need new, simple method and go in the face of challenge.Just must improve microprocessor theory and structure, the fuzzy logic technology then is a kind of selection preferably at all.
Fuzzy logic has obtained application in a lot of fields, but the development of fuzzy hardware lags behind the application of fuzzy logic far away.The development of fuzzy hardware is an important branch in the fuzzy logic research field.Development obfuscation circuit and fuzzy functional part are to satisfy the needs of using.Fuzzy logic is the set of the infinite successive value of utilization, and the set of this infinite successive value is also referred to as continuous logic.So fuzzy logic circuit and continuous logic circuit belong to same logic of class circuit, their no essential distinctions.Can come diagnostic cast fuzzy logic circuit by the method for research continuous logic circuit like this.The fuzzy logic circuit is the another kind of functional circuit between mimic channel and digital circuit, and it has the dual nature of Analog signals and digital signal.
Utilize this dual nature of fuzzy logic circuit, adopt fuzzy logic circuit and its functional part to constitute fuzzy logic system.Both made it to have and directly to handle the arbitrary carry system digital signal, can directly handle the arbitrary mould analog signal again.Thereby can effectively bring into play the characteristic of fuzzy logic, to satisfy the needs of artificial intelligence, pattern-recognition, speech recognition and process control.Make the realization of artificial intelligence, pattern-recognition, speech recognition and process control become easier, easier, its performance is better, more reliable.
[summary of the invention]
Fundamental purpose of the present invention is for the composition and the structure of the fuzzy microprocessor of a kind of inlaid self-adaptive are provided.A more far-reaching purpose of the present invention is the method for the adaptation arbitrary carry system addition, subtraction operation that provided, not only can be used as the foundation of electronics self-adaptation full adder, full subtracter design and many-valued full adder, full subtracter design, also can be used as the foundation of non-electronics full adder, full subtracter design, and can improve design effort efficient greatly.The fuzzy microprocessor of inlaid self-adaptive of the present invention not only can directly carry out computing and the arbitrary value logic is carried out computing any R system number, and also can directly carry out computing to any continuous analog signal.
The invention provides a kind of general-purpose operation method of self-adaptation full adder and a kind of general-purpose operation method of self-adaptation full subtracter.In the implementation method of self-adaptation full adder, adopt and transmit carry control signal U
C0Replace transmitting carry C
iMethod.This method is with respect to direct transmission carry C
i, this method both had been convenient to implement.In full subtracter embodiment to relevant borrow C
JiAlso be to adopt transmission borrow control signal to come replaced C
Ji
In the fuzzy microprocessor of inlaid self-adaptive of the present invention, adopt the exclusive data exchange register to combine, the carry C input current potential of realistic requirement is provided for self-adaptation arithmetic and logic unit (ALU) with D/A.In addition, the output result to ALU adopts hardware such as comparer to judge.
The present invention also provides and has been used for forming the fuzzy required a series of basic fuzzy logic element circuits that are made of metal-oxide-semiconductor of microprocessor of inlaid self-adaptive, as fuzzy logic threshold gate circuit, variable window fuzzy logic threshold not gate, fuzzy logic get little gate circuit, fuzzy logic is got basic circuits such as big gate circuit, fuzzy logic adding circuit, fuzzy logic subtraction circuit, fuzzy logic not circuit.They have had complete function system, can satisfy the needs that are used for constituting any indistinct usage flogic system, provide reliable guarantee for implementing the fuzzy microprocessor of inlaid self-adaptive.
Other benefits of the present invention and more far-reaching purpose are conspicuous for the professional and technical personnel in this field.
[description of drawings]
In order to understand the present invention better, provide the application's the building-block of logic of relevant functional part of the fuzzy microprocessor of inlaid self-adaptive and each required logic gates schematic diagram thereof.In the accompanying drawings:
Fig. 1 illustrates the structured flowchart according to the fuzzy microprocessor of a kind of inlaid self-adaptive of the present invention
Fig. 2 illustrates the building-block of logic according to a self-adaptation arithmetic and logic unit of the present invention.
Fig. 3 illustrates the building-block of logic according to a self-adaptation full adder of the present invention.
Fig. 4 illustrates the building-block of logic according to a self-adaptation full subtracter of the present invention.
Fig. 5 illustrates according to fuzzy logic threshold gate circuit theory diagrams of the present invention.
Fig. 6 illustrates according to fuzzy logic variable window threshold not circuit schematic diagram of the present invention.
Fig. 7 illustrates fuzzy logic according to the present invention and gets one of wicket circuit theory diagrams.
Fig. 8 illustrates fuzzy logic according to the present invention and gets two of wicket circuit theory diagrams.
Fig. 9 illustrates fuzzy logic according to the present invention and gets one of gate circuit theory diagrams.
Figure 10 illustrates fuzzy logic according to the present invention and gets two of gate circuit theory diagrams.
Figure 11 illustrates according to fuzzy logic adding circuit schematic diagram of the present invention.
Figure 12 illustrates according to fuzzy logic subtraction circuit schematic diagram of the present invention.
Figure 13 illustrates according to one of fuzzy logic not circuit schematic diagram of the present invention.
Figure 14 illustrates according to two of fuzzy logic not circuit schematic diagram of the present invention.
[embodiment]
The fuzzy microprocessor of inlaid self-adaptive of the present invention adopts fuzzy logic circuit and two-valued function circuit be combined into.The parts that every any R system data-signal or simulating signal will be passed through all adopt the fuzzy logic circuit to constitute, if the parts that have only binary signal to pass through separately then adopt the two-valued function circuit to constitute.In the fuzzy microprocessor of the inlaid self-adaptive shown in Fig. 1, except that self-adaptation arithmetic and logic unit ALU, threshold gate, D/A1, D/A2 and control gate 1.～3., all the other each functional parts are the two-valued function parts.
Fig. 2 is a self-adaptation arithmetic and logic unit structural drawing provided by the invention.It mainly is made of self-adaptation full adder and self-adaptation full subtracter and some logical operation circuits.When the E end is high level, carry out arithmetical operation: if I
2I
1I
0During=HHH, carry out additive operation, promptly F=A adds B; If I
2I
1I
0During=HHL, carry out subtraction, promptly F=A subtracts B.When the E end is low level, carry out logical operation:
If I
2I
1I
0During=HHH, get macrooperation, i.e. F=A ∨ B
If I
2I
1I
0During=HHL, get big inverse, promptly F=(A ∨ B) is non-
If I
2I
1I
0During=HLH, get little computing, i.e. F=A ∧ B
If I
2I
1I
0During=HLL, get little inverse, promptly F=(A ∧ B) is non-
If I
2I
1I
0During=LHH, carry out threshold operation, i.e. F=A ⊙ B
If I
2I
1I
0During=LHL, carry out the threshold inverse, promptly F=(A ⊙ B) is non-
If I
2I
1I
0During=LLH, carry out the A inverse, promptly F=A is non-
If I
2I
1I
0During=LLL, carry out the B inverse, promptly F=B is non-
Fig. 3 is a self-adaptation full adder building-block of logic provided by the invention.Among the figure with input end A
iLevel and the carry control signal U of input
CiIn fuzzy logic threshold gate G0, compare, work as A
i=U
CiThe time, door G0 is output as maximum level, otherwise door G0 is output as minimum level.The input end of two-value and door G1 is delivered in the output of door G0, and another input of door G1 is U
Ci, to have only when two inputs of door G1 are high level, the output of door G1 just is high level.The output of door G1 divides three the tunnel to transmit, and one the tunnel delivers to two-valued function or door G2 as carry control signal U
C0Output, another road is delivered to fuzzy logic and is got wicket G12.When Ruo Dangmen G1 is output as maximum level, just allow addend B
iDeliver to fuzzy logic by door G12 and get gate G15 as adding entirely and counting S
iOutput, the carry control signal U of door G2 output this moment
C0Be high level.The high level of door G1 output is got wicket G13 with fuzzy logic after two-valued function not gate G11 negate simultaneously, door G14 blocks.Remove B this moment
iIn addition, the status information of the operation of other circuit all can not be sent to the input end of a G15, not that is to say to influence operation result, and which kind of state comparator circuit G6 this moment (adopting the fuzzy logic comparator circuit) is output as and can have influence on a maximum level of G2 output.Thereby realized the full adder operational method 1. as (A
i+ C
I-1) greater than R-1, i.e. (A
i+ C
I-1During)=radix R, add entirely and S
i=B
i, produce carry C
i=1.
Carry control signal U when input
CiDuring for high level, fuzzy logic is got wicket G3 and is exported 1 level, is equivalent to C
I-1=1; Carry control signal U when input
CiDuring for low level, fuzzy logic is got wicket G3 and is exported 0 level, is equivalent to C
I-1=0.Fuzzy logic adding circuit G5 and addend A are delivered in the output of door G3
iAddition is promptly finished (A in door G5
i+ C
I-1) computing.The operation result of the output of door G5 is delivered to fuzzy logic comparator circuit G6, fuzzy logic adding circuit G7 and fuzzy logic subtraction circuit G9 respectively.Addend B
iBy delivering to fuzzy logic comparator circuit G6 and fuzzy logic adding circuit G8 after the fuzzy logic not gate G4 negate.(A
i+ C
I-1) and B
iRadix-minus-one complement in door G6, compare.
As (A
i+ C
I-1) be less than or equal to B
iRadix-minus-one complement the time, door G6 output minimum level, door G6 output is connected respectively to two-valued function or door G2, two-valued function not gate G10 and fuzzy logic and gets wicket G14.Door G13 is opened in the output of door G6 after door G10 negate.To in fuzzy logic adding circuit G7, finish (A
i+ C
I-1)+B
iOperation result as adding entirely and S
iExport through door G15 again by door G13.This moment, door G1 output also was minimum level, so the carry control signal U of door G2 output
C0Be low level, the expression no-carry.Thereby realized the full adder operational method 2. as (A
i+ C
I-1) be less than or equal to B
iRadix-minus-one complement the time, add entirely and S
i=(A
i+ C
I-1)+B
i, this moment no-carry C
i=0.
As (A
i+ C
I-1) greater than B
iRadix-minus-one complement the time, a door G6 then exports high level, opens a door G14, closes a G13 by door G10 after anti-phase simultaneously, the low level of door G1 output is closed door G12.Meanwhile door G8 finishes B
iRadix-minus-one complement add 1, make it to become B
iComplement code, in door G9, finish (A
i+ C
I-1)-B
I mendsComputing, and with its result as adding entirely and S
iExport through door G15 again by door G14.Because door G6 is output as high level, so the carry control signal U of door G2 output
C0Also be high level, expression has carry.Thereby realized the full adder operational method 3. as (A
i+ C
I-1) greater than B
iRadix-minus-one complement the time, add entirely and S=(A
i+ C
I-1)-B
Mend, carry C
i=1.Actual parallel the carrying out of aforesaid operations.
Fig. 4 is a self-adaptation full subtracter building-block of logic provided by the invention.Among the figure with input end A
iLevel and 0 level compare in fuzzy logic threshold gate G16, work as A
i=0 o'clock, door G16 was output as maximum level, otherwise door G16 is output as minimum level.The input end of two-value and door G17 is delivered in the output of door G16, and another input of door G17 is U
Ji, when two inputs just thinking a G17 were high level, the output of door G17 just was high level.The output of door G17 divides three the tunnel to transmit, and one the tunnel delivers to two-valued function or door G18 as borrow control signal C
JoOutput, another road is delivered to fuzzy logic and is got wicket G28.When Ruo Dangmen G17 is output as maximum level, just allow the subtrahend B that transmits through door G20
iRadix-minus-one complement deliver to fuzzy logic by door G28 and get gate G31 as one's own department or unit difference D
iOutput, the borrow control signal C of door G18 output this moment
JoBe high level.The high level of door G17 output is got wicket G29 with fuzzy logic after two-valued function not gate G27 negate simultaneously, door G30 blocks.Remove B this moment
iRadix-minus-one complement beyond, the operation result of other circuit all can not be delivered to the input end of a G31, not that is to say to influence operation result, and which kind of state comparator circuit G22 this moment (adopting the fuzzy logic comparator circuit) is output as and can have influence on a maximum level of G18 output.Thereby 1. that has realized the full subtracter operational method works as A
i=0, C
Ji-1=1 o'clock, one's own department or unit difference D
i=B
iRadix-minus-one complement, need to high-order borrow, C
Ji=1, i.e. borrow control signal U
JoBe high level.
Borrow control signal U when input
JiDuring for high level, fuzzy logic is got wicket G19 and is exported 1 level, is equivalent to C
Ji-1=1; Carry control signal U when input
JiDuring for low level, fuzzy logic is got wicket G19 and is exported 0 level, is equivalent to C
Ji-1=0.Fuzzy logic subtraction circuit G21 is delivered in the output of door G19, finishes (A in door G21
i-C
Ji-1) computing.The operation result of the output of door G21 is delivered to fuzzy logic comparator circuit G22, fuzzy logic subtraction circuit G23 and fuzzy logic adding circuit G25 respectively.(A
i-C
Ji-1) operation result and B
iIn door G22, compare.
As (A
i-C
Ji-1) more than or equal to B
iThe time, door G22 output maximum level.Door G22 output is connected respectively to two-valued function not gate G26 and fuzzy logic is got wicket G29.Door G29 is opened in the output of door G22.To in fuzzy logic subtraction circuit G23, finish (A
i-C
Ji-1)-B
iOperation result as one's own department or unit difference D
iExport through door G31 again by door G29.Door G17 output this moment and door G26 output are minimum level, so the borrow control signal C of door G18 output
JoBe low level, represent no borrow.Thereby realized the full subtracter operational method 2. as (A
i-C
Ji-1) more than or equal to B
iThe time, one's own department or unit difference D
i=(A
i-C
Ji-1)-B
i, C
Ji=0, i.e. borrow output control signal U
JoIt is 0 level.
As (A
i-C
Ji-1) less than B
iThe time, door G22 then exports minimum level, closes a G29, and by the anti-phase unlatching door of door G26 G30, the low level of door G17 output is closed door G28 simultaneously.Subtrahend B
iBy delivering to fuzzy logic adding circuit G24 after the fuzzy logic not circuit door G20 negate, G24 finishes B at door
iRadix-minus-one complement add 1, make it to become B
iComplement code, in fuzzy logic adding circuit G25, finish (A
i-C
Ji-1)+B
I mendsComputing, and with its result as one's own department or unit difference D
iExport through door G31 again by door G30.Because door G26 is output as high level, so the borrow control signal U of door G18 output
JoAlso be high level, expression has borrow.Thereby realized the full subtracter operational method 3. as (A
i-C
Ji-1) less than B
iThe time, one's own department or unit difference D
i=(A
i-C
Ji-1)+B
Mend, C
Ji=1, i.e. borrow control output system signal U
JoBe high level.Aforesaid operations is parallel to carry out.
Fuzzy logic threshold gate circuit shown in Fig. 5, it by 6 metal-oxide-semiconductor M1 pipe～M6 manage, a triode T and a diode D constitute.Wherein M1 pipe, M2 pipe constitute input circuit, and the M3 pipe is its load.Triode, M1 pipe～M3 pipe and diode constitute output circuit.Diode plays the effect of resistance, and back resistance is very big.Threshold gate has V
AAnd V
BTwo input ends, VO are output terminal.As two input end level V
A=V
BThe time, M1 pipe, M2 pipe all end, and triode T ends, and M5 manages conducting, and the M6 pipe ends, and exports VO ≈ V this moment
DDAs two input end level V
A≠ V
BThe time, M1 manages, M2 manages just a conducting in two pipes, and another ends, and triode and M4 manage new conducting, and the M5 pipe ends, and M6 manages conducting, exports VO ≈ 0 current potential this moment.Thereby realized the threshold logic computing.
Shown in Fig. 6 is fuzzy logic variable window threshold not circuit.It by 6 metal-oxide-semiconductor M1 pipe～M6 manage, a triode T forms, M1 pipe, M2 pipe and M5 pipe are formed input circuit, M3 pipe, M4 pipe, M6 pipe and transistor T are formed active load.It has V
A, V
B, V
CThree input ends, a VO output terminal.As two input end level V wherein
A=V
BThe time, export VO ≈ 0 current potential this moment.As two input end level V wherein
A≠ V
BThe time, export VO ≈ V this moment
DDCurrent potential.Thereby realized the computing of variable window threshold NOT logic, V
CBe window width.
Shown in Fig. 7 is that five input end fuzzy logics are got wicket.Circuit structure is simple, and fan-in factor is unrestricted, and this figure circuit can be realized V
0=V
A∧ V
B∧ V
C∧ V
D∧ V
EGet little computing.Shown in Fig. 8 is that three input ends are got little gate circuit.N channel enhancement load pipe M4 pipe, M5 pipe and M6 pipe are connected among the figure, and P-channel enhancement type driving tube M1 pipe, M2 pipe and M3 pipe are in parallel.V
A, V
BAnd V
CBe input end, V
0Be output terminal.If work as V
A=V
B=V
C, and all rise to the circuit ceiling voltage gradually continuously from 0V, and M1 manages, M2 manages and the M3 pipe tends to end from saturation conduction gradually, and M4 pipe, M5 pipe and M6 pipe then tend to saturation conduction from ending gradually, output V
0Also follow input end and rise to the circuit ceiling voltage gradually continuously from 0V.When a certain end input voltage is lower than other end input voltages, output V
0It then is the minimum input voltage in the input end.Realized V
0=V
A∧ V
B∧ V
CGet little computing.
Shown in Fig. 9 is that fuzzy logic is got one of big gate circuit, and it has four-input terminal.N channel enhancement load pipe M1 pipe～M4 pipe is in parallel among the figure, and P-channel enhancement type driving tube M5 pipe～M8 pipe is connected.V
A, V
B, V
CAnd V
DBe input end, V
0Be output terminal.If work as V
A=V
B=V
C=V
D, and applied signal voltage all rises to supply voltage value gradually continuously from 0V, and M1 pipe～M4 pipe is from by tending to saturation conduction gradually, and M5 pipe～M8 manages and then tends to gradually end output voltage V from saturation conduction
0Also follow applied signal voltage and rise to supply voltage value gradually continuously from 0V.When a certain end applied signal voltage is higher than other end applied signal voltages, output V
0Then equal the highest input signal voltage in the input end.Thereby realized V
0=V
A∨ V
B∨ V
C∨ V
DGet macrooperation.What Figure 10 showed is to get two of big gate circuit, and it has two input ends, can realize V
0=V
A∨ V.
Shown in Figure 11 is adding circuit.M1 pipe～M4 pipe constitutes difference channel.M6 pipe, M7 pipe and resistance R 1, R2 constitute input circuit, require M6 pipe and M7 pipe two pipe parameter symmetries, R1=R2, and its resistance is less.V
AAnd V
BBe the adding circuit input end.The M5 pipe is efferent duct, V
0Be output terminal.M8 pipe, M9 pipe and diode D1, D2 all play resistance.This adding circuit can be realized V
0=V
A+ V
B
Shown in Figure 12 is subtraction circuit.M1 pipe～M4 pipe constitutes difference channel.M6 pipe and M7 pipe constitute V
AInput circuit, M8 pipe, M9 pipe constitute V
BInput circuit.The M5 pipe is efferent duct, V
0Be output terminal.M6 pipe～M9 pipe and diode D1, D2 all play resistance.This circuit can be realized V
0=V
A-V
B
Shown in Figure 13 is one of fuzzy logic not circuit.This circuit is taked the method for " cutting bent cut-off ".If power supply is V
DD, as input end signal voltage V
AChange to V from the continuous linearity of 0V
DDThe time, then can be divided into two sections from M1 pipe and M4 pipe to the variation of the output signal voltage of pipe, one section from V
DDChange to V continuously
DDThe/2nd, rectilinearity changes section, and meets V
AThe relation of negate, another section is from V
DD/ 2 beginnings then are the curvilinear motion sections, and it is not from V
DD/ 2 linearities change to 0V, but from V
DD/ 2 non-linearly change to a certain magnitude of voltage, and this section does not meet V
AThe relation of negate; Applied signal voltage remains unchanged, if also can be divided into two sections from M2 pipe and M5 pipe to the variation of managing output signal voltage, one section changes to V from a certain magnitude of voltage
DDThe/2nd, curve variation section, this section does not meet V
AThe relation of negate, but from V
DDIt then is straight-line segment that/2 beginning linearities change to 0V, and this section meets V
AThe relation of negate.M3 pipe and M6 pipe are exactly that these two curves to pipe are partly clipped to the effect of pipe, and both rectilinearity are partly combined.Thereby realize V
0=V
AInverse.
Shown in Figure 14 is two of fuzzy logic not circuit.It is to realize on subtraction circuit basis shown in Figure 13, with the V of subtraction circuit
AInput end is connected to power supply V
DD, with its V
BInput end changes V into
AInput end has just become not circuit.Can realize V
0=V
AInverse.
Embodiment provided by the invention exemplaryly is not construed as limiting the present invention.As what propose in claims, all alternative all are comprised in the category of the present invention.
Claims (10)
1. an inlaid self-adaptive blurs microprocessor, and its feature comprises:
The composition of the fuzzy microprocessor of this inlaid self-adaptive.It is by fuzzy logic functional part and two-valued function functional part be combined into.Mainly comprise 1 or multi-bit parallel carry self-adaptation arithmetic and logic unit (ALU), controller, programmable counter (PC), general/the special register group, Timer, digital to analog converter (D/A1, D/A2 or a plurality of D/A), control gate, differentiation register (RF1, RF2), comparer, impulse source/start and stop/frequency dividing circuit, Cache (or EPROM) and three groups of bus functional parts such as (AB, DB, CB).The exclusive data exchange register will be delivered to D/A1 respectively from the binary data of Cache (or EPROM), D/A2 changes.1. the output of D/A1 deliver to the A input end of ALU through control gate, and another road input of the A end of ALU is from control gate output 2., and control gate input end is 2. delivered in the input of the outside A end of processor.The B input end of ALU is directly delivered in the B end input of processor outside.The carry C input end of ALU is directly delivered in the output of D/A2, for ALU provides different carry C level.3. the output one tunnel of ALU deliver to the Fo output terminal of processor through control gate.An input end of comparer is directly delivered on another road of ALU output, and the data of sending here with differentiation register RF1 compare in comparer.The comparative result of comparer is exported one tunnel Zo output terminal of delivering to processor, and another Lu Zejing differentiates register RF2 and delivers in the general-purpose register.
This microprocessor adapts to the method for any R system additive operation.Comprise: 1. as (A
i+ C
I-1) greater than R-1, i.e. (A
i+ C
I-1During)=radix R, one's own department or unit and number S
i=B
i, C
i=1; 2. as (A
i+ C
I-1) be less than or equal to B
iRadix-minus-one complement the time, one's own department or unit and the number S
i=(A
i+ C
I-1)+B
i, C
i=0; 3. as (A
i+ C
I-1) greater than B
iRadix-minus-one complement the time, one's own department or unit and the number S
i=(A
i+ C
I-1)-B
Mend, C
i=1.Wherein R is a radix, A
iAnd B
iBe respectively summand and addend, C
I-1Be carry, S from low level
iBe one's own department or unit and number, C
iFor producing carry to a high position.
This microprocessor adapts to the method for any R system subtraction.Comprise: 1. work as A
i=0, C
Ji-1=1 o'clock, one's own department or unit difference D
i=R-1-B
i, i.e. D
i=B
iRadix-minus-one complement, C
Ji=1; 2. as (A
i-C
Ji-1) more than or equal to B
iThe time, one's own department or unit difference D
i=(A
i-C
Ji-1)-B
i, C
Ji=0; 3. as (A
i-C
Ji-1) less than B
iThe time, one's own department or unit difference D
i=(A
i-C
Ji-1)+B
Mend, C
Ji=1; Wherein R is a radix, A
iAnd B
iBe respectively minuend and subtrahend, C
Ji-1Be borrow, D from low level
iBe one's own department or unit difference, C
JiBe the borrow of need to a high position.
Self-adaptation arithmetic and logic unit in this microprocessor is the fuzzy logic functional part.Mainly by self-adaptation full adder Q1, self-adaptation full subtracter Q2, fuzzy logic get the gate, fuzzy logic is got fuzzy logic circuit such as wicket, fuzzy logic threshold gate, fuzzy logic threshold not gate, fuzzy logic not gate and is constituted.
2. self-adaptation arithmetic and logic unit according to claim 1 is got gate G32, door G52, door G53 and door G56 by self-adaptation full adder Q1, self-adaptation full subtracter Q2, fuzzy logic, fuzzy logic is got wicket G33 and door G40～door G51, fuzzy logic threshold gate G34, fuzzy logic threshold not gate G35, fuzzy logic not gate G54, two-valued function not gate G36～door G39, circuit such as two-valued function or door G55 constitute.U
CiBe carry (borrow) control input end, C
I-1Be carry (borrow) value input, A
iAnd B
iBe respectively two any R system numeric datas or two arbitrary value logical data input ends, the E end is Enable Pin, and when the E end was high level, the self-adaptation arithmetic and logic unit carried out the arithmetic plus and minus calculation, when E holds to low level, then carries out logical operation.I
2I
1I
0The calculation function of assembled state decision self-adaptation arithmetic and logic unit.U
C0Be carry (borrow) control output end, F
oBe the operation result output terminal.According to U
C0And F
oCan constitute multi-bit parallel carry arithmetical unit.
Carry (borrow) control input U
CiEnd connects the U of full adder Q1
CiThe U of end and full subtracter Q2
JiEnd, carry (borrow) numerical value input C
I-1End connects the C of full adder Q1
I-1The C of end and full subtracter Q2
Ji-1End.A
iAnd B
iEnd connects A, the B end of full adder Q1 and A, the B of full subtracter Q2 end and door G32～door G35 etc. input end, A respectively
iAlso the input end with door G50 links to each other, B
iAlso the input end with door G51 links to each other.The U of Q1
C0Output terminal is connected to the input end of a G40, the S of Q1
iOutput terminal is connected to the input end of a G41.The U of Q2
J0Output terminal is connected to the input end of a G42, the D of Q2
iOutput terminal is connected to the input end of a G43.The output of door G32 is connected to the input end of a G44 and the input end of door G48.The output of door G33 is connected to the input end of a G45 and the input end of door G49.The output of door G34 is connected to the input end of a G46, and the output of door G35 is connected to the input end of a G47.I
2End is connected to input and the input of door G40～door G45 and the input of door G48, door G51 of a G36.I
1End is connected to input and the input of door G40～door G44 and the input of door G46～door G48 of a G37.I
0End is connected to the input of a G38 and the input that door G40, door G41, door G44, door G45, door G46 and door G50 etc. get wicket.The output of door G36 is connected to the input that a G46, door G47, door G50, door G51 etc. get wicket.The output of door G37 is connected to the input that a G45, door G49, door G50, door G51 etc. get wicket.The output of door G38 is connected to the input that a G42, door G43, door G47, door G48, door G49, door G51 etc. get wicket.The E end is connected to the input of a G39～each gate circuit of door G43.The output of door G39 is connected to a G44～door G51 and respectively gets the input of wicket.The output of door G44～door G47 is connected respectively to each input end of a G52, and the output of door G48～door G 51 is connected respectively to each input end of a G53.The input that a G54 is linked in the output of door G53.Two input ends of a G55 are linked in the output of the output of door G40 and door G42 respectively, and door G55 is output as carry (borrow) control output end U
C0Door G41, door G43, door G52 and each output of door G54 are connected respectively to each input end of a G56, and a door G56 is output as operation result F
oOutput terminal.
3. the method for any R system of adaptation according to claim 1 additive operation.Both voltage available type circuit was realized, also available current type circuit is realized, also available non-electronic technology realizes.Self-adaptation full adder Q1 in the present embodiment adopts the level of R different height to represent 0,1,2 to any radix R ..., (R-1) wait R numeral.With output carry control signal U
C0Replace carry C
i, when producing, represent U with the maximum level in the system to high-order carry
C0, represent U with minimum 0 level in the system when not producing carry
C0Be C
i=1 o'clock, U
C0Be high level; C
i=0 o'clock, U
C0It is 0 level.With U
C0Deliver to high-order input carry control end U
Ci, i.e. U
Ci=U
C0Use U
CiThe carry C of control input
I-1Be 1 to be 0 still, work as U
CiDuring for high level, C
I-1=1, work as U
CiDuring for low level, C
I-1=0.The operational method of the described self-adaptation full adder of claim 1 just becomes like this: 1. as expression A
iLevel=U
CiLevel, and when being maximum level adds entirely and counts S
i=B
i, and produce to high-order carry, this moment U
C0Level then is the maximum level in the system; 2. as (A
i+ C
I-1) be less than or equal to B
iRadix-minus-one complement the time, add entirely and count S
i=(A
i+ C
I-1)+B
i, no-carry, U at this moment
C0Level is 0 level in the system; 3. as (A
i+ C
I-1) greater than B
iRadix-minus-one complement the time, add entirely and count S
i=(A
i+ C
I-1)-B
Mend, produce to high-order carry, at this moment U
C0Level is the maximum level in the system.
A kind of self-adaptation full adder that provides according to claim 2 with according to above-mentioned operational method.A
i, B
iBe the input end of two any R system addends, U
CiBe carry signal input end, C
I-1Be the carry value input; S
iBe the output terminal of one's own department or unit and number, U
C0Be the carry control signal output ends; Wherein door G0 is the fuzzy logic threshold gate, door G3, door G12, door G13 and door G14 are fuzzy logic and get wicket, door G4 is the fuzzy logic not gate, door G5, door G7 and door G8 are the fuzzy logic adding circuit, and door G6 is the fuzzy logic comparator circuit, and door G9 is the fuzzy logic subtraction circuit, door G15 then gets the gate for fuzzy logic, door G1 then is two-valued function and door, and door G2 then is two-valued function or door, and door G10 and door G11 are the two-valued function not gate.
A
iEnd connects the input end of door G0 and the input end of door G5, B respectively
iEnd connects the input end of a door G4, door G7 and the input end of door G12 respectively.U
CiEnd connects the input end of another input end of door G0 and door G1 and the input end of door G3 respectively.Carry C
I-1End connects another input end of door G3 and the input end of door G8 respectively, and the output of door G0 connects another input end of door G1, and the output of door G1 connects the input end of input end of a G2 and door G11 input end and door G12 respectively.The output of door G3 is connected to the input end of a G5, and the output of door G5 connects the input end of a G6 and door G7 and door G9 respectively.Door G7 output connects the input end of door G13.The output of door G4 connects another input end of a G6 and the input end of door G8 respectively.The output of door G8 connects another input end of door G9, and the output of door G9 connects the input end of door G14.Door G6 output connects the input end of door G2 and door G10 and door G14 respectively, and the output of door G10 connects the input end of door G13.The output of door G11 connects the input end of a G13 and door G14 respectively.Door G12, door G13 are connected three input ends of a G15 respectively with the output of door G14, and a door G15 is output as and adds entirely and S
i, S
i=A
i+ B
iDoor G2 output U
C0As control signal to high-order carry.
4. the method for any R system of adaptation according to claim 1 subtraction.Both voltage available type circuit was realized, also available current type circuit is realized, also available non-electronic technology realizes.Self-adaptation full subtracter Q2 in the present embodiment is identical with numeral level in the above-mentioned full adder to any radix R numeric representation method.Handle borrow C
JiThe also similar above-mentioned full adder of method handle carry C
iMethod.With output borrow control signal U
JoReplaced C
Ji, when need are represented U with the maximum level in the system during to high-order borrow
Jo, do not represent U with minimum 0 level in the system when having borrow
JoBe C
i=1 o'clock, U
JoBe maximum level; During Ci=0, U
JoIt is 0 level.With U
JoDeliver to high-order borrow input control end U
Ji, i.e. U
Ji=U
JoUse U
JiThe borrow C of control input
Ji-1Be 1 to be 0 still, work as U
JiDuring for high level, C
Ji-1=1, work as U
JiDuring for low level, C
Ji-1=0.The operational method of the described self-adaptation full subtracter of claim 1 just can be changed into like this: 1. as expression A
iLevel=0 level, U
JiDuring=maximum level, one's own department or unit difference D
i=R-1-B
i, need to high-order borrow, at this moment U
JoLevel then is the maximum level in the system; 2. as (A
i-C
Ji-1) more than or equal to B
iThe time, one's own department or unit difference D
i=(A
i-C
I-1)-B
i, no borrow, U at this moment
JoLevel is the minimum level in the system; 3. as (A
i-C
Ji-1) less than B
iThe time, one's own department or unit difference D
i=(A
i-C
Ji-1)+B
Mend, need to high-order borrow, at this moment U
JoLevel is the maximum level in the system.
A kind of self-adaptation full subtracter that provides according to claim 2 with according to above-mentioned full subtracter general-purpose operation method.A wherein
i, B
iBe the input end of any R system minuend and subtrahend, U
JiBe borrow signal input end, C
Ji-1Be the borrow value input; D
iBe the output terminal of one's own department or unit difference, U
JoBe the borrow control signal output ends; Wherein door G16 is the fuzzy logic threshold gate, door G19, door G28, door G29 and door G30 are fuzzy logic and get wicket, door G20 is the fuzzy logic not gate, door G21, door G23 are the fuzzy logic subtraction circuit, and door G22 is the fuzzy logic comparator circuit, and door G24 and door G25 are the fuzzy logic adding circuit, door G31 then gets the gate for fuzzy logic, door G17 then is two-valued function and door, and door G18 then is two-valued function or door, and door G26 and door G27 are the two-valued function not gate.The logical organization of full subtracter and the logical organization of above-mentioned full adder are similar substantially, and employed logical circuit is also basic identical.
A
iEnd connects the input end of door G16 and the input end of door G21, B respectively
iEnd connects the input end of a door G20, door G22 and the input end of door G23 respectively.C
JiEnd connects the input end of door G17 and the input end of door G19 respectively.Borrow C
Ji-1End connects another input end of door G19 and the input end of door G24 respectively.Another input end grounding of door G16, the output of door G16 connects another input end of door G17, and the output of door G17 connects the input end of input end of a G18 and door G27 input end and door G28 respectively.The output of door G19 is connected to the input end of a G21, and the output of door G21 connects the input end of a G22 and door G23 and door G25 respectively.The output of door G23 connects the input end of door G29.The output of door G20 connects another input end of a G24 and the input end of door G28 respectively.The output of door G24 connects another input end of door G25, and the output of door G25 connects the input end of door G30.Door G22 output connects the input end of door G26 and door G29 respectively, and the output of door G26 connects the input end of door G18 and door G30.The output of door G27 connects the input end of a G29 and door G30 respectively.Door G28, door G29 are connected three input ends of a G31 respectively with the output of door G30, and a door G31 is output as one's own department or unit difference D
i, door G18 output U
JoAs control signal to high-order borrow.
5. fuzzy logic threshold gate according to claim 1.It has V
A, V
BTwo input ends, a V
0Output terminal.It is made of 6 metal-oxide-semiconductor M1 pipe～M6 pipe and 1 transistor T and 1 diode D.Wherein M1 pipe, M2 pipe, M4 pipe, M6 pipe are the NMOS pipe, and M3 pipe, M6 pipe are the PMOS pipe.The source S of M1 tube grid G and M2 pipe links together as the V of threshold gate
AInput end, the source S of the grid G of M2 pipe and M1 pipe is connected together as the V of threshold gate
BInput end.M1 pipe drain electrode d, the M2 pipe drain electrode d and the source S of M3 pipe and the base stage of triode link together.The grid G of M3 pipe and drain electrode d, the emitter of triode and the drain electrode d of M5 pipe are connected to positive source.The grid G of the grid G of the collector of triode and M4 pipe, drain electrode and M5 pipe links together.The grid G of the source S of M4 pipe and diode cathode and M6 pipe links together.The positive pole of diode all is connected earth potential with M6 pipe source S.The drain electrode d of the source S of M5 pipe and M6 pipe links together as V
0Output terminal.
If the connection of M1 tube grid G and M2 pipe between the source S in the fuzzy logic threshold gate disconnected, M1 tube grid G is separately as the V of threshold gate
AInput end, the source S of M2 pipe are separately as the V of threshold gate window voltage
CInput end, V
BInput end remains unchanged, and other parts of circuit also remain unchanged.This just becomes the variable window threshold gate.
If the connection of the input circuit M1 pipe～M3 pipe of maintenance three input end variable window threshold gates is constant, change its output circuit into active load.Be that M4 pipe～M6 pipe and transistor T are formed active load.M1 pipe, the drain electrode d of M2 pipe and the source S of M3 pipe and the grid G of M4 pipe and the base stage of transistor T link together.The emitter of M4 pipe drain electrode d and transistor T all meets power supply V
DD, the grid G of the drain electrode d of the source S of M4 pipe, M5 pipe and grid G, M6 pipe links together.The equal ground connection of source S of M5 pipe, M6 pipe.The drain electrode d of M6 pipe and the collector of transistor T link together as V
0Output terminal.So just, become variable window threshold not gate.
As long as V with three input end variable window threshold not gates
CInput end and V
AInput end links together as V
AInput end, other parts of circuit remain unchanged, and have so just become V
A, V
BTwo input end threshold not gates.
6. fuzzy logic according to claim 1 is got wicket.Its circuit provided by the invention is made of 7 metal-oxide-semiconductor M1 pipe～M7 pipes, and wherein M1 pipe～M6 pipe is the PMOS pipe, and the M7 pipe is the NMOS pipe.M1 pipe～M5 pipe is five input pipes, and their grid G is respectively as V
A, V
B, V
C, V
DAnd V
EInput end, the equal earthing potential of source S of their source S and M6 pipe, their drain electrode d and M6 tube grid G, M7 tube grid G link together.M6 pipe and M7 pipe constitute the output stage of getting wicket, and the drain electrode d of M7 pipe meets power supply V
DD, the drain electrode d of the source S of M7 pipe and M6 pipe links together as V
0Output terminal.It is unrestricted that this gets wicket input pipe quantity, and promptly fan-in factor is unrestricted.
Fuzzy logic according to claim 1 is got wicket, the invention provides two of its circuit.It is made of 6 metal-oxide-semiconductor M1 pipe～M6 pipes, and wherein M1 pipe～M3 pipe is the PMOS pipe, and M4 pipe～M6 pipe is the NMOS pipe.The grid G of the grid G of M1 pipe and M4 pipe links together as V
AInput end, the grid G of the grid G of M2 pipe and M5 pipe links together as V
BInput end, the grid G of the grid G of M3 pipe and M6 pipe links together as V
CInput end.The equal earthing potential of source S of M1 pipe, M2 pipe and M3 pipe.M1 pipe, M2 pipe and the drain electrode d of M3 pipe and the source S of M6 pipe link together as V
0Output terminal.The drain electrode d of M6 pipe is connected with the source S of M5 pipe, and the drain electrode d of M5 pipe is connected with the source S of M4 pipe, and the drain electrode d of M4 pipe connects power supply V
DD
7. fuzzy logic according to claim 1 is got the gate.The invention provides one of its circuit.It is made of 8 metal-oxide-semiconductor M1 pipe～M8 pipes, and wherein M1 pipe～M4 pipe is the NMOS pipe, and M5 pipe～M8 pipe is the PMOS pipe.The grid G of the grid G of M1 pipe and M5 pipe links together as V
AInput end, the grid G of the grid G of M2 pipe and M6 pipe links together as V
BInput end, the grid G of the grid G of M3 pipe and M7 pipe links together as V
CInput end.The grid G of the grid G of M4 pipe and M8 pipe links together as V
DInput end.The drain electrode d of M1 pipe～M4 pipe all meets power supply V
DDThe source S of M1 pipe～M4 pipe and the drain electrode d of M5 pipe link together as the V that gets the gate
0Output terminal.The source S of M5 pipe is connected with the drain electrode d of M6 pipe, and the source S of M6 pipe is connected with the drain electrode d of M7 pipe, and the source S of M7 pipe is connected with the drain electrode d of M8 pipe, the source S earthing potential of M8 pipe.Fuzzy logic according to claim 1 is got the gate.The invention provides two of circuit.It is made of 4 metal-oxide-semiconductors such as M1 pipe～M4 pipes, and wherein M1 pipe～M2 pipe is the PMOS pipe, and M3 pipe～M4 pipe is the NMOS pipe.M2 pipe, the grid G of M4 pipe and the source S of M1 pipe link together as V
AInput end.M1 pipe, the grid G of M3 pipe and the source S of M2 pipe link together as V
BInput end.The source S of the drain electrode d of M1 pipe, M2 pipe and M3 pipe, M4 pipe links together as the V that gets the gate
0Output terminal.The drain electrode d of M3 pipe, M4 pipe all meets power supply V
DD
8. according to claim 3 and the described fuzzy logic totalizer of claim 4.It by 9 metal-oxide-semiconductor M1 pipe～M9 manage, 2 diode D1, D2 and 2 resistance R 1, R2 constitute.Wherein M1 pipe, M2 pipe, M7 pipe～M9 pipe are the NMOS pipe, and M3 pipe～M6 pipe is the PMOS pipe.Form difference channel by M1 pipe～M4 pipe.The source S of the source S of M1 pipe and M2 pipe is connected the plus earth of diode D1 with the negative pole of diode D1.The grid g of the drain electrode d of M1 pipe and the source S of M3 pipe and PMOS pipe M5 links together.M3 pipe, the grid g of M4 pipe and the source S of M4 pipe and the drain electrode d of M2 pipe link together, and the drain electrode d of M3 pipe～M5 pipe all meets power supply V
DDM6 pipe drain electrode d links to each other as V with substrate b
AInput end, the drain electrode d of M7 pipe links to each other as V with substrate b
BInput end.The grid G of M6 pipe meets power supply V
DD, the grid G ground connection of M7 pipe, the source S of M6 pipe, M7 pipe is connected with the grid G of difference channel M1 pipe by resistance R 1, R2 respectively.The drain electrode d of the M2 tube grid G of difference channel and the grid G of M8 pipe, drain electrode d and substrate b and M9 pipe links together.The grid G of M9 pipe and source S and substrate b ground connection.The negative pole of the source S of the source S of M8 pipe and M5 pipe and diode D2 links together as V
0Output terminal, the plus earth of diode D2.
9. according to claim 3 and the described fuzzy logic subtracter of claim 4.It by 9 metal-oxide-semiconductor M1 pipe～M9 manage, 2 diode D1, D2 constitute.Wherein M1 pipe, M2 pipe are the NMOS pipe, and M3 pipe～M9 is the PMOS pipe.Form difference channel by M1 pipe～M4 pipe.M1 pipe～M4 pipe, M5 pipe and diode D1, D2 structure connected mode are the same with the connected mode of pairing each pipe of claim 8.The just input circuit part that the fuzzy logic subtraction circuit is different with the fuzzy logic adder circuit.The M6 pipe of fuzzy logic subtracter, M7 tube grid G all meet power supply V
DD, the drain electrode d of M6 pipe links to each other as V with substrate b
AInput end.The drain electrode d of the source S of M6 pipe and M7 pipe and substrate b are connected with the grid G of M1 pipe, the source S ground connection of M7 pipe.The drain electrode d of the grid G of the grid G of M2 pipe and M8 pipe, drain electrode d and substrate b and M9 pipe links together.The grid G of M9 pipe and source S and substrate b link together as V
BInput end.The negative pole of the source S of the source S of M8 pipe and M5 pipe and diode D2 links together as V
0Output terminal.
10. fuzzy logic not gate according to claim 1, the invention provides circuit has two kinds of structures.First kind of not gate is made of 6 metal-oxide-semiconductors such as M1 pipe～M6 pipes, and wherein M1 pipe～M4 pipe is the PMOS pipe, and M5 pipe, M6 pipe are the NMOS pipe.The grid G of M1 pipe, M3 pipe, M5 pipe and M6 pipe links together as not gate V
AInput end.The drain electrode d of M1 pipe, M2 pipe all connects positive source.The drain electrode d of the source S of M1 pipe and M4 pipe and the source S of M6 pipe link together.The equal earthing potential of the source S of the grid G of M4 pipe and source S and M5 pipe.The drain electrode d of the grid G of M2 pipe and source S, M3 pipe and the drain electrode d of M5 pipe link together.The drain electrode d of the source S of M3 pipe and M6 pipe links together as not gate V
0Output terminal.
Second kind of not gate is on the basis of the described subtraction circuit of claim 9, with the former V of this circuit
AInput end removes, and the drain electrode d of M6 pipe and substrate b are connected to power supply V
DD, with its V
BInput end changes V into
AInput end has just become not circuit.
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| US11126433B2 (en) | 2015-09-19 | 2021-09-21 | Microsoft Technology Licensing, Llc | Block-based processor core composition register |
| US11531552B2 (en) | 2017-02-06 | 2022-12-20 | Microsoft Technology Licensing, Llc | Executing multiple programs simultaneously on a processor core |
| CN109347475A (en) * | 2018-09-30 | 2019-02-15 | 郑州轻工业学院 | A kind of voting machine circuit realized based on memristor |
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