CN102070120B - Preparation method for high-density interposer for microelectronic system-in-package - Google Patents
Preparation method for high-density interposer for microelectronic system-in-package Download PDFInfo
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Abstract
The invention discloses a preparation method for a high-density interposer for microelectronic system-in-package. The preparation method comprises the following steps of: 1, preparing a drectionally growing carbon nanotube bundle array, wherein the diameter of each carbon nanotube bundle is 0.5 to 30 microns, the gap of the carbon nanotube bundle is 0.8 to 100 microns, and the carbon nanotube bundle is 40 to 500 microns long; 2, depositing metal tungsten on the surface of the drectionally growing carbon nanotube bundle so as to form a conductor array; 3, melting borosilicate glass and compounding the melted borosilicate glass with the conductor array so as to form a compound body; and 4, grinding the upper surface and the lower surface of the formed compound body so as to expose the end of the carbon nanotube bundle deposited with the metal tungsten, and obtaining the high-density interposer for the system-in-package. The material adopted by the preparation method has low thermal expansivity and the process method is low in time consumption, so the prepared high-density interposer has the advantages of high density, high reliability and low cost.
Description
Technical field
The present invention relates to a kind of microelectronic manufacturing technology, relate in particular to a kind of preparation method who is used for the high density patching plate of microelectronic system level encapsulation.
Background technology
In the microelectronics system, live width tens nanometers normally on the chip, and on the pcb board normally tens to a hundreds of micron.Usually utilize various keysets (this keyset is the interposer in the English, comprises substrate) with chip and pcb board interconnection, realize the transition of nanometer to micro-meter scale.Requirement to keyset has a lot, and for example requiring has lower thermal coefficient of expansion, high density, high rigidity and low dielectric constant etc.
The problem of existing organic material keyset is that its thermal coefficient of expansion is higher, and is bigger with the thermal mismatching of chip, and its modulus is lower, makes the angularity of substrate higher, therefore is difficult to realize high density interconnect.
Existing silicon through hole (TSV) technology is the main direction that develops at present; It at first is on silicon, to adopt methods such as dry method (DRIE) or laser processing to make the less through hole of yardstick; And then adopt electric plating method with hole metallization, but efficient is lower, and cost is higher; Adopt at present below the wafer thinning to 50 micron even thinner, greatly reduce cost, but whole process need tens hours, and reliability also is difficult to satisfy the requirement of industrial quarters.
Adopt glass just becoming the direction of concern as keyset.At processing through hole on glass is a difficult problem.Adopt the method for DRIE to utilize gas that glass is carried out etching, etch rate is merely 750nm/min, and the planform and the size limitations of not only being carved are big, can't realize large ratio of height to width, and working (machining) efficiency is low, and cost is high.The method of main at present employing laser processing prepares through hole, but the cost of laser processing is higher, and the hole shape of processing is also irregular; When processing the aperture of 3-10 micron; Its speed is slower, and processing still need adopt electrochemical method to metallize later, when requiring high density, small size pin interconnection; Efficient is lower, and cost is higher.
Therefore, be badly in need of a kind of low cost of development, high efficiency, highdensity keyset at present.
Summary of the invention
The present invention mainly provides a kind of low cost, the high efficiency preparation method who is used for the high density patching plate of microelectronic system level encapsulation.
The present invention adopts following technical scheme:
A kind of preparation method who is used for the high density patching plate of microelectronic system level encapsulation may further comprise the steps:
The first step, the carbon nano-tube bundle array 2 of preparation oriented growth, the diameter of carbon nano-tube bundle is the 0.5-30 micron, and spacing is the 0.8-100 micron, and length is the 40-500 micron;
In second step, form conductor array at above-mentioned oriented growth of carbon nanometer tube bundle surface deposition tungsten 1;
The 3rd step made Pyrex and conductor array under the Pyrex molten condition, form complex,
In the 4th step, carry out grinding and polishing for the upper and lower surfaces of the complex that forms and make the carbon nano-tube bundle end of plated metal tungsten expose, thereby obtain being used for the high density patching plate of system in package.
In the technique scheme; The 3rd step adopted the negative pressure method to make conductor array and glass form complex; Concrete steps are: at first above-mentioned described metal array is transferred in the pre-prepd silicon chamber, and Pyrex and silicon are carried out anode linkage in a vacuum, make the silicon chamber seal; Two again that above-mentioned bonding is good disks are heated to more than the softening temperature of glass under an atmospheric pressure, and melten glass under action of negative pressure, gets into the silicon chamber and said carbon nano-tube bundle array forms complex, cooling, annealing.Through the synthetic described carbon nano-tube bundle array of the method for plasma reinforced chemical vapour deposition.The thickness of carbon nano-tube bundle surface deposition tungsten is the 0.5-2 micron.Method at carbon nano-tube bundle surface deposition tungsten is the mode of electron beam evaporation.Said Pyrex are Pyrex7740 glass, and the heating-up temperature in said the 4th step is 850 ℃-900 ℃.Said Pyrex are BOROFLOAT33 glass.The grinding and polishing method in said the 5th step is the chemical machinery corrosion.
The present invention obtains following effect:
The present invention adopt oriented growth the carbon nano-tube bundle array as template, adopt tungsten as conducting metal with soak into metal, prepared the glass keyset, wherein the complex of carbon nano pipe array and tungsten is as conductor material.Because the present invention adopts the carbon nano-tube bundle array of oriented growth, therefore can prepare highdensity through-hole interconnection line.Existing carbon nano-tube bundle can realize that micron is to sub-micron diameter; Live width be micron to sub-micron, length is sub-micron to several millimeters manufacturing, therefore adopts carbon nano-tube bundle compound of glass and oriented growth to be expected to realize highdensity interconnection; Conductor diameter, live width, length accurate and adjustable; Can realize tens microns to sub-micron diameter, live width be the hundreds of micron to sub-micron, length is sub-micron to the manufacturing of several millimeters scopes.The present invention adopts tungsten metal and Pyrex to have excellent wetability, therefore is easy to compound; In addition, tungsten and carbon nano pipe array caking property are good, can promote the compound degree of glass and tungsten, thereby improve the reliability of complex; Tungsten metal (about 5/1000000ths) and CNT have lower thermal coefficient of expansion, Heat stability is good, and the complex that therefore prepares has higher reliability when bearing higher thermal cycle load; The conductivity of tungsten is better, and carbon nano-tube bundle also has higher conductivity, and the complex of tungsten and carbon nano-tube bundle also has conductivity preferably, and can realize the electrical interconnection function; In addition, the complex of tungsten and carbon nano-tube bundle is easy to and other metal in the end, and for example copper, ashbury metal etc. form good bonding, and the pad tie point of formation has higher reliability, and this is that single employing carbon nanotube interconnect is not available.
2. Pyrex (comprise BOROFLOAT33, Pyrex7740-Corning Incorporated produces) can wetting tungsten surface.It has high transmission rate, higher characteristics such as intensity, high-modulus and low-k, makes keyset have good light, electricity, mechanical performance, and has higher reliability.In addition, because the composite conductor surface roughness lower (a few nanometer to tens nanometer) that carbon nano pipe array and tungsten form, therefore the glass keyset of leading of preparation is particularly useful for frequency applications.Because carbon nano-tube bundle, Pyrex and tungsten all can bear high temperature, so this glass keyset also is suitable for the high temperature application.
3. be that glass melting is cast straight in the metal array among the present invention, preparation speed is fast, and efficient is high, greatly reduces cost; Because oriented growth of carbon nanometer tube array can carry out wafer level manufacturing (adopting brand is the manufacturing of Blackmagic vapor deposition apparatus), the present invention can also prepare the glass keyset of wafer level, and therefore the cost of preparation can access further reduction.
4. the modulus of the modular ratio silicon of the glass among the present invention is high, and need be with the glass substrate attenuate in the course of processing, so the good substrate of ability force rate silicon of the anti-warpage of glass substrate.
5. therefore the permittivity ratio silicon of the glass that uses among the present invention low reduced capacitive coupling and signal cross-talk than silicon substrate.The silicon chamber among the present invention and the anode linkage of glass have very high intensity, the characteristics of good leak tightness, in heating process, be difficult for to take place leak and cause glass with process that metal array combines in produce bubble.At 400 ° of C of temperature, under the bonding conditions of voltage direct current 600V, anode linkage can reach best sealing effectiveness.
6. the annealing process that adopts among the present invention can effectively be eliminated glass and bear the stress that forms in high temperature and the metal array cohesive process, thereby makes its strength and toughness higher.Annealing temperature is that temperature retention time is 30min in 550 ℃～570 ℃ scopes, slow then cool to room temperature.Under this condition, anneal, the stress of effectively decorporating, low excessively annealing temperature then can't effectively be removed the glass internal stress.
7. can adopt concentration among the present invention is the silicon of 25% TMAH solution removal carbon nano-tube, can remove silicon chip effectively like this and etching glass not, selects silicon chip, glass than being 1000:1.
It is high that the present invention has metal throuth hole density, and thermal conductivity is good, and the characteristics that manufacturing cycle is short also can be widely used in the preparation of the glass substrate in the MEMS manufacturing.
Description of drawings
Fig. 1 is the schematic cross-section of carbon nano-tube bundle array.
Fig. 2 is the schematic cross-section after the carbon nano-tube bundle array metallization.
Fig. 3 is the glass substrate sketch map of solid metal through hole.
Fig. 4 is the glass keyset schematic cross-section that exposes solid metal through hole (center is the carbon pipe) end face after the grinding and polishing up and down.
Fig. 5 is the glass substrate schematic top plan view of solid metal through hole.
Embodiment
Embodiment 1
A kind of preparation method who is used for the high density patching plate of microelectronic system level encapsulation may further comprise the steps:
The first step, the carbon nano-tube bundle array 2 of preparation oriented growth, the diameter of carbon nano-tube bundle is the 0.5-30 micron, for example is 0.8 micron, 2 microns, 3 microns, 5 microns; 10 microns, 20 microns, spacing is the 0.8-100 micron, for example is 1 micron, 3 microns, and 5 microns, 8 microns; 10 microns, 20 microns, 30 microns, 50 microns, 80 microns, length is the 40-500 micron; For example can be 45 microns, 60 microns, 100 microns, 200 microns, 300 microns, 400 microns;
In second step, form conductor array at above-mentioned oriented growth of carbon nanometer tube bundle surface deposition tungsten 1; The thickness of tungsten is the 0.1-20 micron, for example can be 0.2 micron, 0.8 micron, and 1 micron, 5 microns, 10 microns, 15 microns.
The 3rd step made Pyrex and conductor array under the Pyrex molten condition, form complex,
In the 4th step, carry out grinding and polishing for the upper and lower surfaces of the complex that forms and make the carbon nano-tube bundle end of plated metal tungsten expose, thereby obtain being used for the high density patching plate of system in package.
In the technique scheme, the 3rd step can adopt positive pressure-driven that glass is infiltrated between the conductor array, also can adopt negative pressure suction melten glass to form the complex of glass and conductor array, again with glass cools, annealed.The present invention can be through the synthetic described carbon nano-tube bundle array of the method for plasma reinforced chemical vapour deposition.Method at carbon nano-tube bundle surface deposition tungsten is the mode of electron beam evaporation.Said Pyrex are Pyrex7740 glass, and corresponding said heat fused temperature is 850 ℃-900 ℃, for example 860 ℃, and 880 ℃.Said Pyrex also can BOROFLOAT33 glass.The grinding and polishing method in said the 5th step is the chemical machinery corrosion.
Embodiment 2
A kind of preparation method who is used for the high density patching plate of microelectronic system level encapsulation may further comprise the steps:
The first step, the carbon nano-tube bundle array of preparation oriented growth, the diameter of carbon nano-tube bundle is 3 microns, and spacing is 5 microns, and length is 200 microns; Growing method is that plasma strengthens CVD method etc.,
Second step is at above-mentioned described carbon nano-tube bundle surface deposition tungsten; Can prepare one deck tungsten in carbon nano tube surface; The thickness of tungsten is 3 microns; The method of preparation can be sputter or methods such as electron beam evaporation or plating, and electron beam evaporation (Ebeam) can make the uniform tungsten of surface coverage thickness of carbon nano pipe array, and has lower surface roughness.
The 3rd step, the carbon nano-tube bundle after the above-mentioned metallization is transferred in the pre-prepd silicon chamber, and Pyrex7740 glass and silicon are carried out anode linkage in a vacuum, make the silicon chamber seal; Vacuum degree is less than 1Pa, 0.1Pa for example, 0.01Pa, anode linkage; Process conditions are: 400 ℃ of temperature, voltage: 600V.
In the 4th step, two disks that above-mentioned bonding is good are being heated under the atmospheric pressure under 850 ℃-900 ℃, and glass gets into the silicon chamber under the action of negative pressure in the chamber, and compound with the carbon nano-tube bundle after the said metallization, cooling, and annealing,
The 5th step; Carry out grinding and polishing for the upper and lower surfaces of the complex that forms and make the carbon nano-tube bundle end of plated metal tungsten expose, thereby obtain being used for the high density patching plate of system in package, after the carbon nano-tube bundle end with plated metal tungsten exposes; Can make the metal pad that is used for pin interconnection on its surface; Because the existence of tungsten, the reliability of the solder joint that tungsten and metal form is higher, thereby has overcome the shortcoming of the reliability of electrical connection difference of existing CNT and metal.
In the technique scheme; Through the synthetic described carbon nano-tube bundle array of the method for plasma reinforced chemical vapour deposition; The thickness of carbon nano-tube bundle surface deposition tungsten is the 0.5-2 micron; Method at carbon nano-tube bundle surface deposition tungsten is the mode of electron beam evaporation, and the grinding and polishing method in said the 5th step is the chemical machinery corrosion.
Embodiment 3
A kind of preparation method who is used for the high density patching plate of microelectronic system level encapsulation, may further comprise the steps: the first step is employed in carbon nano-tube bundle array on the silicon wafer; Second step is to above-mentioned described carbon nano-tube bundle array metallization; In the 3rd step, above-mentioned described metal array is put into pre-prepd silicon chamber, and BOROFLOAT33 glass and silicon chamber are carried out anode linkage; In the 4th step, two disks that above-mentioned bonding is good to the BOROFLOAT33 glass heats, make its fusion under an atmospheric pressure, itself and above-mentioned metal array are well combined, and cooling is with above-mentioned disk stress relieving by annealing; The 5th step, remove the silicon of carbon nano-tube, finally obtain being used for the preparation method of the high density patching plate of microelectronic system level encapsulation.
In the technique scheme; The method for preparing described carbon nano-tube bundle array does; Silicon wafer to cleaning carries out surface oxidation; Adopt the certain thickness aluminium oxide layers of method deposit of atomic layer deposition then and adopt the method for electron beam evaporation to make one deck iron catalyst layer, and it is carried out photoetching, at last through CVD method synthesize nano carbon tube bank array.Preparing a collection of diameter is 5 microns, 20 microns, 50 microns, 100 microns; Spacing does; At first with the CNT oxidation, then CNT is put into activating solution after, the surface forms one deck colloid protective layer as thin as a wafer; It under the protective layer catalytic activity nucleus; Protective layer is removed, expose catalytic active layer, at last CNT is put into chemical plating fluid and carry out the corresponding metal plating.The 4th step, the slice, thin piece that above-mentioned bonding is good was heated to about 1270 ° of C under the atmospheric pressure, for example was chosen for 1200 ° of C, 1270 ° of C, 1240 ° of C, was incubated 3-8 minute; For example can be chosen for: 4 min, 5 min, 6 min; Glass and metal array are combined, cooling, stress relieving by annealing at normal temperatures again; The annealing temperature retention time is 30min, and is slowly air-cooled to normal temperature then.The method of the silicon of described removal carbon nano-tube of the 5th step is with in the immersion 25%TMAH solution after annealed, with the temperature water-bath heating greater than 90 ° of C, until removing silicon layer fully.In the described anodic bonding process of the 3rd step, silicon chip and glass substrate carry out necessary cleaning according to the technological requirement of anode linkage.
Embodiment 4
A kind of preparation method who is used for the high density patching plate of microelectronic system level encapsulation may further comprise the steps:
The first step is employed in carbon nano-tube bundle array on the silicon wafer; The titanium of spin coating one deck 20 nanometers is as resilient coating on silicon substrate; And then prepare layer of aluminum on the titanium, pass through method electrode one deck nickel Catalytic Layer of electron beam evaporation again, photoetching; At last above-mentioned substrate is put into a chamber; And above-mentioned substrate was processed 1 minute under 850 degree conditions with 40SCCM hydrogen and 10SCCM nitrogen gas plasma, being equipped with a collection of diameter is 5 microns, 20 microns, 50 microns, 100 microns, and spacing is 15 microns, 50 microns, 100 microns a carbon nano-tube bundle array.
Second step is to above-mentioned described carbon nano-tube bundle array metallization; At first with the CNT oxidation, then CNT is put into activating solution after, the surface forms one deck colloid protective layer as thin as a wafer; It under the protective layer catalytic activity nucleus; Protective layer is removed, expose catalytic active layer, at last CNT is put into chemical plating fluid and carry out the corresponding metal plating.
In the 3rd step, above-mentioned described metal array is put into pre-prepd silicon chamber, and BOROFLOAT33 glass and silicon chamber are carried out anode linkage; Process conditions are: 400 ℃ of temperature, voltage: 600V.
In the 4th step, the slice, thin piece that above-mentioned bonding is good is being heated to about 1270 ° of C under the atmospheric pressure, for example is chosen for 1200 ° of C, 1270 ° of C, 1240 ° of C; Be incubated 3-8 minute, for example can be chosen for: 4 min, 5 min; 6 min combine glass and metal array, cooling; Stress relieving by annealing at normal temperatures again, the annealing temperature retention time is 30min, and is slowly air-cooled to normal temperature then.
The 5th step, remove the silicon of carbon nano-tube, finally obtain being used for the preparation method of the high density patching plate of microelectronic system level encapsulation.In the immersion 25%TMAH solution after annealed, with temperature water-bath heating, until removing silicon layer fully greater than 90 ° of C.
In the technique scheme; The method for preparing described carbon nano-tube bundle array does, the silicon wafer of cleaning carried out surface oxidation, then certain thickness aluminium oxide layers of deposit and iron catalyst layer; And it is carried out photoetching, at last through the synthetic carbon nano-tube bundle array as shown in the figure of CVD method.The method of deposit aluminium oxide layers is an atomic layer deposition, and the method for described making iron catalyst layer is an electron beam evaporation, and the process conditions of described CVD method synthesizing carbon nanotubes are: 750 ° of C of temperature, air-flow ratio utilization steam is auxiliary.Second step is described to be at first with the CNT oxidation, then with the CNT activation, to use the method plating of chemical plating at last to the metallized method of carbon nanotubes.The 4th step, described glass heats temperature was 1270 ℃, and annealing temperature is 560 ℃, and the annealing temperature retention time is 30min, and is slowly air-cooled to normal temperature then.The method of the silicon of described removal carbon nano-tube of the 5th step is with in the immersion 25%TMAH solution after annealed, with the temperature water-bath heating greater than 90 ° of C, until removing silicon layer fully.In the described anodic bonding process of the 3rd step, silicon chip and glass substrate carry out necessary cleaning according to the technological requirement of anode linkage.
Claims (2)
1. a preparation method who is used for the high density patching plate of microelectronic system level encapsulation is characterized in that, may further comprise the steps:
The first step, the carbon nano-tube bundle array (2) of preparation oriented growth, the diameter of carbon nano-tube bundle is the 0.5-30 micron, and spacing is the 0.8-100 micron, and length is the 40-500 micron;
In second step, form conductor array at above-mentioned oriented growth of carbon nanometer tube bundle surface deposition tungsten (1);
The 3rd step made Pyrex (3) and conductor array under the Pyrex molten condition, form complex,
In the 4th step, carry out grinding and polishing for the upper and lower surfaces of the complex that forms and make the carbon nano-tube bundle end of plated metal tungsten expose, thereby obtain being used for the high density patching plate of system in package.
2. the preparation method who is used for the high density patching plate of microelectronic system level encapsulation according to claim 1; It is characterized in that the 3rd step employing negative pressure method makes conductor array and glass form complex; Concrete steps are: at first above-mentioned described conductor array is transferred in the pre-prepd silicon chamber; And Pyrex and silicon are carried out anode linkage in a vacuum, make the sealing of silicon chamber; Two again that above-mentioned bonding is good disks are heated to more than the softening temperature of glass under an atmospheric pressure, and melten glass under action of negative pressure, gets into the silicon chamber and said carbon nano-tube bundle array forms complex, cooling, annealing.
3. the preparation method who is used for the high density patching plate of microelectronic system level encapsulation according to claim 1 is characterized in that, through the synthetic described carbon nano-tube bundle array of the method for plasma reinforced chemical vapour deposition.
4. the preparation method who is used for the high density patching plate of microelectronic system level encapsulation according to claim 1 and 2 is characterized in that the thickness of carbon nano-tube bundle surface deposition tungsten is the 0.5-2 micron.
5. the preparation method who is used for the high density patching plate of microelectronic system level encapsulation according to claim 1 and 2 is characterized in that, is the mode of electron beam evaporation in the method for carbon nano-tube bundle surface deposition tungsten.
6. the preparation method who is used for the high density patching plate of microelectronic system level encapsulation according to claim 2 is characterized in that said Pyrex are Pyrex7740 glass, and the heating-up temperature in said the 3rd step is 850 ℃-900 ℃.
7. the preparation method who is used for the high density patching plate of microelectronic system level encapsulation according to claim 1 is characterized in that said Pyrex are BOROFLOAT33 glass.
8. the preparation method who is used for the high density patching plate of microelectronic system level encapsulation according to claim 1 is characterized in that, the grinding and polishing method in said the 4th step is the chemical machinery corrosion.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9889635B2 (en) | 2012-12-13 | 2018-02-13 | Corning Incorporated | Facilitated processing for controlling bonding between sheet and carrier |
| US10014177B2 (en) | 2012-12-13 | 2018-07-03 | Corning Incorporated | Methods for processing electronic devices |
| US10086584B2 (en) | 2012-12-13 | 2018-10-02 | Corning Incorporated | Glass articles and methods for controlled bonding of glass sheets with carriers |
| US10046542B2 (en) | 2014-01-27 | 2018-08-14 | Corning Incorporated | Articles and methods for controlled bonding of thin sheets with carriers |
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