CN105399050B - Wafer-level preparation method of glass substrate integrating chip heat radiation structure and passive devices - Google Patents
Wafer-level preparation method of glass substrate integrating chip heat radiation structure and passive devices Download PDFInfo
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- CN105399050B CN105399050B CN201510957861.3A CN201510957861A CN105399050B CN 105399050 B CN105399050 B CN 105399050B CN 201510957861 A CN201510957861 A CN 201510957861A CN 105399050 B CN105399050 B CN 105399050B
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- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00206—Processes for functionalising a surface, e.g. provide the surface with specific mechanical, chemical or biological properties
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Abstract
The invention discloses a wafer-level preparation method of a glass substrate integrating a chip heat radiation structure and passive devices. The wafer-level preparation method comprises the following steps of dry-etching a silicon wafer to form a silicon mold wafer which internally comprises a groove array of each passive device; electroplating to embed metallic copper in each groove array at the interior of the silicon mold wafer so as to form each passive device; dry-etching the silicon mold wafer after being subjected to the electroplating process so as to form the chip heat radiation structure; performing anodic bonding for a glass wafer and the chip heat radiation structure in a vacuum; heating the bonded wafer to enable glass to flow backwards and fill with gaps among the passive devices; annealing and cooling to form a backflow wafer; completely grinding and polishing an all-glass substrate on the upper surface of the backflow wafer and an all-silicon-wafer substrate on the lower surface of the backflow wafer; and depositing a metal adhesive layer and electroplating a metal conductive layer to form the glass substrate which integrates a heat radiation function and the passive devices and is used as a three-dimensional glass adapter plate or a three-dimensional passive device. According to the wafer-level preparation method, as the way of firstly electroplating and then reflowing is adopted, the process difficulty is reduced, the prepared passive devices are excellent in performance, and the chip heat radiation structure is integrated.
Description
Technical field
The present invention relates to the substrate keyset technology of preparing in film sealed technology field, more particularly, to a kind of
There is heat sinking function and the switching template glass basal plate structure containing passive device and preparation method thereof.
Background technology
The manufacturing process of traditional passive device uses surface processing technique, utilizes surface processing technique to prepare such as in silicon face
The passive devices such as inductance, the performance of usual passive device with highly closely related, height increases and can reduce Kelvin effect, improves device
The performance of part.But surface processing technique limits the height of device, therefore improve the height of device further to improve device
Performance is difficult to realize simply by surface processing technique.It is to improve performance on this basis, technique need to greatly improve and technique
Complexity greatly increases although the performance of device can improve, but so brings the increase of time and cost.This technique simultaneously
The passive device of preparation belongs to planar device, has the shortcomings that longitudinal extension is shorter, D.C. resistance is larger, electric pathway is less,
Generally three-dimensional interconnection need to be realized by the way of stacking.Prepare passive device using this technique and integrated system has technique again
The shortcomings of limited by polygamy, high cost, device performance.
The three dimension system packing forms of higher form adopt baried type substrate to realize, and substrate form is typically silicon substrate.
Silicon is semi-conducting material, has conductive characteristic, inevitably electric leakage, parasitic capacitance, unnecessary in preparation process
The effect such as signal coupling, the performance to device and the integrated of system have a negative impact.It is swollen that glass has the heat mated with silicon
Swollen coefficient, can be preferably integrated with silicon base chip, and glass is good insulant simultaneously, will not produce in device fabrication process
The effects such as raw electric leakage, parasitic capacitance, the coupling of unnecessary signal, the shortcoming overcoming silica-base material.With respect to silicon materials, glass
Thermal conductivity lower, there is in terms of preparing hot radical device bigger advantage, the transparency of glass and optical property also give interconnection
Monitoring reliability and optics provide advantage.
Content of the invention
For above-mentioned the deficiencies in the prior art, it is an object of the invention to provide a kind of integrated chip radiator structure and passive device
The wafer level preparation method of the glass substrate of part, on the basis of not reducing device performance, substantially reduces first glass and flows back
The difficulty of electroplating technology preparation.
For achieving the above object, the present invention employs the following technical solutions:
A kind of wafer level preparation method of the glass substrate of integrated chip radiator structure and passive device, walks including following
Rapid:
Step one, dry etching silicon wafer forms silicon mould disk, makes to comprise on silicon mould disk to include embedded type passive
The groove array of device architecture mould；
Metal is filled up the groove array in step one by electroplating technology and forms passive device structure by step 2；
Step 3, the silicon mould disk after dry etch step two forms groove, discharges passive device structure, is formed simultaneously
Chip cooling structure；
Step 4, the silicon mould with passive device structure and chip cooling structure that glass wafer and step 3 are obtained
Disk in a vacuum anode linkage so that passive device structure and groove are sealed in bonding wafers；
Step 5, the bonding wafers that step 4 is obtained are placed and are heated in atmosphere, and heating-up temperature is higher than the softening of glass
Point temperature, and be incubated, until melten glass flows back in the presence of pressure difference inside and outside groove, the full groove of filling, annealing, are cooled to
Room temperature, forms composite construction layer, the bottom of top all-glass construction layer, middle embedment passive device structure and chip cooling structure
The backflow disk of the three-decker of total silicon substrat structure layer；
Step 6, former of the backflow that step 5 is obtained is ground and polishes, and removes top all-glass construction layer and bottom
Portion's total silicon substrat structure layer, leaves the composite construction layer of middle embedment passive device structure and chip cooling structure, makes backflow glass
Glass substrate exposes, and obtains glass substrate；
Step 7, the glass substrate upper and lower surface deposited metal adhesion layer obtaining in step 6, plated metal conductive layer, shape
Become to include the glass substrate of passive device structure, metal conducting layer and chip cooling structure, the interconnection as passive device or three
Dimension integrated glass keyset.
Further, in step one, described silicon wafer thickness is not less than 300um；Described dry etching is deep reactive ion
Etching, etching depth is less than more than silicon wafer thickness 100um.
Further, in step 2, the shape of described passive device structure includes cylinder, Ring-cylindrical, coaxial cylindrical, or
Kinky line column, square spiral post, hexagon borded pile, octagon borded pile, round screw thread post, or double cuboid, coaxially bicyclic
Shape post；In step 3, the shape of described chip cooling structure includes cylinder, cuboid.
Further, the process conditions of electro-coppering described in step 2 are: in hydrosulphate plating copper electrolyte, cuso4·
5h2O content 85g/l, h2so4Content 200g/l, cl-Content 79mg/l, electric current density is 30ma/cm2.
Further, in step 3, described dry etching is deep reaction ion etching, and etching depth is not more than passive device
The height of structure.
Further, in step 4, described glass wafer is Pyrex, and thickness is not less than 300um；Described vacuum anode
Bonding technology condition is: 400 DEG C of temperature, voltage 800v, and vacuum is less than 10-3pa.
Further, in step 5, the heating process conditions of bonding wafers are: heating-up temperature is 900 DEG C -1100 DEG C, plus
Hot temperature retention time is not less than 2h, and annealing process condition is: 510 DEG C -560 DEG C of annealing temperature, temperature retention time 30min, is often cooled to
Warm condition is natural cooling.
Further, in step 6, the step of described grinding and polishing is: adopts automatic grinding and polishing device, to backflow circle
Piece is implemented to grind reduction process, removes top all-glass construction layer and bottom total silicon substrat structure layer, stays middle embedment passive
Device architecture and the composite construction layer of chip cooling structure.
Further, in step 8, described deposited metal adhesion layer be ti or cr, described plated metal conductive layer be au or
cu.
The invention has the beneficial effects as follows:
The present invention has the three-dimensional passive device of embedded type of heat sinking function using glass reflux technique preparation after a kind of first plating
The glass substrate of part.The glass substrate of this technique preparation is integrated with embedded type passive device, is improve passive using three-dimensional advantage
Device is energy, saves space surface simultaneously；And devise radiator structure, the radiating to chip improves a channel.Should
Technique, using glass reflow method after first electroplating, on the basis of not reducing device performance, substantially reduces first glass and flows back
The difficulty of electroplating technology preparation, and devise chip cooling passage, be conducive to chip cooling.
Brief description
Fig. 1 is to be etched with the groove array sectional view including embedment passive device structure mould on silicon mould disk；
Fig. 2 is the disk sectional view being electroplate with passive device structure on silicon mould disk；
Fig. 3 is release passive device structure and the disk sectional view being etched with radiator structure on silicon wafer；
Fig. 4 is the bonding wafers sectional view after silicon wafer and glass wafer anode linkage；
Fig. 5 is the backflow disk sectional view after being heated to reflux and annealing；
Fig. 6 be grinding and polishing after glass substrate sectional view；
Fig. 7 be surface processing technique after glass substrate sectional view；
Fig. 8 is the perspective view that glass substrate imbeds passive device and chip cooling structure；
In figure, 1- silicon mould disk, 2- groove array, 3- passive device structure mould, 4- passive device structure, 5- chip
Radiator structure, 6- groove, 7- glass wafer, 8- all-glass construction layer, 9- composite construction layer, 10- total silicon substrat structure layer, 11-
Reflowed glass substrate, 12- metal adhesion layers, 13- metal conducting layer, 14- glass substrate, 15- annular capacitor, 16- square spiral
Inductance, 17- fold-line-shaped spiral inductance.
Specific embodiment
With reference to embodiment and accompanying drawing, the present invention is done and further explain.The following example is merely to illustrate this
Bright, but be not used to limit the practical range of the present invention.
Embodiment 1
A kind of wafer level preparation method of the glass substrate of integrated chip radiator structure and passive device, walks including following
Rapid:
Step one, dry etching silicon wafer form silicon mould disk 1, make to comprise on silicon mould disk 1 to include embedment passive
The groove array 2 of device architecture mould 3, as shown in figure 1, the silicon that do not etch between groove array 2 is used for follow-up dry etching.Its
In, silicon wafer thickness is 525um；Dry etching is deep reaction ion etching, and etching depth is 300um.The shape of groove array 2
Including kinky line column, square spiral post, hexagon borded pile, octagon borded pile, round screw thread post or double cuboid, coaxial
Crossed Circle post.
Step 2, with silicon substrate as Seed Layer, in the full groove array 2 of electro-coppering filling, electro-coppering is formed imbeds passive device
Part structure 4, as shown in Figure 2.Wherein, the process conditions of electro-coppering are: in hydrosulphate plating copper electrolyte, cuso4·5h2O contains
Amount 85g/l, h2so4Content 200g/l, cl-Content 79mg/l, electric current density is 30ma/cm2.
Step 3, dry etching silicon mould disk 1 form groove 6, make the embedment passive device including on silicon mould disk 1
Structure 4 exposes, and forms chip cooling structure 5, as shown in Figure 3 simultaneously.Wherein, dry etching is deep reaction ion etching, etching
Depth is 250um.The shape of chip cooling structure 5 includes cylinder, cuboid.
Step 4, the silicon mould disk 1 obtaining glass wafer 7 and step 3 are less than 10 in vacuum-3Pa, temperature 400
DEG C, carry out anode linkage under the conditions of voltage 800v so that embedment passive device structure 4 and chip cooling structure 5 are sealed in bonding
In disk, as shown in Figure 4.Described glass wafer 7 is pyrex7740 glass, thickness 500um.
Step 5, the bonding wafers obtaining step 4 are placed and are heated in atmosphere, and heating-up temperature is 950 DEG C, is incubated 6h,
The full groove 6 of filling until melten glass flows back in the presence of pressure difference inside and outside groove 6, and the 30min that anneals at 560 DEG C, from
So it is cooled to room temperature, form top all-glass construction layer 8, the glass substrate of middle embedment passive device structure 4 and chip cooling
The composite construction layer 9 of structure 5, the backflow disk of the triplen of bottom total silicon substrat structure layer 10, as shown in Figure 5.
Step 6, adopt automatic grinding and polishing device, top all-glass construction layer 8 is implemented grind reduction process to base first
This removal top all-glass construction layer 8, recycles cerium oxide polishing slurry polished glass surface, to embedment passive device structure 4 He
The upper surface of chip cooling structure 5 exposed in smooth reflowed glass substrate 11 upper surface, as shown in Figure 6.Then complete to bottom
Silicon substrate structure layer 10 is implemented to grind reduction process to basic removal bottom total silicon substrat structure layer 10, makes middle composite construction layer
9 lower surface exposes, and recycles cerium oxide polishing slurry polished glass surface, to embedment passive device structure 4 and chip cooling
The lower surface of structure 5 exposed in smooth reflowed glass substrate 11 lower surface, as shown in Figure 6.
The composite construction 9 that step 7, Surface Machining step 6 obtain, deposition ti or cr obtains metal adhesion layers 12, plating
Au obtains metal conducting layer 13, as shown in fig. 7, being used as passive device element, or three-dimensionally integrated glass keyset.Described broken line
Shape post, square spiral post, hexagon borded pile, octagon borded pile, round screw thread post are used for preparing the folding of embedded in glass substrate
Linear spiral inductance, square spiral inductance, hexagon spiral inductance, octagon spiral inductance, round screw thread inductance；Described double long
Cube is used for the plate type capacitance that preparation is fully embedded glass substrate, and coaxial Crossed Circle post is used for the annular that preparation is fully embedded glass substrate
Electric capacity.Chip cooling structure 5, annular capacitor 15, square spiral inductance 16, fold-line-shaped spiral inductance 17 are as shown in Figure 8.
The above be only the preferred embodiment of the present invention it should be pointed out that: for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (9)
1. the glass substrate of a kind of integrated chip radiator structure and passive device wafer level preparation method it is characterised in that: bag
Include following steps:
Step one, dry etching silicon wafer forms silicon mould disk (1), makes to comprise to include embedded type no on silicon mould disk (1)
The groove array (2) in source device architecture mould (3)；
Metal is filled up the groove array (2) in step one by electroplating technology and forms passive device structure (4) by step 2；
Step 3, the silicon mould disk (1) after dry etch step two forms groove (6), discharges passive device structure (4), with
When formed chip cooling structure (5)；
Step 4, by glass wafer (7) and step 3 obtain with passive device structure (4) and chip cooling structure (5)
Silicon mould disk (1) in a vacuum anode linkage so that passive device structure (4) and groove (6) are sealed in bonding wafers；
Step 5, the bonding wafers that step 4 is obtained are placed and are heated in atmosphere, and heating-up temperature is higher than the softening point temperature of glass
Degree, and be incubated, until melten glass flows back in the presence of pressure difference inside and outside groove, the full groove (6) of filling, annealing, are often cooled to
Temperature, forms the composite construction on top all-glass construction layer (8), middle embedment passive device structure (4) and chip cooling structure (5)
Layer (9), the backflow disk of the three-decker of bottom total silicon substrat structure layer (10)；
Step 6, former of the backflow that step 5 is obtained is ground and polishes, and removes top all-glass construction layer (8) and bottom
Total silicon substrat structure layer (10), leaves the composite construction layer of middle embedment passive device structure (4) and chip cooling structure (5)
(9) so that reflowed glass substrate (11) is exposed, obtain glass substrate；
Step 7, glass substrate upper and lower surface deposited metal adhesion layer (12) obtaining in step 6, plated metal conductive layer
(13), the glass substrate (14) including passive device structure (4), chip cooling structure (5), the interconnection as passive device are formed
Or three-dimensionally integrated glass keyset.
2. the wafer level preparation side of the glass substrate of integrated chip radiator structure according to claim 1 and passive device
Method it is characterised in that: in step one, described silicon wafer thickness be not less than 300um；Described dry etching is carved for deep reactive ion
Erosion, etching depth is less than more than silicon wafer thickness 100um.
3. the wafer level preparation side of the glass substrate of integrated chip radiator structure according to claim 1 and passive device
Method it is characterised in that: in step 2, the shape of described passive device structure (4) includes cylinder, Ring-cylindrical, coaxial cylindrical, or
Kinky line column, square spiral post, hexagon borded pile, octagon borded pile, round screw thread post, or double cuboid；In step 3,
The shape of described chip cooling structure (5) includes cylinder, cuboid.
4. the wafer level preparation side of the glass substrate of integrated chip radiator structure according to claim 1 and passive device
Method it is characterised in that: in electroplating technology described in step 2 adopt metal be copper, the process conditions of electro-coppering are: acid sulphuric acid
In salt plating copper electrolyte, cuso4·5h2O content 85g/l, h2so4Content 200g/l, cl-Content 79mg/l, electric current density is
30ma/cm2.
5. the wafer level preparation side of the glass substrate of integrated chip radiator structure according to claim 1 and passive device
Method it is characterised in that: in step 3, described dry etching be deep reaction ion etching, etching depth be not more than passive device knot
The height of structure (4).
6. the wafer level preparation side of the glass substrate of integrated chip radiator structure according to claim 1 and passive device
Method it is characterised in that: in step 4, described glass wafer (7) be Pyrex, thickness be not less than 300um；Described in a vacuum
The process conditions of anode linkage are: 400 DEG C of temperature, voltage 800v, and vacuum is less than 10-3pa.
7. the wafer level preparation side of the glass substrate of integrated chip radiator structure according to claim 1 and passive device
Method it is characterised in that: in step 5, the heating process conditions of bonding wafers are: heating-up temperature be 900 DEG C -1100 DEG C, heating protect
The warm time is not less than 2h, and annealing process condition is: 510 DEG C -560 DEG C of annealing temperature, temperature retention time 30min, is cooled to room temperature bar
Part is natural cooling.
8. the wafer level preparation side of the glass substrate of integrated chip radiator structure according to claim 1 and passive device
Method it is characterised in that: in step 6, described grind and the step of polishing is: adopt automatic grinding and polishing device, real to backflow disk
Apply grinding reduction process, remove top all-glass construction layer (8) and bottom total silicon substrat structure layer (10), leave middle embedment no
The composite construction layer (9) of source device architecture (4) and chip cooling structure (5).
9. the wafer level preparation side of the glass substrate of integrated chip radiator structure according to claim 1 and passive device
Method it is characterised in that: in step 7, described deposited metal adhesion layer (12) be ti or cr, described plated metal conductive layer (13)
For au or cu.
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| CN106564856A (en) * | 2016-10-27 | 2017-04-19 | 东南大学 | Composite substrate and preparation method thereof |
| CN115206676B (en) * | 2022-07-20 | 2023-09-08 | 广州天极电子科技股份有限公司 | Glass chip capacitor and preparation method thereof |
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| JP2011204950A (en) * | 2010-03-26 | 2011-10-13 | Panasonic Electric Works Co Ltd | Metal embedded glass substrate and method of manufacturing the same, and mems device |
| CN102070120A (en) * | 2010-12-31 | 2011-05-25 | 东南大学 | Preparation method for high-density interposer for microelectronic system-in-package |
| CN201994289U (en) * | 2011-01-31 | 2011-09-28 | 江阴长电先进封装有限公司 | Wafer level adapter plate structure |
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