CN101807913B - Enabling signal generating method, device and equipment of low-speed clock - Google Patents
Enabling signal generating method, device and equipment of low-speed clock Download PDFInfo
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- CN101807913B CN101807913B CN2010101333564A CN201010133356A CN101807913B CN 101807913 B CN101807913 B CN 101807913B CN 2010101333564 A CN2010101333564 A CN 2010101333564A CN 201010133356 A CN201010133356 A CN 201010133356A CN 101807913 B CN101807913 B CN 101807913B
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Abstract
The embodiment of the invention discloses enabling signal generating method, device and equipment of a low speed clock, relating to the technical field of mobile communication and simulating the low speed clock by using a high speed clock fixed ratio. The equipment comprises an equivalent circuit which realizes the modular operation effect through combination of a first selector, a second selector, a register, a comparator, an adder and a subtractor. The method comprises the following steps of comparing a remainder M obtained by dividing n times of C by P in the period of the nth high-speed clock; if the remainder M is less than C, outputting effective enabling signals of the low speed clock; and if the remainder M is bigger than or equal to C, outputting invalid enabling signals of the low speed clock, wherein the integer ratio of a high speed clock and the low speed clock is P/C, P is an integer value of the high speed clock, C is an integer value of the low speed clock, and n=1 to P. The embodiment of the invention is applied to the communication technology.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of low-speed clock enable signal production method, device and equipment.
Background technology
Along with the expansion of chip-scale and the increase of function, compatible simultaneously interface also is multiple and increases, at present; Most of chips all are multi-clock zones; The chip of multi-clock zone exists asynchronous and power problems, and addressing the above problem needs to increase chip capacity, has directly caused the increase of chip cost.
The multi-clock zone chip is for homology clock clock frequency scheme for a long time; Mainly by internal or external phase-locked loop (Phase Locked Loop; Be called for short PLL) realize, use the clock branch of a system clock generation different clocks frequency, but this scheme receives the restriction of PLL configuration coefficients; Use PLL can increase the cost of chip or chip-scale solution simultaneously, and the expansion of divide ratio need increase to cost with cost.
To above-mentioned defective, prior art provides a kind of frequency of using maximum clock frequency as system clock, and the clock using system clock+clock of all the other frequencies enables the implementation that breach (gap) substitutes clock.This scheme can reach only needs a crystal oscillator that the effect of clock is provided, and different clocks enables gap and represents different clock-domains, has eliminated the problem of asynchronous process.
Particularly, when utilizing high-frequency clock simulation low-speed clock, use ripple counter to realize the low-speed clock enable signal.For example, can use the counter of one 1 bit of 100MHz clock design,, represent 1/2 divide ratio, reach the branch yupin effect of 50MHz clock in 0/1 upset with 100MHz clock simulation 50MHz clock.For divide ratio complicated situation comparatively, can use A* (B*CLK+1*gap)+(C*CLK+1*gap), promptly use high-frequency clock to produce two speed patterns and simulate the method for low-speed clock, realize the low-speed clock enable signal.Wherein, " " B*CLK+1*gap " representes fast pattern, and physical meaning is B effective clock cycle+1 an invalid clock cycle (breach); " C*CLK+1*gap " representes slow pattern, and physical meaning is C effective clock cycle+1 an invalid clock cycle (breach); Total formula A* (B*CLK+1*gap)+(C*CLK+1*gap) then represented in the individual clock cycle of A* (B+1)+(C+1); A fast pattern and 1 slow pattern are simulated the low-speed clock enable signal, and wherein the frequency proportions of low-speed clock and high-frequency clock is (A*B+C)/(A* (B+1)+(C+1)).
Because there is the clock index request in telecommunication transmission system; The low-speed clock that uses high-frequency clock to simulate need reach best effect of uniform; Exchanging best clock jitter performance for, so the clock index of chip system is relevant with the uniformity of clock enable signal gap.When stating scheme in realization; The inventor finds that there is following problem at least in the technical scheme of prior art: for frequency division system N/M complicated situation comparatively; Especially when the least common multiple of N and M was big, the result who uses A* (B*CLK+1*gap)+(C*CLK+1*gap) formula to draw was unsatisfactory, and the frequency deviation of generation is bigger; The clock enable signal is inhomogeneous, thereby the clock that causes simulating has deviation.
Summary of the invention
The embodiment of the invention provides a kind of low-speed clock enable signal production method, device and equipment, can realize using the low-speed clock of high-frequency clock simulation fixed proportion.
For solving the problems of the technologies described above, the embodiment of the invention adopts following technical scheme:
A kind of low-speed clock enable signal produces equipment, comprising: first selector, second selector, register, comparator, adder and subtracter, wherein; The integer ratio of high-frequency clock and low-speed clock is: P/C, P are the high-frequency clock integer value, and C is the low-speed clock integer value; Then
The first input end of said first selector is used to receive low-speed clock integer value C, and its second input is coupled to the output of said adder, and its control input end is used to receive reset signal, and its output is coupled to the input of said register;
The input of said register is coupled to the output of said first selector; Its drive end is used to receive high-frequency clock, and its output is coupled respectively to the first input end of the input of said comparator, said second selector and the first input end of said subtracter;
The first input end of said comparator is coupled to the output of said register, and its second input is used to receive high-frequency clock integer value P, and its output is exported low-speed clock enable signal and is coupled to the control input end of said second selector;
The first input end of said second selector is coupled to the output of said register; Its control input end is coupled to the output of said comparator; Its second input is coupled to the output of said subtracter, and its output is coupled to second input of said adder;
The first input end of said subtracter is coupled to the output of said register, and its second input is used to receive high-frequency clock integer value P, and its output is coupled to second input of said second selector;
The first input end of said adder is used to receive low-speed clock integer value C, and its second input is coupled to the output of said second selector, and its output is coupled to second input of said first selector.
A kind of low-speed clock enable signal production method comprises:
In the cycle of n high-frequency clock, the n of C is doubly compared with said C divided by the resulting remainder M of P;
If said remainder M less than C, then exports effective low-speed clock enable signal; If said remainder M more than or equal to C, then exports invalid low-speed clock enable signal;
Wherein, the integer ratio of said high-frequency clock and said low-speed clock is: P/C, P are the high-frequency clock integer value, and C is the low-speed clock integer value, n=1 ..., P.
A kind of low-speed clock enable signal generation device comprises:
Comparing unit was used in the cycle of n high-frequency clock, and the n of C is doubly compared with said C divided by the resulting remainder M of P; Wherein, the integer ratio of said high-frequency clock and said low-speed clock is: P/C, P are the high-frequency clock integer value, and C is the low-speed clock integer value, n=1 ..., P;
Output unit is used for if said remainder M less than C, then exports effective low-speed clock enable signal; If said remainder M more than or equal to C, then exports invalid low-speed clock enable signal.
Low-speed clock enable signal production method, device and equipment that the embodiment of the invention provides; Utilized the Sigma-Delta algorithm; According to ratio of integers and high-frequency clock integer value and the low-speed clock integer value of the high-frequency clock that obtains with the low-speed clock of being simulated; At high-frequency clock in the integer-valued cycle, the integer-valued n of low-speed clock is doubly compared with the low-speed clock integer value divided by the resulting remainder M of high-frequency clock integer value, when remainder M exports effective low-speed clock enable signal during less than the low-speed clock integer value; When remainder M more than or equal to the low-speed clock integer value the invalid low-speed clock enable signal of time output; Thereby utilize Sigma-Delta algorithm equivalent electric circuit to export uniform low-speed clock enable signal, thereby realized complicated clock division, high-frequency clock is simulated the low-speed clock output of fixed proportion.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; The accompanying drawing of required use is done to introduce simply in will describing embodiment below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is an embodiment of the invention low-speed clock enable signal production method flow chart;
Fig. 2 is the structural representation of embodiment of the invention low-speed clock enable signal generation device;
Fig. 3 is the structural representation that embodiment of the invention low-speed clock enable signal produces equipment;
Fig. 4 is the electrical block diagram of embodiment of the invention low-speed clock enable signal and system clock binding control.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
The embodiment of the invention provides a kind of low-speed clock enable signal production method, device and equipment, realizes using the low-speed clock of high-frequency clock simulation fixed proportion.
Embodiment one
The embodiment of the invention provides a kind of low-speed clock enable signal production method, and as shown in Figure 1, this method comprises:
Wherein, the integer ratio of said high-frequency clock and said low-speed clock is: P/C, P are the high-frequency clock integer value, and C is the low-speed clock integer value, n=1 ..., P.
The method that present embodiment provided adopts the Sigma-Delta algorithm; Produce the low-speed clock enable signal; Thereby high-frequency clock is modeled as low-speed clock output; Below be the system clock that the 10GE client traffic is adopted with the high-frequency clock, the low-speed clock of simulation is that example describes for the ODU2E business clock.Wherein, 10GE and ODU2E are the type of service that synchronous ethernet and OTN transmit net, and service rate is respectively 10.3125Gbit/s and 10.3558Gbit/s, are mainly used in transmitting loading low speed transmissions business and data packet traffic in the network.
When the 10GE client traffic was applied to transmit network, data flow was transmitted through synchronous backboard after using hard speed-raising mode to be packaged into ODU (Optical Channel Data Unit, Optical Channel Data Unit-k) structure.Use the backboard clock as system clock, clock frequency is 174.96MHz, and simulated clock simulation clock is the ODU2E business clock.The clock frequency value that draws the ODU2E business clock according to the corresponding relation (239/237) of 10GE and ODU2E frame structure is that 162.49258306962025316455696202532MHz (only shows numerical digit behind the decimal point here; This is worth non-exact value); Therefore the using system clock can't be accomplished absolute 0ppm (Parts Permillion, represent 1,000,000/) frequency deviation, needs the value of the low-speed clock of intercepting simulation; Within the tolerable frequency deviation region of the system that is; As+/-1ppm, with ODU2E business clock value 162.4925MHz, can convert both desirable 60865: 65535 of integer ratio; The clock frequency deviation of simulation is 1.03592ppm, is the acceptable frequency deviation region of system.
If P=65535, C=60865, when n=1, M=(nC) MODP=60865=C=60865 then exports invalid clock enable signal; When n=2, M=(nC) MODP=56195＜C=60865 then still exports effective clock enable signal; When n=3, M=(nC) MODP=51525＜C=60865 then still exports effective clock enable signal; When n=4, M=(nC) MODP=46855＜C=60865 then still exports effective clock enable signal; ... when n=N, M=(nC) MODP >=C=60865 then exports invalid clock enable signal; ..., wherein, the effective clock enable signal of output is 60865, and invalid clock enable signal is 65535-60865=4670.
The embodiment of the invention also provides a kind of low-speed clock enable signal generation device, and as shown in Figure 2, this device comprises: comparing unit 11 and output unit 12
Comparing unit 11 was used in the cycle of n high-frequency clock, and the n of C is doubly compared with said C divided by the resulting remainder M of P; Wherein, the integer ratio of said high-frequency clock and said low-speed clock is: P/C, P are the high-frequency clock integer value, and C is the low-speed clock integer value, n=1 ..., P; Output unit 12 is used for if said remainder M less than C, then exports effective low-speed clock enable signal; If said remainder M more than or equal to C, then exports invalid low-speed clock enable signal.That is, if M=(nC) MODP＜C then exports effective low-speed clock enable signal; If M=(nC) MODP >=C then exports invalid low-speed clock enable signal, MOD is a modulo operation.
Low-speed clock enable signal production method and device that the embodiment of the invention provides; Utilized the Sigma-Delta algorithm; According to ratio of integers and high-frequency clock integer value and the low-speed clock integer value of the high-frequency clock that obtains with the low-speed clock of being simulated; At high-frequency clock in the integer-valued cycle, the integer-valued n of low-speed clock is doubly compared with the low-speed clock integer value divided by the resulting remainder M of high-frequency clock integer value, when remainder M exports effective low-speed clock enable signal during less than the low-speed clock integer value; When remainder M more than or equal to the low-speed clock integer value the invalid low-speed clock enable signal of time output; Thereby utilize Sigma-Delta algorithm equivalent electric circuit to export uniform low-speed clock enable signal, realized complicated clock division.
Embodiment two
The embodiment one described Sigma-Delta algorithm that utilizes is realized low-speed clock enable signal production method; Because its equivalent electric circuit of getting remainder simulates the comparison difficulty, so the low-speed clock enable signal generation equipment that present embodiment proposes based on said method is a kind of equivalent electric circuit that utilizes adder and subtracter combination realization modulo operation effect, and is as shown in Figure 3; This equipment comprises: the logic combination circuit of being made up of first selector 1, second selector 2, register 3, comparator 4, adder 5 and subtracter 6; Can be substituted by immobilising device, wherein, the integer ratio of high-frequency clock and low-speed clock is: P/C; P is the high-frequency clock integer value; C is the low-speed clock integer value, then
The first input end of said first selector 1 connects the output of output low-speed clock integer value C; Be used to receive low-speed clock integer value C; Its second input is coupled to the output of said adder 5; Its control input end is used to receive reset signal RST, and its output is coupled to the input of said register 3;
The first input end of said register 3 is coupled to the output of said first selector 1; Its second input (being drive end) connects high-frequency clock; Its output is coupled respectively to the input of said comparator 4, the first input end of the first input end of said second selector 2 and said subtracter 6;
The first input end of said comparator 4 is coupled to the output of said register 3; Its second input connects the output of output high-frequency clock integer value P; Be used to receive high-frequency clock integer value P, its output is exported low-speed clock enable signal and is coupled to the control input end of said second selector 2;
The first input end of said second selector 2 is coupled to the output of said register 3; Its control input end is coupled to the output of said comparator 4; Its second input is coupled to the output of said subtracter 6, and its output is coupled to second input of said adder 5;
The first input end of said subtracter 6 is coupled to the output of said register 3; Its second input connects the output of said output high-frequency clock integer value P; Be used to receive high-frequency clock integer value P, its output is coupled to second input of said second selector 2;
The first input end of said adder 5 connects the output of said output low-speed clock integer value C; Be used to receive low-speed clock integer value C; Its second input is coupled to the output of said second selector 2, and its output is coupled to second input of said first selector 1.
Wherein, register can be rising edge trigger or trailing edge trigger, is driven by high-frequency clock, overturns by high-frequency clock.Perhaps, employing is two along trigger, can use rising edge triggering or trailing edge to trigger the roll over condition as this trigger according to the real system application choice.Further, this high-frequency clock can adopt system clock.
Still be the system clock that the 10GE client traffic is adopted with the high-frequency clock, the simulation low-speed clock is that example describes for the ODU2E business clock.
The clock frequency of 10GE client traffic is 174.96MHz, and simulated clock simulation clock is the ODU2E business clock.The clock frequency value that draws the ODU2E business clock according to the corresponding relation (239/237) of 10GE and ODU2E frame structure is 162.49258306962025316455696202532MHz; With ODU2E business clock value 162.4925MHz; Can convert to such an extent that both integer ratio is: 60865: 65535; The clock frequency deviation of simulation is 1.03592ppm, is the acceptable frequency deviation region of system.
With numerical value 60865 and 65535 respectively as the input value C and the P of Sigma-Delta equivalent electric circuit; Using system clock (clk_sys=174.96MHz) is as the drive clock of circuit, and then the low-speed clock enable signal gap and system clock (clk_sys=174.96MHz) equivalence of output are simulated clock simulation clock (ODU2E), and promptly low-speed clock enable signal gap is as the indication of high-frequency clock; With high-frequency clock; Be that the system clock binding is used, gap is effective for the low-speed clock enable signal, then the output system clock; Gap is invalid for the low-speed clock enable signal, then the shielding harness clock.
If W
N=(Y
N-1+ C)＜and P, then export invalid low-speed clock enable signal; If W
N=(Y
N-1+ C)>=and P, then export effective low-speed clock enable signal.(wherein, if W
N-1＜P, then Y
N-1=P; If W
N-1>=P, then Y
N-1=W
N-1-P; W is the value of output in the register 3, and Y is the value of exporting in the second selector.)
Then in the cycle of P high-frequency clock, as shown in Figure 3, the value W that comparator 4 obtains in the register 3 compares with P, if W＜P then exports invalid low-speed clock enable signal; If W >=P then exports effective low-speed clock enable signal, promptly essence is for producing low-speed clock enable signal gap, and indication is in the individual clock cycle of 65535 (P), and the individual effective low-speed clock enable signal of 60865 (C) is indicated with gap=0; The individual invalid low-speed clock enable signal of 4670 (65535-60865) is indicated with gap=1.Wherein, effectively low-speed clock enable signal (C) is evenly to distribute in whole clock cycle (P), and implementation procedure is following:
Drive clock is system clock (clk_sys=174.96MHz), and register 3 can be triggered by rising edge clock, and promptly each clock cycle of register value upgrades once;
In P clock cycle; At first carry out initialization, reset signal RST is effective, and first selector 1 is reset to the C value with register 3 behind circuit start; 4 pairs of register values of comparator this moment (C) compare with the P value; Because C＜P, then the low-speed clock enable signal gap of output this moment is 1, and indicating first clock cycle position is invalid low-speed clock enable signal; Simultaneously, this low-speed clock enable signal gap=1 control second selector 2 mask register values (C) are as the input of adder 5, and then the adder output valve is 2C;
First system clock clk_sys rising edge place after cancelling in resetting; 3 pairs of input values of register latch; Because this moment, reset signal was cancelled, first selector 1 is selected the input of the output valve of adder 5 as register 3, and then register 3 storing values refresh and are 2C; 4 pairs of register values of comparator (2C) compare with the P value, because 2C＞P, then the low-speed clock enable signal gap of output this moment is 0, and indication should the clock cycle position be effective low-speed clock enable signal; Simultaneously, this clock enable signal gap=0 control second selector 2 is selected the input of the output valve (2C-P) of subtracter 6 as adder 6, and then adder 6 output valves are (3C-P);
In second system clock clk_sys rising edge place, register 3 latchs input value once more, and follow-up work is with above-mentioned consistent;
Circuit is in P clock cycle, and C clock cycle output signal g ap=0 representes that the low-speed clock enable signal of this clock cycle is effective; (P-C) individual clock cycle output signal g ap=1 representes that the low-speed clock enable signal of this clock cycle is invalid.
After the clock cycle, register value copies as C again through computing at circuit working P, and then first execution cycle finishes, and gets into next execution cycle.The output of the upset of circuit and low-speed clock enable signal gap is in full accord.
As shown in Figure 3; The reset signal RST of first selector 1 is used to control said first selector 1; When reset signal is effective; The low-speed clock integer value C that said first selector 1 selects output to receive, when reset signal is invalid, the value that said first selector 1 selects output to obtain from said adder 5.It will be understood by those skilled in the art that reset mode do not have only this a kind of form shown in Figure 3, also can be when needs reset, by second input input reset signal of software or hardware controls first selector 1.
Further, equipment shown in Figure 3 also can comprise: the low-speed clock generation unit is used to utilize said low-speed clock enable signal and said high-frequency clock to generate said low-speed clock.
The low-speed clock enable signal gap of equipment that present embodiment provides output and system clock clk_sys binding use, thereby the upset of control circuit, promptly when low-speed clock enable signal gap is effective, the circuit operate as normal; When low-speed clock enable signal gap was invalid, circuit kept.As shown in Figure 4; Low-speed clock enable signal gap and system clock clk_sys binding are used; Thereby the upset of control d type flip flop, and, further; Can the control signal of low-speed clock enable signal gap as the gated clock clock-gate of system clock can be reached the effect of the dynamic power consumption that reduces circuit.The circuit of gated clock clock-gate is generally provided by rear end producer; Realize the low-power consumption processing of circuit; The operation principle of Fig. 4 is that clock-gate exports the upset of clock driving d type flip flop when gap=0; Shielding clock when gap=1, then this moment, d type flip flop kept initial value not overturn, thereby reached the effect of low-power consumption.
In the technical scheme of present embodiment; Utilized the equivalent electric circuit of Sigma-Delta algorithm; According to ratio of integers and high-frequency clock integer value and the low-speed clock integer value of the high-frequency clock that obtains with the low-speed clock of being simulated, in the integer-valued cycle, the value W that first comparator 1 obtains in the register 3 compares with P at high-frequency clock; If W＜P then exports effective low-speed clock enable signal; If W >=P; Then export invalid low-speed clock enable signal, thereby utilize Sigma-Delta algorithm equivalent electric circuit that high-frequency clock is modeled as low-speed clock output, realized complicated clock division; Export uniform low-speed clock enable signal; And reach further evenly, avoided unnecessary frequent saltus step, obtain best clock jitter and drift performance.
Through the description of above execution mode, the those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential common hardware, can certainly pass through hardware, but the former is better execution mode under a lot of situation.Based on such understanding; The part that technical scheme of the present invention contributes to prior art in essence in other words can be come out with the embodied of software product, and this computer software product is stored in the storage medium that can read, like the floppy disk of computer; Hard disk or CD etc.; Comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; Can expect easily changing or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of said claim.
Claims (10)
1. a low-speed clock enable signal produces equipment, it is characterized in that, comprising: first selector, second selector, register, comparator, adder and subtracter; Wherein, The integer ratio of high-frequency clock and low-speed clock is: P/C, P are the high-frequency clock integer value, and C is the low-speed clock integer value; Then
The first input end of said first selector is used to receive low-speed clock integer value C; Its second input is coupled to the output of said adder, and its control input end is used to receive reset signal, and its output is coupled to the input of said register; When said reset signal is effective; The low-speed clock integer value C that said first selector selects output to receive, when said reset signal is invalid, the value that said first selector selects output to obtain from said adder;
The input of said register is coupled to the output of said first selector; Its drive end is used to receive high-frequency clock, and its output is coupled respectively to the first input end of the input of said comparator, said second selector and the first input end of said subtracter;
The first input end of said comparator is coupled to the output of said register, and its second input is used to receive high-frequency clock integer value P, and its output is exported low-speed clock enable signal gap and is coupled to the control input end of said second selector; If W＜P; Then export invalid low-speed clock enable signal gap=1, if W >=P then exports effective low-speed clock enable signal gap=0; Wherein, W is the value of exporting in the said register;
The first input end of said second selector is coupled to the output of said register; Its control input end is coupled to the output of said comparator; Its second input is coupled to the output of said subtracter; Its output is coupled to second input of said adder; Invalid low-speed clock enable signal gap=1 controls said second selector and selects the input of the value of said register as said adder, and effectively low-speed clock enable signal gap=0 controls said second selector and selects the input of the output valve of subtracter as adder;
The first input end of said subtracter is coupled to the output of said register, and its second input is used to receive high-frequency clock integer value P, and its output is coupled to second input of said second selector;
The first input end of said adder is used to receive low-speed clock integer value C, and its second input is coupled to the output of said second selector, and its output is coupled to second input of said first selector.
2. equipment according to claim 1 is characterized in that, said register is rising edge trigger or trailing edge trigger.
3. equipment according to claim 1; It is characterized in that; The low-speed clock enable signal of said comparator output is used to control said second selector, when said low-speed clock enable signal is effective clock enable signal, and the value that said second selector selects output to obtain from said register; When said low-speed clock enable signal is invalid clock enable signal, the value that said second selector selects output to obtain from said subtracter.
4. equipment according to claim 1; It is characterized in that; Said reset signal is used to control said first selector, when reset signal is effective, and the low-speed clock integer value C that said first selector selects output to receive; When reset signal is invalid, the value that said first selector selects output to obtain from said adder.
5. according to each described equipment in the claim 1 to 4, it is characterized in that, also comprise:
The low-speed clock generation unit is used to utilize said low-speed clock enable signal and said high-frequency clock to generate said low-speed clock.
6. a low-speed clock enable signal production method is characterized in that, comprising:
In the cycle of n high-frequency clock, the n of C is doubly compared with said C divided by the resulting remainder M of P;
If said remainder M less than C, then exports effective low-speed clock enable signal; If said remainder M more than or equal to C, then exports invalid low-speed clock enable signal;
Wherein, the integer ratio of said high-frequency clock and said low-speed clock is: P/C, P are the high-frequency clock integer value, and C is the low-speed clock integer value, n=1 ..., P.
7. method according to claim 6 is characterized in that, said high-frequency clock is a system clock.
8. according to claim 6 or 7 described methods, it is characterized in that, also comprise: utilize the low-speed clock enable signal and the said high-frequency clock of output to generate said low-speed clock.
9. a low-speed clock enable signal generation device is characterized in that, comprising:
Comparing unit was used in the cycle of n high-frequency clock, and the n of C is doubly compared with said C divided by the resulting remainder M of P; Wherein, the integer ratio of said high-frequency clock and said low-speed clock is: P/C, P are the high-frequency clock integer value, and C is the low-speed clock integer value, n=1 ..., P;
Output unit is used for if said remainder M less than C, then exports effective low-speed clock enable signal; If said remainder M more than or equal to C, then exports invalid low-speed clock enable signal.
10. device according to claim 9 is characterized in that, said high-frequency clock is a system clock.
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| KR101682272B1 (en) * | 2014-01-27 | 2016-12-05 | 엘에스산전 주식회사 | Method for generating clock for system operating in rising edge |
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| JP2003256068A (en) * | 2002-03-04 | 2003-09-10 | Seiko Epson Corp | Clock control system |
| JP4613080B2 (en) * | 2005-03-10 | 2011-01-12 | 池上通信機株式会社 | Clock reproduction information generation circuit and clock reproduction circuit |
| CN1835389B (en) * | 2005-03-14 | 2010-07-14 | 华为技术有限公司 | Method able to eliminate frequency error of digital controlled oscillator and phase accumulator |
| US7428652B2 (en) * | 2005-05-10 | 2008-09-23 | Intel Corporation | Programmable phase generator for cross-clock communication where the clock frequency ratio is a rational number |
| GB0714848D0 (en) * | 2007-07-31 | 2007-09-12 | Zarlink Semiconductor Inc | Flexible waveform generation with extended range capability |
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2010
- 2010-03-26 CN CN2010101333564A patent/CN101807913B/en active Active
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| CN101807913A (en) | 2010-08-18 |
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