CN101217277B - A non-integer frequency difference eliminator and phase-lock loop that can product non-integer real-time clock signal - Google Patents
A non-integer frequency difference eliminator and phase-lock loop that can product non-integer real-time clock signal Download PDFInfo
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- CN101217277B CN101217277B CN2008100010436A CN200810001043A CN101217277B CN 101217277 B CN101217277 B CN 101217277B CN 2008100010436 A CN2008100010436 A CN 2008100010436A CN 200810001043 A CN200810001043 A CN 200810001043A CN 101217277 B CN101217277 B CN 101217277B
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Abstract
The invention relates to a non-integer frequency difference eliminator and a phase-lock control loop that can produce non-integer clock; wherein, the frequency difference eliminator comprises a frequency difference eliminating circuit, a delay circuit and an option circuit. The frequency difference eliminating circuit is used for leading a clock signal to be divided by an integer preset value so as to obtain a frequency difference eliminating impulse. The delay circuit is used for delaying a first preset multiple and a second preset multiple respectively of the circle of the frequency difference eliminating impulse so as to produce a first delay impulse and a second delay impulse. The option circuit chooses one of the first delay impulse and the second delay impulse according to the frequency difference eliminating multiple so as to be used for being taken as the output impulse of frequency difference eliminator; wherein, the frequency difference eliminating multiple is between the first preset multiple and the second preset multiple.
Description
Technical field
The invention relates to a kind of technology of phase-locked loop, and particularly relevant for a kind of non-integer frequency eliminator and the phase-locked loop that can produce the non-integer clock signal.
Background technology
Phase-locked loop (Phase Lock Loop, PLL) effect is to use the extremely low oscillation source of frequency variation amount as reference, by the feedback effect of loop circuit control system, drive the action of the element of variable frequency, make it reach synchronous state with oscillation source fast and sustainedly and stably.
Fig. 1 is shown the system architecture diagram of known phase-locked loop.Please refer to Fig. 1, this phase-locked loop is made up of five sub-Circuits System, is respectively: phase frequency detector PFD, charge pump CP, loop filter LF, voltage controlled oscillator VCO and frequency eliminator FD.The difference of the feedback signal DS of phase frequency detector PFD after in order to detecting reference signal REF and frequency elimination, and the comparative result of above-mentioned both REF and DS turned to two digital signals draws signal DH and pulldown signal DL to export on being respectively.Charge pump CP purpose is for being converted to this two digital signal one control voltage CV output.The HFS that loop filter LF then can control this voltage filters.Voltage controlled oscillator VCO is promptly according to the size of this control voltage, and a vibration clock signal VO vibrates.Frequency eliminator FD act as the frequency that downgrades this vibration clock signal VO, produces feedback signal DS and is fed back to phase frequency detector PFD.
The vibration clock signal VO that export known phase-locked loop can present same-phase with reference signal REF basically, but frequency differs a prearranged multiple, and this prearranged multiple is that the frequency elimination multiple by frequency eliminator FD decides.Because some application need makes reference signal REF and the frequency of vibration clock signal VO have non-integral multiple relation.Therefore there is the people to propose in order to produce the phase-locked loop of non-integral number frequency multiplication clock signal.Figure 2 shows that known circuit block diagram in order to the phase-locked loop that produces the non-integral number frequency multiplication clock pulse.Please refer to Fig. 2, it is identical with above-mentioned Fig. 1 that this circuit constitutes basically, it is the feedback signal DS that can produce frequency elimination N or N+1 that its difference is in the frequency eliminator FD of this phase-locked loop, and this frequency eliminator FD is controlled by counting circuit CU1, CU2 respectively, and counting circuit CU1 and CU2 have threshold value A and threshold value B respectively, and according to cycle of feedback signal DS to be used as the benchmark operation clock pulse of its counting.
Frequency eliminator FD for the operation of this frequency eliminator of simple declaration FD, does following hypothesis earlier: if may operate in 4 patterns of removing or 5 patterns of removing (be above-mentioned N=4, and N+1=5); And two threshold values of above-mentioned A and B are respectively 3 and 5.So when frequency eliminator FD starts, counting circuit CU1, CU2 can count downwards since 3 and 5 respectively, and counting circuit CU1 meeting this moment output mode signal Mode is 1 state, so that frequency eliminator FD operates in the pattern except that N+1, and when counting circuit CU1 count down to 0 downwards, counting circuit CU1 just can make the state of its mode signal Mode that exports transfer 0 to by 1, so that frequency eliminator FD operates in the pattern except that N, and stops counting.
And then, when counting circuit CU2 continues to count down to 0 downwards, counting circuit CU2 can make the state of the mode signal Mode that counting circuit CU1 exported transfer 1 to by 0, so that frequency eliminator FD operates in the pattern except that N+1, and counting circuit CU1, CU2 can restart downward counting more simultaneously at this moment, to change the state of the mode signal Mode that frequency eliminator FD received again and again, so making frequency eliminator FD will have time of 3/5 is to operate in the pattern except that N+1, and time of 2/5 is arranged is to operate in the pattern except that N.Therefore, the frequency of the feedback signal DS that exported of the disclosed frequency eliminator FD of Fig. 2 can be equivalent to vibrate the frequency of clock signal VO divided by the numerical value of 4+ (3/5).
According to as can be known above-mentioned, though the known frequency that can produce with reference signal REF in order to the phase-locked loop that produces the non-integral number frequency multiplication clock pulse differs N+A/B vibration clock signal VO doubly.Yet the multiple of the frequency of the vibration clock signal VO that this kind phase-locked loop is exported has been limited between N and the N+1.That is to say that the frequency elimination pattern of the phase-locked loop under this type of framework only is to remove N or the two frequency elimination patterns of N+1, and can't be transformed into many frequency eliminations pattern under same framework arbitrarily.
Summary of the invention
Purpose of the present invention is providing a kind of non-integer frequency eliminator exactly, can be in order to a clock signal is obtained the clock signal of non-integer frequency divided by a non-integer.
Another object of the present invention provides a kind of phase-locked loop, can be in order to produce non-integral multiple clock signal.
Based on above-mentioned purpose, the present invention proposes a kind of non-integer frequency eliminator, and this frequency eliminator comprises frequency eliminating circuit, delay circuit and selects circuit.Frequency eliminating circuit in order to the clock signal that will be received divided by an integer preset value after, to obtain a frequency elimination pulse.Delay circuit is in order to receiving above-mentioned frequency elimination pulse and above-mentioned clock signal, and the frequency elimination pulse postponed respectively after first and second preset multiple in cycle of clock signal to produce first and second delay pulse respectively.After selecting circuit to receive first delay pulse and second delay pulse, first delay pulse and second delay pulse are selected an output with the output pulse as the non-integer frequency eliminator according to a frequency elimination multiple.Wherein, above-mentioned frequency elimination multiple is between first preset multiple and second preset multiple, and when the output pulse enable, the startup frequency eliminating circuit is with the pulse of output frequency elimination.
The present invention proposes a kind of phase-locked loop, and it produces the non-integer clock signal by utilizing a non-integer frequency eliminator.This phase-locked loop comprises phase frequency detector, charge pump, voltage controlled oscillator, frequency eliminating circuit, delay circuit, and selects circuit.The phase frequency detector receives output pulse and reference signal, and draws signal and a pulldown signal by relatively exporting after pulse and the reference signal in one of the output.Voltage was controlled in one of output after charge pump received and to draw signal and pulldown signal on above-mentioned.After voltage controlled oscillator receives above-mentioned control voltage, decide the frequency of its clock signal of exporting again according to control voltage.
Frequency eliminating circuit in order to the clock signal that will be received divided by an integer preset value after, to obtain a frequency elimination pulse.Delay circuit is in order to receiving above-mentioned frequency elimination pulse signal and above-mentioned clock signal, and the frequency elimination pulse postponed respectively after first and second preset multiple in cycle of clock signal to produce first and second delay pulse respectively.After selecting circuit to receive first delay pulse and second delay pulse, first delay pulse and second delay pulse are selected an output with as exporting pulse according to a frequency elimination multiple.Wherein, above-mentioned frequency elimination multiple is between first preset multiple and second preset multiple, and when the output pulse enable, the startup frequency eliminating circuit is with the pulse of output frequency elimination, and frequency eliminating circuit, delay circuit and selection circuit constitute the non-integer frequency eliminator.
The present invention proposes a kind of frequency eliminator that produces the non-integer frequency.This non-integer frequency eliminator produces a frequency elimination pulse by the frequency eliminating circuit of integer, and it is identical to produce at least two frequencies by delay circuit, but the delay pulse that phase retardation is different, last one of them is used as the output pulse of non-integer frequency eliminator with output by selecting circuit to select above-mentioned at least two delay pulses according to the frequency elimination multiple of desire frequency elimination again.
Also also because of so, non-integer frequency eliminator of the present invention can produce the clock signal of any different divisors in theory, and uses phase-locked loop of the present invention and can produce the clock signal that differs any different multiplying with reference signal.In addition, frequency eliminator of the present invention only need be selected the frequency elimination multiplying power that circuit received by changing, just can adjust the frequency of output clock pulse arbitrarily, and the present invention is by suitable design, but the adjusting range of the clock signal frequency that export the phase-locked loop is come more widely more than known phase-locked loop, and can not be subject to the integer frequency elimination multiple of known applied frequency eliminator.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the system architecture diagram of known phase-locked loop.
Fig. 2 is known circuit block diagram in order to the phase-locked loop that produces the non-integral number frequency multiplication clock pulse.
Fig. 3 is the circuit block diagram of the phase-locked loop 30 of one embodiment of the invention.
Clock signal VCK, the output pulse VFB that non-integer frequency eliminator 34 is exported that Fig. 4 is exported for the voltage controlled oscillator 33 of one embodiment of the invention, and the clock pulse sequential chart of the frequency elimination pulse VP that exported of frequency eliminating circuit 341.
Fig. 5 is applied to the present invention's a kind of circuit diagram of selecting circuit 343 embodiment illustrated in fig. 3.
Fig. 6 is the circuit diagram of the phase-locked loop 60 of another preferred embodiment of the present invention.
Fig. 7 is the present invention's delay circuit 642 internal circuit diagrams embodiment illustrated in fig. 6.
Fig. 8 is the present invention's selection circuit 643 internal circuit diagrams embodiment illustrated in fig. 6.
Embodiment
Figure 3 shows that the circuit block diagram of the phase-locked loop 30 of one embodiment of the invention.Please refer to Fig. 3, this phase-locked loop 30 comprises phase frequency detector 31, charge pump 32, voltage controlled oscillator 33, and non-integer frequency eliminator 34.This non-integer frequency eliminator 34 comprises frequency eliminating circuit 341, delay circuit 342, and selects circuit 343.The relation that couples between all members in the phase-locked loop 30 of this embodiment as shown in Figure 3.In addition, in Fig. 3, also marked with lower label, it is respectively: the clock signal VCK that the reference signal REF that phase frequency detector 31 is received, voltage controlled oscillator 33 are exported, the frequency elimination pulse VP that frequency eliminating circuit 341 is exported, the first delay pulse VD1 and the second delay pulse VD2 that delay circuit 342 is exported, and non-integer frequency eliminator 34 feeds back to the output pulse VFB of phase frequency detector 31.
For being had, field of the present invention knows that usually the knowledgeable can be well understood to the spirit that institute of the present invention desire is set forth, before the operation logic of the phase-locked loop 30 that the foregoing description is described, earlier above-mentioned several members are made following hypothesis: at first, suppose that the frequency of the reference signal REF that clock signal VCK that voltage controlled oscillator 33 is exported and phase frequency detector 31 are received differs 12.25 times.If in the time of will designing clock signal VCK and reference signal REF and differ the above-mentioned multiplying power that sets with phase-locked loop 30, do following mathematical analysis earlier at this:
F
VCK/ 12.25=1/ (T
VCK* 12.25) (mathematical expression 1.1)
Wherein, F
VCKThe frequency of expression clock signal VCK; T
VCKThe cycle of expression clock signal VCK.Next, more above-mentioned mathematical expression 1.1 is done following the decomposition:
F
VCK/12.25＝1/[T
VCK*(12-8)+T
VCK*8.25]
=1/ (T
VCK* 4+T
VCK* 8.25) (mathematical expression 1.2)
According to mathematical expression 1.2, it mainly is that originally frequency elimination multiple 12.25 is divided into an integer preset value is that 4 numerical value and frequency elimination multiple are 8.25 numerical value.Can therefore the integer preset value of the divisor of the frequency eliminating circuit 341 of the phase-locked loop 30 of embodiment just be set at 4, and why above-mentioned mathematical expression 1.2 selects (12-8) and 8.25? the row argumentation more in the following embodiments of this reason.
Based on above-mentioned, frequency eliminating circuit 341 is to receive the clock signal VCK that voltage controlled oscillator 33 is exported, and this clock pulse signal VCK is obtained frequency elimination pulse VP divided by integer preset value (being 4).Next, delay circuit 342 postpones first time of delay and second time of delay with this frequency elimination pulse VP again, to produce at least the first delay pulse VD1 and the second delay pulse VD2.Wherein, one of them of first, second above-mentioned time of delay can be greater than the cycle of 8.25 times clock signal VCK, and another time of delay then can be less than the cycle of 8.25 times clock signal VCK.In order to allow this embodiment be easily understood more, below be the cycle of 8 times clock signal VCK the time of delay of the hypothesis first delay pulse VD1, and be the cycle of 9 times clock signal VCK the time of delay of the second delay pulse VD2.
So, select circuit 343 again in order to select the output first delay pulse VD1 or the second delay pulse VD2, and this selects circuit 343 to select mechanism of the first delay pulse VD1 or second delay pulse VD2 output is with 8.25 as benchmark basically, then uses X in the following mathematical expression 1.3 to do with ratio (1-X) again and selects to export:
(1-X) 8.25=X*8+9 (mathematical expression 1.3)
Wherein, the X in the mathematical expression 1.3 is 0.75 numerical value, so in per 4 periods, it is the output second delay pulse VD2 that 1 period is arranged, and other 3 periods are output first delay pulse VD1.
Figure 4 shows that clock signal VCK, the output pulse VFB that non-integer frequency eliminator 34 is exported that the foregoing description voltage controlled oscillator 33 is exported, and the clock pulse sequential chart of the frequency elimination pulse VP that exported of frequency eliminating circuit 341.Please refer to Fig. 4, also marked several labels in this Fig. 4, it is respectively the period T of clock signal VCK
VCK, the first delay pulse VD1, and the second delay pulse VD2.Can find out obviously that at Fig. 4 frequency eliminating circuit 341 is when output pulse VFB enables, just can begin clock signal VCK is done the action of frequency elimination to produce frequency elimination pulse VP.After frequency eliminating circuit 341 produced frequency elimination pulse VP, frequency eliminating circuit 341 was just out of service when exporting pulse VFB next time and enable, and just can begin clock signal VCK is done the action of frequency elimination again.So, that is to say that when output pulse VFB enabled, frequency eliminating circuit 341 just can be exported frequency elimination pulse VP.
The phase-locked loop 30 of present embodiment can by after the operation between its inner each member to produce the output pulse VFB of non-integer multiplying power.And its relevant operation logic operation is as described below: at first, phase frequency detector 31 is relatively exported pulse VFB and reference signal REF and is produced and draw signal DH and pulldown signal DL.Then, charge pump 32 is according to drawing signal DH and pulldown signal DL to produce control voltage CV on above-mentioned.Follow, voltage controlled oscillator 33 produces clock signal VCK according to control voltage CV again.At last, produce output pulse VFB by non-integer frequency eliminator 34 again.
Loop circuit control mode between 30 inner each member of above-mentioned phase-locked loop just can produce with reference signal REF and differ non-integral multiple clock signal VCK.By above-mentioned Fig. 3 and Fig. 4 as can be seen, this phase-locked loop 30 utilizes and known different operational modes, with the output pulse VFB of generation non-integer multiplying power.Certainly, though embodiments of the invention are to be used as one for example with the non-integer multiplying power, according to as can be known above-mentioned, phase-locked loop 30 also can produce the clock signal VCK that differs the integer multiplying power with reference signal REF.
Be the cycle of 8 times clock signal VCK the time of delay of the first delay pulse VD1 that the foregoing description exemplified, be the cycle of 9 times clock signal VCK the time of delay of the second delay pulse VD2, the integer preset value is 4 numerical value, and the frequency elimination multiple only is to know usually that in order to allow field of the present invention have the knowledgeable can understand the example that spirit provided that institute of the present invention desire is set forth for 8.25 numerical value.Certainly, as long as field of the present invention has knows the knowledgeable usually with reference to the foregoing description, and the example of the foregoing description is done some digital modification, just can produce the clock signal VCK of different multiplying powers or the output pulse VFB of different frequency elimination multiplying powers.So the invention is not restricted to the embodiments described.Next, provide a kind of execution mode of selecting circuit 343 to have and know that usually the knowledgeable can implement the present invention for this area.
Figure 5 shows that a kind of circuit diagram of selecting circuit 343 of the foregoing description.Please, select circuit 343 to comprise adder 51, postpone buffer 52 in the lump with reference to figure 3 and Fig. 5, and multiplexer 53.Before the operation logic of those members of explanation, suppose that at first adder 51 is the adder of one 4 bit, and this adder 51 has first receiving unit 511, second receiving unit 512, output 513, and overflow output 514, wherein first receiving unit 511 and second receiving unit 512 are all the input of 4 bits.Postpone buffer 52 and have input IN, output OUT, and clock pulse input CK.The relation that couples between these members of selection circuit 343 inside as shown in Figure 5.
First receiving unit 511 of adder 51 receives a floating-point numerical value F, and wherein this floating-point numerical value F represents the floating number of above-mentioned frequency elimination multiple 8.25 numerical value, is 0.25.For instance, 0001 has represented 0.0625,0010 to represent 0.125,0011 to represent 0.1875... by that analogy, so in this embodiment, floating-point numerical value F will equal 0100.
The major function of adder 51 be with after first receiving unit 511 and 512 additions of second receiving unit to output to its output 513.The major function that postpones buffer 52 is all after dates that the numerical value that the output 513 of adder 51 is exported postponed an output pulse VFB, offers second receiving unit 512 of adder 51 again.Therefore, adder 51 with the circuit function that delay buffer 52 is combined into is exactly: the cycle at each output pulse VFB adds up floating-point numerical value F once.
And as if the numerical value that with floating-point numerical value F is 0100, the cycle of per 4 output pulse VFB just once adder 51 overflows (overflow) can take place, so when overflow of adder 51 every generations, it just can utilize overflow output 514 control multiplexers 53, so that multiplexer 53 is selected the output pulse VFB of the second delay pulse VD2 as non-integer frequency eliminator 34.Therefore, if with for a long time on average, output pulse VFB just can be regarded as clock signal VCK divided by 12.25 times frequency elimination signal.And what deserves to be mentioned is that in fact the combination of disclosed adder 51 and delay buffer 52 among Fig. 5 has constituted the different integration modulation circuit of 1 jump (first order delta-sigma modulator).
In addition, in this first relatively difference of the non-integer frequency eliminator 34 of the frequency eliminator FD of the disclosed Fig. 2 of prior art and the embodiment of the invention.According to the description of the invention described above embodiment, though the non-integer frequency eliminator 34 same adjustable frequencies of the frequency eliminator FD of Fig. 2 and the embodiment of the invention all between N and N+1, the technological means that is adopted is obviously different.In addition, the disclosed Fig. 2 of similar prior art is in order to remove (N, N+K) frequency eliminating circuit, only can provide the frequency elimination coefficient with existing technological means is the decimal frequency eliminator of 16 and 17,32 and 33,64 and 65,128 and 129 or 256 and 257 etc. double modulus, so, then must change the circuit framework of decimal frequency eliminator if will realize the decimal frequency eliminator of multimode number.
On the contrary, the non-integer frequency eliminator 34 of the embodiment of the invention is owing to be directly to utilize different delay pulses to produce different frequency elimination coefficients, so as long as the user preestablishes its desired delay pulse, can produce frequency elimination coefficient arbitrarily, so be not limited to above-mentioned some fixing frequency elimination coefficient.Therefore, the non-integer frequency eliminator 34 of the embodiment of the invention can also can make the decimal frequency eliminator of bimodulus or multimode into according to actual circuit design demand.
Fig. 3 has depicted a possible circuit kenel at phase-locked loop and frequency eliminator, and has improved the design bottleneck that the disclosed frequency eliminator of prior art is brought really.Next, enumerating another embodiment below again has for field of the present invention and knows that usually the knowledgeable realizes the spirit that institute of the present invention desire is set forth with better technological means.
Figure 6 shows that the circuit diagram of the phase-locked loop 60 of another embodiment of the present invention.Please refer to Fig. 6, members all in the phase-locked loop 60 is similar to the above embodiments basically.Yet 60 special places, phase-locked loop are that the delay circuit 642 in the non-integer frequency eliminator 34 has more than the output first delay pulse VD1 and the second delay pulse VD2, but the most delay pulse VD1～VD16 of output.Usually know that in order more clearly to allow field of the present invention have the knowledgeable can understand the benefit that this embodiment brings, below will continue to use all hypothesis of above-mentioned Fig. 3 embodiment, promptly with: the integer preset value of the divisor of (1) frequency eliminating circuit 341 is 4; (2) frequency of the reference signal REF that received of the clock signal VCK that exported of voltage controlled oscillator 33 and phase frequency detector 31 differs 12.25 times, for the basis illustrates present embodiment.
In present embodiment, the 1st～16th delay pulse VD1～VD16 is respectively the cycle that frequency elimination pulse VP is postponed 1～16 times clock signal VCK.Therefore, the selection circuit 643 of present embodiment can pass through at random or the fixing choice mechanism that sorts, and selects one of them output pulse VFB as non-integer frequency eliminator 34 from the 1st～the 16th delay pulse VD1～VD16.And this kind way has a very big benefit to be exactly: under the situation that does not change circuit framework, the user can reach the effect of multimode frequency elimination as long as increase the delay pulse that delay circuit 642 is exported.In addition, because delay circuit 642 can produce delay circuit 342 more delay pulse VD1～VD16 than Fig. 3 embodiment, so that the adjustable range of the frequency of clock signal VCK also can be than embodiment illustrated in fig. 3 or known technology is more extensive.
Figure 7 shows that the internal circuit diagram of the delay circuit 642 of present embodiment.Please in the lump with reference to figure 6 and Fig. 7, as shown in Figure 7, delay circuit 643 inside comprise 16 D type flip-flop DFF1～DFF16, and the relation that couples of these D type flip-flops DFF1～DFF16 as shown in Figure 7.So, the user is as long as input to clock signal VCK the clock pulse receiving terminal clk of each D type flip-flop DFF1～DFF16, after the frequency elimination pulse VP that frequency eliminating circuit 341 is produced inputs to the data input pin D of the 1st D type flip-flop DFF1 again, on the data output end Q of each D type flip-flop DFF1～DFF16, will produce a delay pulse VD1～VD16.And if the user desires to increase the number of the delay pulse that delay circuit 642 exported again, the user is as long as increase the number of delay circuit 642 inner applied D type flip-flops.
Figure 8 shows that selection circuit 643 internal circuit diagrams that the present invention is embodiment illustrated in fig. 6.Please in the lump with reference to figure 6～Fig. 8, select circuit 643 to comprise multiplexer 81 and the different integration modulation circuit 82 of 4 jumps, wherein the different integration modulation circuit 82 of 4 jumps also can be called multistage noise shaped (Multi-stAge noiSesHapping, MASH) circuit.The different integration modulation circuit 82 of 4 jumps comprises 811～814,5 second adders of 4 first adders 822～826, the 3rd adder 821, and 7 delay buffers 841～847.
Therefore, if be that 8.25 numerical value is example with the frequency elimination multiple of the foregoing description equally, and hypothesis adder 811～814 all is 4 bit adder, so floating-point numerical value F equally also is 0100 numerical value as can be known.In addition, the integer numerical value of N of the 3rd acceptance division branch of the 3rd adder 821 reception is 8 numerical value.Therefore, by the operation of difference integration modulation circuit 82, if with for a long time on average, the selection numerical value of N out that the output P of adder 821 is exported is equivalent to 8.25 numerical value.So selecting circuit 643 mainly is can be 8.25 numerical value according to the frequency elimination multiple, select delay pulse VD1～VD16 that delay circuit 642 exported to be used as the output pulse VFB of non-integer frequency eliminator 34 fifty-fifty, make that so the spectrum energy beyond the frequency of clock signal VCK can be lower.
In addition, the reason that why will select (12.25-4)=8.25 under different integration modulation circuit 82 frameworks of this 4 jump is exactly because the selection numerical value of N out that the different integration modulation circuit 82 of 4 jumps is exported is 4 bits, its numerical value is between-7～+ 8, but because can't realize postponing the time of delay (being the delay that the actual hardware circuit can't be realized negative) of-7～+ 8 clock signal VCK on the hardware circuit of reality, Gu Benshishilite is set at numerical value more than or equal to 8 with the integer numerical value of N.Thus, if make integer numerical value of N=8, then the value of the selection numerical value of N out that exported of the different integration modulation circuit 82 of 4 jumps just can be between+1～+ 16, promptly representing postpone on the occasion of 1 clock signal VCK on the occasion of 16 clock signal VCK between time of delay, so on the hardware circuit of reality, can realize postponing+time of delay of 1～+ 16 clock signal VCK.
In sum, the present invention proposes a kind of frequency eliminator that produces the non-integer frequency.This non-integer frequency eliminator produces a frequency elimination pulse by the frequency eliminating circuit of integer, and it is identical to produce at least two frequencies by delay circuit, but the delay pulse that phase retardation is different, last one of them is used as the output pulse of non-integer frequency eliminator with output by selecting circuit to select above-mentioned at least two delay pulses according to the frequency elimination multiple of desire frequency elimination again.Also just because of this, the present invention just has following some advantage at least:
1. non-integer frequency eliminator of the present invention can produce the clock signal of any different divisors.
2. use phase-locked loop of the present invention and can produce the clock signal that differs any different multiplying with reference signal.
3. non-integer frequency eliminator of the present invention only need be selected the frequency elimination multiplying power that circuit received by changing, and just can adjust the frequency of output clock pulse arbitrarily.
4. what the present invention can arrange in pairs or groups the output of different bit numbers arbitrarily divides modulator with difference-product.
In addition, in above-mentioned several embodiment of the present invention, also comprise following some advantage:
1. but the adjusting range of the frequency of the clock signal that export the phase-locked loop of using non-integer frequency eliminator of the present invention is come more widely more than known phase-locked loop, and can not be subject to the integer frequency elimination multiple of known applied frequency eliminator.
2. the frequency spectrum of using the clock signal of the phase-locked loop of non-integer frequency eliminator of the present invention exporting can be near the desirable frequency spectrum of institute's desire design.
Though the present invention discloses as above with preferred embodiment; but it is not in order to limit the present invention; any affiliated technical field has knows the knowledgeable usually; without departing from the spirit and scope of the present invention; should do a little change and retouching, so protection scope of the present invention is as the criterion with claims.
Claims (10)
1. non-integer frequency eliminator comprises:
One frequency eliminating circuit receives a clock pulse signal, in order to this clock signal divided by an integer preset value, obtain a frequency elimination pulse;
One delay circuit, receive this frequency elimination pulse and this clock signal, in order to one first preset multiple with cycle of this this clock signal of frequency elimination pulse daley, and then produce one first delay pulse, and with one second preset multiple in cycle of this this clock signal of frequency elimination pulse daley, and then produce one second delay pulse; And
One selects circuit, receives this first delay pulse and this second delay pulse, and according to a frequency elimination multiple this first delay pulse and this second delay pulse is selected an output with the output pulse as this non-integer frequency eliminator,
Wherein, this frequency elimination multiple and whenever this output during pulse enable, starts this frequency eliminating circuit to export this frequency elimination pulse between this first preset multiple and this second preset multiple.
2. non-integer frequency eliminator as claimed in claim 1, it is characterized in that, this delay circuit also in order to one the 3rd preset multiple in cycle of this this clock signal of frequency elimination pulse daley to produce one the 3rd delay pulse, and should select circuit according to this frequency elimination multiple, and this first delay pulse, this second delay pulse and the 3rd delay pulse were selected an output with this output pulse as this non-integer frequency eliminator.
3. non-integer frequency eliminator as claimed in claim 1 or 2 is characterized in that, wherein this selection circuit comprises:
One multiplexer receives whole delay pulses that this delay circuit produces; And
One difference integration modulation circuit, in order to control this multiplexer go to select whole delay pulses that this delay circuit produces one of them, with this output pulse as this non-integer frequency eliminator.
4. non-integer frequency eliminator as claimed in claim 3 is characterized in that, wherein this difference integration modulation circuit comprises:
One adder has one first receiving unit, one second receiving unit, an output, and an overflow output, and wherein this first receiving unit receives a floating-point numerical value, and this floating-point numerical value is represented the floating number of this frequency elimination multiple; And
One postpones buffer, have an input, an output and a clock pulse input, wherein this input couples this output of this adder, this clock pulse input receives this output pulse, and this output couples this second receiving unit of this adder, all after dates that this delay buffer postpones this output pulse according to this output pulse with the numerical value that this input received are to output to this second receiving unit of this adder
Wherein, this overflow output of this adder is couple to this multiplexer, in order to control this multiplexer with select this first delay pulse and this second delay pulse one of them, and then as this non-integer frequency eliminator this output pulse.
5. non-integer frequency eliminator as claimed in claim 3 is characterized in that, wherein this delay circuit is in order to according to 2
NIndividual preset multiple is done to postpone to produce 2 to this frequency elimination pulse
NIndividual delay pulse, and this difference integration modulation circuit comprises:
N difference integration modulator, N+1 second adder, N-1 the second delay buffer, and one the 3rd adder;
Each aforementioned difference integration modulator comprises:
One first adder has one first receiving unit, one second receiving unit, an output, and an overflow output; And
One first postpones buffer, have an input, an output and a clock pulse input, wherein this input couples this output of this first adder, this clock pulse input receives this output pulse, this output couples this second receiving unit of this first adder, the numerical value that this first delay buffer is imported this input according to this output pulse postpones the cycle of this output pulse, and then outputs to this second receiving unit of this first adder
Wherein, the output of the first adder of i difference integration modulator couples first receiving unit of i+1 the first adder in the difference integration modulator, first receiving unit of the first adder in the 1st difference integration modulator receives a floating-point numerical value, and wherein this floating-point numerical value is represented the floating number of this frequency elimination multiple;
Each aforementioned second adder has one first receiving unit, one second receiving unit, an and output, first receiving unit of i second adder couples the overflow output of i the first adder in the difference integration modulator, second receiving unit of i second adder couples i+1 the output in the second adder, the output of i second adder couples second receiving unit of i-1 second adder, second receiving unit of N+1 second adder couples the overflow output of N the first adder in the difference integration modulator, wherein i second adder be in order to being outputed to its output with its first receiving unit mutually with the numerical value that its second acceptance division branch receives, and i-1 second adder and i+1 second adder subtract each other to output to its output in order to this numerical value with its first receiving unit and the reception of its second acceptance division branch respectively;
Each aforementioned second delay buffer has an input, one output and a clock pulse input, wherein the input of i the second delay buffer couples the output of i second adder, i second output that postpones buffer couples first receiving unit of i-1 second adder, each aforementioned second this clock pulse input that postpones buffer receives this output pulse, N-1 second input that postpones buffer couples the overflow output of N the first adder in the difference integration modulator, and the individual second delay buffer of N-1 postpones this numerical value that its input received this output pulse respectively according to this output pulse all after dates export its output to; And
The 3rd adder has one first receiving unit, one second receiving unit, one the 3rd receiving unit, an and output, wherein this first receiving unit of the 3rd adder couples the overflow output of the 1st first adder, this second receiving unit of the 3rd adder couples the output of the 1st second adder, the 3rd receiving unit of the 3rd adder receives an integer numerical value, this output of the 3rd adder couples this multiplexer, the 3rd adder is in order to its first receiving unit, after the numerical value addition that second receiving unit and the 3rd acceptance division branch receive to export its output to, and this multiplexer selects aforementioned 2 according to the numerical value of the output of the 3rd adder
NOne of them this output pulse of individual delay pulse as this non-integer frequency eliminator,
Wherein, this integer numerical value is represented the integer part of this frequency elimination multiple, and above-mentioned N and i are positive integer;
Wherein, i is that correspondence is selected from N difference integration modulator, a N+1 second adder or N-1 the second delay buffer.
6. phase-locked loop, it produces the non-integer clock signal by utilizing a non-integer frequency eliminator, and this phase-locked loop comprises:
One phase frequency detector receives an output pulse and a reference signal, and draws a signal and a drop-down signal by exporting on one after relatively this output pulse and this reference signal;
One charge pump receives to be somebody's turn to do and draws signal and this pulldown signal, to export a control voltage;
One voltage controlled oscillator receives this control voltage, in order to determine the frequency of the clock pulse signal that it is exported according to this control voltage;
One frequency eliminating circuit receives this clock signal, and in order to this clock signal divided by an integer preset value, obtain a frequency elimination pulse;
One delay circuit, receive this frequency elimination pulse and this clock signal, in order to one first preset multiple in cycle of this this clock signal of frequency elimination pulse daley producing one first delay pulse, and with one second preset multiple in cycle of this this clock signal of frequency elimination pulse daley to produce one second delay pulse; And
One selects circuit, receives this first delay pulse and this second delay pulse, and according to a frequency elimination multiple, and this first delay pulse and this second delay pulse are selected an output with as this output pulse,
Wherein, this frequency elimination multiple is between this first preset multiple and this second preset multiple, and, start this frequency eliminating circuit exporting this frequency elimination pulse, and this frequency eliminating circuit, this delay circuit and this selection circuit constitute this non-integer frequency eliminator when this output during pulse enable.
7. phase-locked loop as claimed in claim 6, it is characterized in that, this delay circuit also in order to one the 3rd preset multiple in cycle of this this clock signal of frequency elimination pulse daley to produce one the 3rd delay pulse, this selects circuit according to this frequency elimination multiple, and then this first delay pulse, this second delay pulse and the 3rd delay pulse selected an output, in order to as this output pulse.
8. as claim 6 or 7 described phase-locked loops, it is characterized in that wherein this selection circuit comprises:
One multiplexer receives whole delay pulses that this delay circuit produces; And
One difference integration modulation circuit, control this multiplexer with whole delay pulses of selecting this delay circuit and producing one of them, in order to as this output pulse.
9. phase-locked loop as claimed in claim 8 is characterized in that, wherein this difference integration modulation circuit comprises:
One adder has one first receiving unit, one second receiving unit, an output, and an overflow output, and wherein this first receiving unit receives a floating-point numerical value, and this floating-point numerical value is represented the floating number of this frequency elimination multiple; And
One postpones buffer, have an input, an output and a clock pulse input, wherein this input couples the output of this adder, this clock pulse input receives this output pulse, and this output couples second receiving unit of this adder, this delay buffer postpones the numerical value that this input received according to this output pulse the cycle of this output pulse, in order to output to second receiving unit of this adder
Wherein, this overflow output of this adder is couple to this multiplexer, and one of them exports pulse as this to select this first delay pulse and second delay pulse in order to control this multiplexer.
10. phase-locked loop as claimed in claim 8 is characterized in that, wherein this delay circuit is in order to according to 2
NIndividual preset multiple is done to postpone to produce 2 to this frequency elimination pulse
NIndividual delay pulse, and this difference integration modulation circuit comprises:
N difference integration modulator, N+1 second adder, N-1 the second delay buffer, and one the 3rd adder;
Each aforementioned difference integration modulator comprises:
One first adder has one first receiving unit, one second receiving unit, an output, and an overflow output; And
One first postpones buffer, have an input, an output and a clock pulse input, wherein this input couples this output of this first adder, this clock pulse input receives this output pulse, and this output couples this second receiving unit of this first adder, this first delay buffer postpones the numerical value that this input is imported according to this output pulse the cycle of this output pulse, in order to output to this second receiving unit of this first adder
Wherein, the output of the first adder in i difference integration modulator couples first receiving unit of i+1 the first adder in the difference integration modulator, first receiving unit of the first adder in the 1st difference integration modulator receives a floating-point numerical value, and wherein this floating-point numerical value is represented the floating number of this frequency elimination multiple;
Each aforementioned second adder has one first receiving unit, one second receiving unit, an and output, first receiving unit of i second adder couples the overflow output of i the first adder in the difference integration modulator, second receiving unit of i second adder couples the output of i+1 second adder, the output of i second adder couples second receiving unit of i-1 second adder, second receiving unit of N+1 second adder couples the overflow output of N the first adder in the difference integration modulator, wherein i second adder be in order to being outputed to its output with its first receiving unit mutually with the numerical value that its second acceptance division branch receives, and i-1 second adder and i+1 second adder subtract each other to output to its output in order to this numerical value with its first receiving unit and the reception of its second acceptance division branch respectively;
Each aforementioned second delay buffer has an input, one output and a clock pulse input, wherein the input of i the second delay buffer couples the output of i second adder, i second output that postpones buffer couples first receiving unit of i-1 second adder, each aforementioned second clock pulse input that postpones buffer receives this output pulse, N-1 second input that postpones buffer couples the overflow output of N the first adder in the difference integration modulator, and the individual second delay buffer of N-1 postpones the numerical value that its input received this output pulse respectively according to this output pulse all after dates export its output to; And
The 3rd adder has one first receiving unit, one second receiving unit, one the 3rd receiving unit, an and output, wherein this first receiving unit of the 3rd adder couples this overflow output of the 1st first adder, this second receiving unit of the 3rd adder couples the output of the 1st second adder, the 3rd receiving unit of the 3rd adder receives an integer numerical value, this output of the 3rd adder couples this multiplexer, the 3rd adder is in order to its first receiving unit, after the numerical value addition that second receiving unit and the 3rd acceptance division branch receive to export its output to, and this multiplexer selects aforementioned 2 according to the numerical value of the output of the 3rd adder
NIndividual delay pulse one of them, in order to as this output pulse,
Wherein, this integer numerical value is represented the integer part of this frequency elimination multiple, and above-mentioned N and i are positive integer;
Wherein, i is that correspondence is selected from N difference integration modulator, a N+1 second adder or N-1 the second delay buffer.
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| CN103259535B (en) * | 2012-02-15 | 2018-11-23 | 联咏科技股份有限公司 | Delay locked loop circuit and delay phase-lock technique |
| CN105490666B (en) * | 2014-09-19 | 2018-08-24 | 宏达国际电子股份有限公司 | High-res clock pulse generation device and radar detection system |
| WO2019183866A1 (en) * | 2018-03-29 | 2019-10-03 | 深圳市汇顶科技股份有限公司 | Frequency generator and frequency generation method |
| CN110867199B (en) * | 2018-08-27 | 2021-07-09 | 华邦电子股份有限公司 | Synchronous mirror delay circuit and synchronous mirror delay operation method |
| TWI675280B (en) * | 2018-10-25 | 2019-10-21 | 新唐科技股份有限公司 | Clock generation circuit and clock adjustment method thereof |
| CN111198835B (en) * | 2018-11-16 | 2021-07-30 | 瑞昱半导体股份有限公司 | Clock generating device and clock generating method |
| CN111934671B (en) * | 2020-09-14 | 2021-01-05 | 四川科道芯国智能技术股份有限公司 | Multi-frequency-point frequency eliminator and control circuit |
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| CN1685616A (en) * | 2002-06-20 | 2005-10-19 | 诺基亚有限公司 | Digital delta-sigma modulator in a fractional-N frequency synthesizer |
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