CN101798054B - Wafer-level vacuum encapsulating method for micro-electromechanical device - Google Patents
Wafer-level vacuum encapsulating method for micro-electromechanical device Download PDFInfo
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Abstract
The invention provides a wafer-level vacuum encapsulating method for a micro-electromechanical device, which comprises the following steps in turn: S1, preparing a seal cover wafer and a device wafer; S2, growing a seal ring on the fronts of the device wafer and the seal cover wafer respectively; S3, growing a solder on the seal ring on the front of the seal cover wafer; S4, performing deep silicon etching on the seal cover wafer to form a groove by using the seal ring as a mask; S5, growing a degasser film on the front of the seal cover wafer, wherein the pattern of the degasser film is directly obtained from the grown mask plate; S6, heating linkage equipment to activate the degasser film, and bonding the seal cover wafer and the device wafer together; S7, growing an anti-reflection film on the back of the seal cover wafer, wherein the pattern of the anti-reflection film is directly obtained from the grown mask plate; and S8, cutting flakes. The method avoids the influence of the post process on the previous process by adjusting the sequence of the processes, and is particularly suitable for encapsulating infrared devices.
Description
Technical field
The present invention relates to a kind of wafer-level vacuum encapsulating method of micro electro mechanical device.
Background technology
Concerning micro electronmechanical (MEMS) device, traditional encapsulation technology mainly is the encapsulation of chip-scale.Technological process comprises the steps: at first preparation MEMS chip on Silicon Wafer; Then wafer is carried out pitch cutting, releasing sacrificial layer, paster, lead-in wire; Last capping.In these steps, the later step of releasing sacrificial layer is all carried out to single chip.Owing to can produce hundreds and thousands of chips after a wafer pitch cutting, therefore the cost of this wafer-level package is very high.In fact, concerning the finished product of a MEMS device, about 90% cost all consumes in encapsulation.Therefore, reduce the main development trend that packaging cost is MEMS industry.Integrated circuit (IC) has been realized wafer-level packaging, on the basis of the wafer-level packaging technology of using for reference integrated circuit, has proposed the technical scheme of the wafer-level packaging technology of MEMS device to the MEMS Devices Characteristics.
Shown in Fig. 1, Fig. 2 A and Fig. 2 B; In the wafer-level vacuum encapsulating method of traditional M EMS device; Participate in two wafer that have of encapsulation, the wafer at MEMS transducer (or integrated circuit) place is called device wafers (Device Wafer), and another sheet then is called cover wafer (Cap Wafer).
Plated multiple layer metal with the method for sputter on the device wafers 1 and formed sealing ring (Bond Ring) 4, sealing ring 4 constitutes a square frame.Sealing ring 4 outsides in device wafers 1 are provided with a plurality of lead wire tray 8, and lead wire tray 8 is passed the below of sealing ring 4 from device wafers 1 inside, form with the MEMS transducer (or integrated circuit) of device wafers 1 to be electrically connected.
Sealing ring 4 opposite positions with device wafers 1 on the cover wafer 2 have plated multiple layer metal with the method for sputter, form sealing ring 7.
Also plated one deck scolder 5 on the sealing ring 7 of cover wafer 2 through the method for plating or electronic printing.The effect of sealing ring 7 is the wettabilities in the time of should strengthening scolder 5 fusings, can stop scolder 5 scattering and permeatings again, avoids scolder 5 to contact with cover wafer 2.
Use vacuum bonding equipment then, the sealing ring on the device wafers 14 is aligned and contacts with the sealing ring 7 of cover wafer 2, after heating under atmosphere or the vacuum environment makes scolder 5 fusings, stop heating; After treating scolder 5 coolings, two wafer just have been bonded together; The unit one by one that forms after with bonding with slicing machine at last cuts down, and just becomes a complete tube core, and chip is as the bottom of tube core, and capping is as the top of tube core, and scolder is as the side wall of tube core.
In the wafer-level vacuum encapsulating method of this traditional M EMS device,, certain height is arranged because the MEMS transducer all contains hanging structure usually.In the process of bonding, scolder 5 can fusion and crystallizations again, the thickness that actual (real) thickness will be when electroplating, and the top of MEMS transducer 3 might contact with cover wafer 2 behind the bonding, causes inefficacy, the encapsulation of this conventional method, failure rate is very high.
In addition, above-described only is general MEMS wafer method for packing.Different MEMS devices, the specific requirement of its packaging technology is different.Some device, such as non-refrigeration formula infrared emanation meter array (IRFPA), its chip need be under vacuum environment could operate as normal, so need Vacuum Package, its difficulty is greater than air-tight packaging and conventional encapsulation.Therefore how to realize that vacuum and long-term maintenance vacuum degree are challenges always.Common solution is to use getter (Getter) material.Getter is the block shape normally, must be fixed on the encapsulation shell.This mode obviously is not suitable for wafer-level package.In wafer-level packaging, gettering material (Ti, TiZr, TiZrV etc.) must be deposited on the form of film on the wafer, normally is deposited on the cover wafer, in vacuum environment, activates before the bonding.Do not select to the reason of device wafers deposition gettering material to be:
(a) the technological process more complicated of chip will experience repeatedly cleaning, etching, and the high temperature in the technical process possibly activate getter in advance.
(b) zone occupied of getter can increase area of chip, and the number of chips that can comprise on the same wafer will reduce, thereby reduces production capacity, increases cost.
In addition; Non-refrigeration formula infrared emanation meter array (IRFPA) is used for infrared imaging or temperature survey more; Therefore need extraneous infrared energy to penetrate encapsulating material and incide on the chip, this has also proposed requirement to cover wafer in the transmitance of infrared band.In infrared device, often the material as optical window has Si and Ge.Si and Ge in 8-12um wave band transmitance at 40%-55%, then lower in 12-14um wave band transmitance, therefore separately lean on wafer material itself also to be not enough to reach the requirement of transmitance.The transmitance reason of lower is that quite a few incident light has been reflected on the surface of air-wafer.In order to reduce reflection, often need plate one deck anti-reflection film at the cover wafer one or both sides.
After need activating, could use getter.The active mode of film getter is realized through heating a period of time before bonding, in during this period of time, must be guaranteed that MEMS transducer and anti-reflection film do not receive the influence of high temperature.Because the temperature of bonding can not be too low, therefore tend to surpass the maximum temperature that anti-reflection film can bear.So also just limit anti-reflection film and can not be plated in the front of cover wafer.
Sealing ring, getter and anti-reflection film occupy different zones on optical window, therefore need effective patterned way.Sealing ring can use common photoetching or stripping technology to handle.But high temperature, acid, alkali, plasma etc. all might change the performance of anti-reflection film or getter, to infrared device unique packaging technology must be arranged.
Summary of the invention
The present invention will solve the technical problem of the wafer-level packaging of infrared device.
For solving the problems of the technologies described above, the present invention proposes following technical scheme:
The wafer-level vacuum encapsulating method of micro electro mechanical device of the present invention in turn includes the following steps:
S1, wafer prepare: prepare cover wafer and the device wafers that has prepared chip, wherein this cover wafer is the silicon single crystal that zone-melting process is grown, crystal orientation < 100 >;
S2, the positive and positive growth of this cover wafer sealing ring in this device wafers respectively;
S3, one deck scolder of on the sealing ring in this cover wafer front, growing;
S4, utilize sealing ring to be mask, use reactive ion etching process that dark silicon etching is carried out in the cover wafer front, form groove;
S5, in this cover wafer front with sputter or evaporation technology growth Fe Getter Films Prepared, the mask of its figure during directly by growth obtains;
S6, use wafer bonding equipment earlier through the heat activation anti-reflection film, are bonded together device wafers and cover wafer again;
S7, at this cover wafer reverse side with the evaporation technology anti-reflection film of growing, the mask of its figure during directly by growth obtains;
S8, pitch cutting.
Wherein, the sealing ring among the said step S2 is followed successively by from inside to outside:
Titanium, chromium or vanadium thickness be 300～700
Nickel thickness be 5000～7000
Titanium, chromium or vanadium thickness be 500～1000
Nickel thickness be 5000～7000
Gold, platinum or palladium thickness be 400～1000
Preferably, said sealing ring is followed successively by from inside to outside:
Titanium thickness be 500
Nickel thickness be 6000
Titanium thickness be 500
Nickel thickness be 6000
The gold thickness be 500
Among the said step S3, this solder thickness is 35～55um.
Among the said step S3, this scolder is tin, terne metal, sn-ag alloy or Sillim's alloy.
In the said step 4, this depth of groove 50～400um, preferred depth of groove 100um.
Among the said step S5, the material of this getter is titanium, titanium-zirconium alloy or titanium zirconium vanadium alloy.
Among the said step S7, the anti-reflection film material on this cover wafer is one or more of zinc sulphide, germanium and zinc selenide.
The advantage and the good effect of the wafer-level vacuum encapsulating method of micro electro mechanical device of the present invention are: the present invention is through the process sequences of the growth of adjustment sealing ring, solder deposition, getter growth, this several steps of anti-reflection film growth; And the figure of getter and anti-reflection film all be directly through mask the film growth stage with regard to straight forming; Just avoided to change the photoetching and the etching technics of these two kinds of film performances in principle, promptly avoided the influence of postchannel process preceding road process results.Simultaneously, in the method for the present invention, make mask, cover wafer carried out dark silicon etching with the sealing ring that has formed, in the etching process used gas only and pasc reaction, not with sealing ring 7 in metal reaction, therefore can not damage sealing ring and scolder.Dark silicon etching has formed groove on cover wafer; Thereby increased MEMS transducer behind the bonding the top might and cover wafer between distance; Guaranteed that the MEMS transducer can not contact with cover wafer; So can avoid the inefficacy that causes because of the two contact, so method of the present invention has farthest reduced failure rate.
Description of drawings
Fig. 1 is the wafer scale Vacuum Package principle schematic of prior micro-electromechanical device;
Fig. 2 A representes the seal ring structure sketch map of device wafers in the micro electro mechanical device shown in Figure 1;
Fig. 2 B representes the seal ring structure sketch map of cover wafer in the micro electro mechanical device shown in Figure 1;
Fig. 3 A-Fig. 3 H representes the schematic flow sheet that example is explained the wafer-level vacuum encapsulating method of micro electro mechanical device of the present invention that is encapsulated as with non-cooling type ultrared micrometering kampometer;
Fig. 4 representes the structural representation of a unit of the employed mask of growth getter in the wafer-level vacuum encapsulating method of micro electro mechanical device of the present invention; A unit figure that has only shown mask among the figure; The actual mask version comprises a plurality of such graphic elements; Cover whole wafer, the position that has been shown in dotted line sealing ring among the figure;
Fig. 5 representes the structural representation of the employed mask of growth anti-reflection film step in the wafer-level vacuum encapsulating method of micro electro mechanical device of the present invention; A unit figure that has only shown mask among the figure; The actual mask version comprises a plurality of such graphic elements; Cover whole wafer, the position that has been shown in dotted line sealing ring among the figure.
Reference numeral among the figure: 1. device wafers; 2. cover wafer; 3.MEMS transducer; 4. device wafers sealing ring; 5. scolder; 6. Fe Getter Films Prepared; 7. cover wafer sealing ring; 8. lead wire tray; 9. cover wafer reverse side anti-reflection film.
Embodiment
Below with the wafer-level vacuum encapsulating method that example is explained micro electro mechanical device that is encapsulated as of non-cooling type ultrared micrometering kampometer chip.
With reference to Fig. 3 A-Fig. 3 H, Fig. 4 and Fig. 5.According to method of the present invention, the wafer-level vacuum encapsulating method of non-cooling type ultrared micrometering kampometer chip 30 in turn includes the following steps:
S1, wafer are prepared: prepare cover wafer 2 and device wafers 1, wherein cover wafer 2 is the silicon single crystal or the germanium single crystal of molten method growth, crystal orientation < 100 >; Prepared in the device wafers 1 non-cooling type ultrared micrometering kampometer 30 and lead wire tray 8 have been arranged.
S2, respectively at device wafers 1 front and cover wafer 2 positive growth sealing rings 4,7, concrete steps are:
S2a, the photoresist about device wafers 1 front and cover wafer 2 positive spin coating 2um (positive glue) respectively;
S2b, exposure imaging carve the sealing ring figure;
S2c, sputter growth successively on the sealing ring figure:
Titanium (Ti) thickness be 500
Nickel (Ni) thickness be 6000
Titanium (Ti) thickness be 500
Nickel (Ni) thickness be 6000
The gold (Au) thickness be 500
Certainly the thickness of forming each layer of sealing ring is not limited to above-mentioned point value, and each layer thickness all is feasible in following scope:
Titanium (Ti) thickness be 300～700
Nickel (Ni) thickness be 5000～7000
Titanium (Ti) thickness be 500～1000
Nickel (Ni) thickness be 5000～7000
The gold (Au) thickness be 400～1000
Titanium wherein (Ti) also can be replaced by chromium (Cr) or vanadium (V), and gold (Au) also can be replaced by platinum (Pt) or palladium (Pd);
S2d, respectively device wafers 1 and cover wafer 2 are cleaned the unnecessary metal film of peel-away removal photoresist and sealing ring top in the ultrasonic cleaning machine with acetone;
S2e, 300 ℃ of down annealing 8 minutes.
S3, on the positive sealing ring 7 of cover wafer 2, be used as the gray tin (Sn) of scolder 5 with method growth one deck of droplet ejection, plating or chemical plating, the thickness of gray tin is 50 ± 5um, the thickness of scolder 5 all is feasible in 35～55um scope.
Electroplating or during chemical plating method growth gray tin, electroplate or chemical plating before photoresist (positive glue) about cover wafer 2 positive spin coating 2um; Exposure imaging exposes sealing ring 7 afterwards; Electroplate then or chemical plating; Remove residual photoresist at last.
S4, be mask with sealing ring 7 and the scolder on it 5, with reactive ion etching process cover wafer carried out dark silicon etching, etching depth is decided to be 100um, is the groove of 100um to form the degree of depth.In this step, etching depth is not limited to 100um, all is feasible in 50～400um scope, specifically can rationally confirm according to the height of hanging structure in the MEMS transducer.
S5, in cover wafer 2 fronts with sputter or evaporation technology growth Fe Getter Films Prepared 6, getter material is a titanium-zirconium alloy, in the growth course with mask block not need long film the zone.Need growth district 11 (see figure 4)s of long film to be about 1 * 6mm; The thickness of mask is merely 0.5mm; In growth district 11, can not produce tangible occlusion effect, that is to say, the size of growth district 11 is more a lot of greatly than mask plate thickness; Then mask can obviously not block the edge of growth district 11, and film all is more uniform in the long-living long zone 11 of the overwhelming majority like this.The material of getter also can be selected titanium or titanium zirconium vanadium alloy etc. for use.
S6, use wafer bonding equipment are earlier through the heat activation anti-reflection film; Then this cover wafer is aimed at and contacted with the sealing ring of this device wafers, under vacuum condition, add this heat-sealing lid wafer and melt fully, be cooled to room temperature again, thereby cover wafer 1 is bonded to device wafers 2 until this scolder.
S7, at the positive deposited by electron beam evaporation technologies growth of cover wafer 2 anti-reflection films 9, the anti-reflection film material is one or more in zinc sulphide (ZnS), germanium (Ge) and the zinc selenide (ZnSe), in the growth course with mask block not need long film the zone.Need growth district 12 (see figure 5)s of long film to be about 8 * 8mm; The thickness of mask is merely 0.5mm; In growth district 12, can not produce tangible occlusion effect (Shadow effect), that is to say that the size of growth district 12 is more a lot of greatly than mask plate thickness; Then mask can obviously not block the edge of growth district 12, and film all is more uniform in the long-living long zone 12 of the overwhelming majority like this.
S8, pitch cutting.
In the wafer-level vacuum encapsulating method of micro electro mechanical device of the present invention; The step of growth sealing ring and scolder is arranged in growth getter and growth anti-reflection film step front, so the needed chemical wet etching technology of sealing ring figure moulding, sealing ring high temperature of annealing and the chemical composition in the electroplate liquid character that can not have influence on getter and anti-reflection film.In addition, among the present invention, the nickel in the sealing ring (Ni) adopts hierarchy.Too thick nickel film may cause demoulding owing to stress is excessive.The titanium film that inserts one deck 500～1000
in the centre is relieve stresses effectively.What gross thickness was that the nickel film of 1.2um plays a part is to stop scolder diffusion.400～1000
gold can strengthen the wetability of scolder.Utilize in the reactive ion etching technology etching gas to material chosen property, with sealing ring with its on scolder as mask, can directly carry out dark silicon etching to cover wafer, saved the step of photoetching.So the wafer-level vacuum encapsulating method of micro electro mechanical device of the present invention is specially adapted to the wafer scale Vacuum Package of infrared micro electro mechanical device.
The wafer-level vacuum encapsulating method of micro electro mechanical device of the present invention, technology is simple, is convenient to realize, can shorten the encapsulation cycle of micro electro mechanical device greatly, improves production capacity, reduces packaging cost.
Though described the present invention with reference to several exemplary embodiments, should be appreciated that used term is explanation and exemplary and nonrestrictive term.Because the present invention's practical implementation and do not break away from the spirit or the essence of invention in a variety of forms; So be to be understood that; The foregoing description is not limited to any aforesaid details; And should in enclose spirit that claim limited and scope, explain widely, therefore fall into whole variations and remodeling in claim or its equivalent scope and all should be the claim of enclosing and contain.
Claims (9)
1. the wafer-level vacuum encapsulating method of a micro electro mechanical device is characterized in that, this method in turn includes the following steps:
S1, wafer prepare: prepare cover wafer and the device wafers that has prepared chip, wherein this cover wafer is silicon single crystal or the germanium single crystal that zone-melting process is grown, crystal orientation < 100 >;
S2, the positive and positive growth of this cover wafer sealing ring in this device wafers respectively; Wherein, sealing ring is followed successively by from inside to outside: titanium, chromium or vanadium, nickel, titanium, chromium or vanadium, nickel, gold, platinum or palladium;
S3, one deck scolder of on the sealing ring in this cover wafer front, growing;
S4, utilize sealing ring to be mask, use reactive ion etching process that dark silicon etching is carried out in the cover wafer front, form groove;
S5, in this cover wafer front with sputter or evaporation technology growth Fe Getter Films Prepared, the mask of its figure during directly by growth obtains;
S6, use wafer bonding equipment earlier through the heat activation anti-reflection film, are bonded together device wafers and cover wafer again;
S7, at this cover wafer reverse side with the evaporation technology anti-reflection film of growing, the mask of its figure during directly by growth obtains;
S8, pitch cutting.
2. the wafer-level vacuum encapsulating method of micro electro mechanical device according to claim 1 is characterized in that, the thickness of the sealing ring among the said step S2 is followed successively by respectively from inside to outside:
3. the wafer-level vacuum encapsulating method of micro electro mechanical device according to claim 2 is characterized in that, said sealing ring is followed successively by from inside to outside:
4. the wafer-level vacuum encapsulating method of micro electro mechanical device according to claim 1 is characterized in that, among the said step S3, this solder thickness is 35～55um.
5. the wafer-level vacuum encapsulating method of micro electro mechanical device according to claim 4 is characterized in that, among the said step S3, this scolder is tin, terne metal, sn-ag alloy or gold-tin alloy.
6. the wafer-level vacuum encapsulating method of micro electro mechanical device according to claim 1 is characterized in that, among the said step S4, the degree of depth of groove is 50～400um.
7. the wafer-level vacuum encapsulating method of micro electro mechanical device according to claim 6 is characterized in that, among the said step S4, the degree of depth of groove is 100um.
8. the wafer-level vacuum encapsulating method of micro electro mechanical device according to claim 7 is characterized in that, among the said step S5, the material of this getter is titanium, titanium-zirconium alloy or titanium zirconium vanadium alloy.
9. according to the wafer-level vacuum encapsulating method of arbitrary described micro electro mechanical device of claim 1-8, it is characterized in that among the said step S7, the anti-reflection film material on this cover wafer is one or more of zinc sulphide, germanium and zinc selenide.
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| CN102351141A (en) * | 2011-11-01 | 2012-02-15 | 北京大学 | Wafer level vacuum encapsulating method for MEMS (Micro Electro Mechanical System) components |
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