CN101789032A - Design method and structure thereof of physical layout of CUP weld pad zone - Google Patents
Design method and structure thereof of physical layout of CUP weld pad zone Download PDFInfo
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- CN101789032A CN101789032A CN200910151189A CN200910151189A CN101789032A CN 101789032 A CN101789032 A CN 101789032A CN 200910151189 A CN200910151189 A CN 200910151189A CN 200910151189 A CN200910151189 A CN 200910151189A CN 101789032 A CN101789032 A CN 101789032A
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- 239000002184 metal Substances 0.000 claims description 42
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- 238000002161 passivation Methods 0.000 claims description 26
- 230000008569 process Effects 0.000 abstract description 6
- 238000003466 welding Methods 0.000 abstract description 6
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 239000000523 sample Substances 0.000 description 17
- 238000005538 encapsulation Methods 0.000 description 11
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- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Abstract
The invention relates to design method and structure thereof of physical layout of a CUP weld pad zone. The method comprises the following steps of: determining the required number of through holes; determining the minimum allowable spacing among the through holes; dispersing the through holes in a zone outside a passivating window at intervals smaller than the minimum allowable spacing; and when the required amount of through holes can not be arranged in the zone outside the window, arranging the rest of through holes in the edge zone of the window or the zone far away from the center in the window. The through holes of the structure of the physical layout of CUP weld pad zone are evenly dispersed in the zone far away from the center of the passivating window, which can reduce the generation of bad microdefects in the pressure welding process and keep the stability of the structure of the weld pad zone, thereby improving the yield and the reliability of chip packaging.
Description
Technical field
The present invention relates to the physical layout design method and the structure thereof of input/output port of physical layout design method and structure thereof, especially CUP (CIRCUIT UNDER PAD, the weld pad dropper spare) type of integrated circuit (IC) chip.
Background technology
Use the metal bonding wire to connect weld pad (input/output port in the circuit) to external system during the integrated circuit (IC) chip encapsulation, under certain process conditions, the physical layout design of input/output port directly has influence on the yield rate and the reliability of encapsulation.Because the chip of the input/output port of CUP type has circuit devcie to exist below pad zone; some metal levels are used to interface unit; make as the metal of CUP pad zone which floor metal that lack than non-CUP pad zone, simultaneously connect these metals of bonding wire and probe as the CUP pad zone also play a part to protect below circuit.Therefore, in the design of CUP type, the structure of pad zone is complicated more; its design should be satisfied the function of common weld pad; protection is without prejudice following circuit again, and following circuit has certain influence for again the reliability and stability of pad zone, and its design is complicated more.
Window and peripheral region at the CUP pad zone have top-level metallic at least, the metal of top layer through hole and time one deck.Top-level metallic and time layer of metal couple together the metal construction that constitutes the basic perforation pad zone that is connected fully by the top layer through hole.
CUP pad zone physical layout design method commonly used is that through hole is evenly distributed between top layer and the inferior layer of metal.Fig. 1 is the top plan view of CUP pad zone commonly used, and wherein, 1. through hole is the passage that connects between the metal, and is metal filled in these through holes, forms the extremely low path of resistance.2. the window of pad zone (passivation window); usually chip surface is covered with the glazed passivation of one deck class; the protection chip internal; the part that needs in the chip to connect out will have corresponding window; exposed metal/bare metal comes out in the window; during connection, the metal that bonding wire or probe and this sheet are exposed forms the path of low-resistance, satisfies encapsulation or the machinery of test and the requirement of electricity.3. pad zone metal, what vertical view showed is the metal of top layer, also has layer of metal to be connected with top-level metallic by through hole below at least.
This method design is fairly simple, original, but the through hole that metal is asked can exert an influence to the integrality of metal inevitably, the CUP structure makes that this influence is more remarkable simultaneously, there are some minute defects near it, when the window at pad zone adds the strength of pressure welding line (or probe), these micro-crack defectives can be exaggerated diffusion and cause the adhesiveness decline of double layer of metal and bigger crackle to occur, thereby cause the pulling force or the pressure-bearing deficiency of bonding wire, break away from easily or the damage pad zone.
At present in the packing forms of integrated circuit, each chip has tens to a hundreds of pad zone, and the trend that significantly increases in addition of pad zone quantity.The inefficacy that quality problems will cause entire chip appears in certain pad zone, i.e. encapsulation failure.
For reducing the generation of this micro-crack defective in the stressed zone, industry has a lot of methods for designing, relatively is typically to separate wire welding area and probe test district, behind the probe test, makes wire welding area not have the damage of probe like this, and encapsulation does not exert an influence to bonding wire.Shortcoming is to go to distinguish this two zones by very big area, and the micro-crack defective still exists.Also have method to reduce number of openings exactly, therefore this micro-crack defective can reduce, but still can have more inefficacy.
Here mention probe test and be because before encapsulation, need to do the operation of some wafer scale, such as pre-detection before the encapsulation of wiping write operation and product of memory content etc. in some integrated circuit (IC) products.
Given this, for the adhesiveness that overcomes CUP pad zone double layer of metal and the problem of stability decreases, be necessary to propose a kind of new method for designing to address the above problem in fact.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method for designing and structure thereof of CUP pad zone physical layout, can reduce the generation of bad microdefect in the pressure welding process, keep the pad zone stability of structure, thereby improved the yield rate and the reliability of Chip Packaging.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of method for designing of CUP pad zone physical layout, the structure of described domain comprises top-level metallic, sublevel metal, connect the through hole of top-level metallic and sublevel metal and be positioned at passivation layer on the top-level metallic, described passivation layer has window, top-level metallic is exposed out, and this method may further comprise the steps:
(1) is connected resistance and, determines the quantity of required through hole according to top-level metallic and sublevel are intermetallic by electric current;
(2) determine minimum allowable spacing between each through hole according to the technological design rule;
(3) with through hole to disperse to be positioned over greater than minimum allowable spacing in the zone outside the described window;
(4) area arrangement beyond the described window is down during the through hole of required quantity, remaining through hole being placed on the fringe region of window greater than minimum allowable spacing, or in the window away from the zone of window center.
As one of preferred version of the present invention, when determining the quantity of through hole in the step (1), be connected resistance and calculate the quantity of required through hole respectively by electric current according to top-level metallic and sublevel are intermetallic, get the maximal value in these two result of calculations.So can guarantee to make that top-level metallic and sublevel are intermetallic is connected the enough little while of resistance and can also passes through enough big electric current.
As one of preferred version of the present invention, the spacing of the middle through hole in described step (3) or (4) is 2-3 a times of described minimum allowable spacing.
As one of preferred version of the present invention, described through hole is disperseed to place equably.
A kind of structure of the CUP pad zone physical layout that obtains by the described method for designing of claim 1, the through hole that comprises top-level metallic, sublevel metal, connection top-level metallic and sublevel metal, and be positioned at passivation layer on the top-level metallic, described passivation layer has window, top-level metallic is exposed out, it is characterized in that: the homodisperse zone that is positioned at away from window center of through hole.
As one of preferred version of the present invention, the homodisperse zone that is positioned at outside the described window of through hole.
As one of preferred version of the present invention, through hole is homodisperse to be positioned at the zone outside the described window and the fringe region of window.
As one of preferred version of the present invention, through hole is homodisperse to be positioned at the fringe region of zone outside the described window, window and the window zone away from window center.
As one of preferred version of the present invention, through hole is to be placed dispersedly greater than minimum allowable spacing.
Compared to prior art, beneficial effect of the present invention is:
For the adhesiveness that overcomes CUP pad zone double layer of metal and the problem of stability decreases, the present invention has studied the existing processes technical parameter, finds the basic reason that has problems, and through hole is improved with relevant metal layout design method.
To discovering of technological parameter, the CUP pad zone does not have adhesiveness between the double layer of metal of through hole and stability than the zone height that through hole is arranged, and when stress took place, there was different strain responses in two kinds of zones, and the stability of no via regions is higher.Owing to the adhesiveness of the double layer of metal that through hole is arranged is stable than there not being the poor of through hole, still do not place the design of the effective pad zone of the just impossible formation of through hole, but also number of through-holes that need be enough formation low resistance connection.
As previously mentioned, use the metal bonding wire to connect weld pad (input/output port in the circuit) to external system when integrated circuit (IC) chip encapsulates, the zone that bonding wire connects is the passivation window, and promptly the metallic region of exposing in the window also is probe and encapsulation operation zone.Through hole is the interface channel between the metal, and the stability of its layout and structure influence relevant range does not have direct physics to contact with encapsulation and probe operation.
During will designing, the present invention is placed on the through hole of the stressed zone of pad zone window (being the passivation window) usually, be placed on the non-window area of pad zone, or, avoid influencing the adhesiveness between the metal at bonding wire or probe operation place, thereby improve reliability away from the zone of pad zone window center.General stressed zone is positioned at the pad zone window, produces when the pad zone window is tested at pad zone window or probe because stress is wire bonding.
This method is applicable to different technology types and different bonding wire encapsulated types, can be under the situation that does not change process conditions, by adjusting via arrangements can improve encapsulation and probe test under the condition that guarantees electric property yield rate and reliability.
Description of drawings
Fig. 1 is the domain structure synoptic diagram of the CUP pad zone used always;
Fig. 2 concentrates on the domain structure synoptic diagram of the CUP pad zone of pad zone window for through hole;
Fig. 3 is scattered in the domain structure synoptic diagram of the CUP pad zone of pad zone window for through hole;
The domain structure synoptic diagram of Fig. 4 a-4c CUP pad zone of the present invention.
Description of symbols among the figure:
The 1-through hole; The window of 2-pad zone; The metal of 3-pad zone.
Embodiment
Further specify concrete implementation step of the present invention below in conjunction with accompanying drawing, for the convenience that illustrates, accompanying drawing is not proportionally drawn.
In order better to describe beneficial effect of the present invention, several CUP pad zone domain structures have at first been designed, these structures all comprise top-level metallic, sublevel metal, connect the through hole of top-level metallic and sublevel metal, and be positioned at passivation layer on the top-level metallic, described passivation layer has window, the passivation window exposes out with top-level metallic, shown in Fig. 2,3,4a-4c.Wherein, Fig. 2 concentrates on the domain structure of pad zone window (being the passivation window) for through hole; Fig. 3 is scattered in the domain structure of pad zone window for through hole; Fig. 4 a-4c is for adopting the domain structure of method design of the present invention.
When designing structure of the present invention: at first, be connected resistance and, determine the quantity of required through hole by electric current according to top-level metallic and sublevel are intermetallic.When determining the quantity of through hole, make that top-level metallic and sublevel are intermetallic to be connected enough little also the wanting simultaneously of resistance and can to pass through enough big electric current.Then, determine minimum allowable spacing between each through hole; With through hole to disperse to be positioned over greater than minimum allowable spacing in the zone outside the described window area.Area arrangement beyond the described window area is down during the through hole of required quantity, and remaining through hole is placed on the fringe region of window, or in the window away from the zone of passivation window center.
Embodiment one
Referring to Fig. 4 a, the through hole of this structure is with greater than the homodisperse fringe region that only is positioned at zone outside the window, window of minimum allowable spacing and the window zone away from the passivation window center.
The specific design step of present embodiment is:
Step 1 is determined the quantity of required through hole.For example the resistance value R1 of single through hole is 4 ohm, the electric current handling capacity J of single through hole is 0.28mA (different process may be different), single input and output designing requirement top-level metallic and sublevel are intermetallic to be 40mA by electric current I, the total resistance value R of all through holes is below 0.02 ohm, and then calculating minimum via count is 200.This result is the maximal value in the minimum acceptable value of different design consideration, as, consider according to resistance: R1/R=4/0.02=200, consider according to electric current: I/J=40/0.28=143.So we get 200.
Preferably, consider some design margins, we can place the through hole about 250-300, in the present embodiment, will place 300 through holes altogether.
Step 4 when window fails to lay down all (300) through holes with exterior domain, is remaining through hole 50 here, can consider to be placed on the marginal position and the interior zone away from the passivation window center of window of window, and spacing remains unchanged.The area of the metal of CUP type is enough big generally speaking, can place the through hole of needed all quantity.
Embodiment two
Referring to Fig. 4 b, its through hole is with greater than the homodisperse zone outside the described window and the fringe region of window of only being positioned at of minimum allowable spacing (280nm).
The method for designing of present embodiment is identical with embodiment one, and difference is: place 270 through holes altogether, placed 250 through holes at window with exterior domain, remaining 20 through hole is placed on the marginal position of window, the spacing of through hole is 700nm.
Embodiment three
Referring to Fig. 4 c, its through hole is with greater than the homodisperse zone that only is positioned at outside the described window of minimum allowable spacing (280nm).
The method for designing of present embodiment is identical with embodiment one, and difference is: place 260 through holes altogether, wherein, 260 through holes all are placed on the zone beyond the window, and the spacing of through hole is 600nm.
After designing various domain structures, respectively the domain structure shown in Fig. 2,3, the 4a-4c is tested.In order to guarantee to design the validity with the result, we have adopted a kind of very strict industrial test screening, comprise pulling experiment and fault detection.Comparatively strict and complicated means of testing such as probe test when experiment, have been adopted.
Passivation window among Fig. 2,3, the 4a-4c is used for bonding wire encapsulation and carry out probe test, and this regional exposed metal/bare metal comes out to be used for to form the low resistance connection with probe and bonding wire.Through hole concentrates on the passivation window among Fig. 2, but the passivation window is with the corresponding minimizing of accessibke porosity; Through hole is placed on the non-passivation window area more among Fig. 3, disperses at the passivation window with then arranging; Most through holes are dispersed in outside the passivation window among Fig. 4 a-4c, and the only a few through hole is at the edge of passivation window, and when pressure welding or probe test, these only a few through holes can be in the stressed zone, and the number of through-holes of Zeng Jiaing has improved electric property simultaneously.
Experimental result shows after experiments such as the contact of repeatedly probe, tensile test (＞2.5 gram), the circulation of high low temperature be aging, adopt the highest 92% the yield rate that can reach of device of the present invention, and the device yield of other structures is at 11%-89%.The screening of general commercial standard does not have so many test events.According to the general commercial standard, adopt the device of structure of the present invention that higher yield rate will be arranged, estimating can be more than 95%.The raising of each percentage point all will greatly reduce cost when the device volume production, increase the benefit.Above-mentioned experimental result is applicable to different technology types and different bonding wire encapsulated types.
The other technologies that relate among the present invention are routine techniques, belong to the category that those skilled in the art are familiar with, and do not repeat them here.
The foregoing description is the unrestricted technical scheme of the present invention in order to explanation only.Any technical scheme that does not break away from spirit and scope of the invention all should be encompassed in the middle of the patent claim of the present invention.
Claims (9)
1. the method for designing of a CUP pad zone physical layout, the structure of described domain comprises top-level metallic, sublevel metal, connect the through hole of top-level metallic and sublevel metal and be positioned at passivation layer on the top-level metallic, described passivation layer has window, top-level metallic is exposed out, it is characterized in that this method may further comprise the steps:
(1) is connected resistance and, determines the quantity of required through hole according to top-level metallic and sublevel are intermetallic by electric current;
(2) determine minimum allowable spacing between each through hole according to the technological design rule;
(3) with through hole to disperse to be positioned over greater than minimum allowable spacing in the zone outside the described window;
(4) area arrangement beyond the described window is down during the through hole of required quantity, remaining through hole being placed on the fringe region of window greater than minimum allowable spacing, or in the window away from the zone of window center.
2. the method for designing of CUP pad zone physical layout according to claim 1, it is characterized in that: when determining the quantity of through hole in the step (1), be connected resistance and calculate the quantity of required through hole respectively according to top-level metallic and sublevel are intermetallic, get the maximal value in these two result of calculations by electric current.
3. the method for designing of CUP pad zone physical layout according to claim 1 is characterized in that: the spacing of the middle through hole in described step (3) or (4) is 2-3 a times of described minimum allowable spacing.
4. the method for designing of CUP pad zone physical layout according to claim 1 is characterized in that: described through hole is disperseed to place equably.
5. the structure of a CUP pad zone physical layout that obtains by the described method for designing of claim 1, the through hole that comprises top-level metallic, sublevel metal, connection top-level metallic and sublevel metal, and be positioned at passivation layer on the top-level metallic, described passivation layer has window, top-level metallic is exposed out, it is characterized in that: the homodisperse zone that is positioned at away from window center of through hole.
6. the structure of CUP pad zone physical layout according to claim 5 is characterized in that: the homodisperse zone that is positioned at outside the described window of through hole.
7. the structure of CUP pad zone physical layout according to claim 5 is characterized in that: through hole is homodisperse to be positioned at the zone outside the described window and the fringe region of window.
8. the structure of CUP pad zone physical layout according to claim 5 is characterized in that: through hole is homodisperse to be positioned at the fringe region of zone outside the described window, window and the window zone away from window center.
9. the structure of CUP pad zone physical layout according to claim 5 is characterized in that: through hole is to be placed dispersedly greater than minimum allowable spacing.
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| CN2009101511893A CN101789032B (en) | 2009-07-23 | 2009-07-23 | Design method and structure thereof of physical layout of CUP weld pad zone |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103123657A (en) * | 2011-11-21 | 2013-05-29 | 上海华虹Nec电子有限公司 | Method for automatically appending redundant hole for chip physical layout |
| US10052949B2 (en) | 2012-05-15 | 2018-08-21 | GKN Driveline Japan Ltd. | Drivetrain control method and system |
| CN111008512A (en) * | 2019-12-04 | 2020-04-14 | 成都九芯微科技有限公司 | Layout design method for reducing packaging stress |
| CN113113322A (en) * | 2021-03-31 | 2021-07-13 | 上海华虹宏力半导体制造有限公司 | CUP through hole overlap correction method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1282245C (en) * | 2002-12-13 | 2006-10-25 | 矽统科技股份有限公司 | Semiconductor chip with partial embedded decoupling capacitance |
| CN100349289C (en) * | 2004-09-24 | 2007-11-14 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and its manufacturing method |
| CN100459081C (en) * | 2006-07-10 | 2009-02-04 | 中芯国际集成电路制造(上海)有限公司 | Making method of solder protruding block |
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2009
- 2009-07-23 CN CN2009101511893A patent/CN101789032B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103123657A (en) * | 2011-11-21 | 2013-05-29 | 上海华虹Nec电子有限公司 | Method for automatically appending redundant hole for chip physical layout |
| US10052949B2 (en) | 2012-05-15 | 2018-08-21 | GKN Driveline Japan Ltd. | Drivetrain control method and system |
| CN111008512A (en) * | 2019-12-04 | 2020-04-14 | 成都九芯微科技有限公司 | Layout design method for reducing packaging stress |
| CN113113322A (en) * | 2021-03-31 | 2021-07-13 | 上海华虹宏力半导体制造有限公司 | CUP through hole overlap correction method |
| CN113113322B (en) * | 2021-03-31 | 2024-03-15 | 上海华虹宏力半导体制造有限公司 | CUP through hole overlapping correction method |
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Denomination of invention: Design method and structure thereof of physical layout of CUP weld pad zone Effective date of registration: 20170726 Granted publication date: 20120718 Pledgee: National integrated circuit industry investment fund, Limited by Share Ltd Pledgor: VeriSilicon Microelectronics (Shanghai) Co., Ltd.|VeriSilicon Holdings Co., Ltd.|VeriSilicon Microelectronics (Beijing) Co., Ltd. Registration number: 2017990000684 |
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| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 201203 Zhangjiang Building 20A, 289 Chunxiao Road, China (Shanghai) Free Trade Pilot Area, Pudong New Area, Shanghai Co-patentee after: Core holdings limited company Patentee after: Xinyuan Microelectronics (Shanghai) Co., Ltd. Co-patentee after: VeriSilicon Microelectronics (Beijing) Co., Ltd. Address before: 201203 Zhangjiang Building 20A, 560 Songtao Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai Co-patentee before: VeriSilicon Holdings Co., Ltd. Patentee before: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Co-patentee before: VeriSilicon Microelectronics (Beijing) Co., Ltd. |