CN101615287A - A kind of image processing IP core based on the Wishbone bus - Google Patents
A kind of image processing IP core based on the Wishbone bus Download PDFInfo
- Publication number
- CN101615287A CN101615287A CN200910041725A CN200910041725A CN101615287A CN 101615287 A CN101615287 A CN 101615287A CN 200910041725 A CN200910041725 A CN 200910041725A CN 200910041725 A CN200910041725 A CN 200910041725A CN 101615287 A CN101615287 A CN 101615287A
- Authority
- CN
- China
- Prior art keywords
- module
- bus
- sdram
- wishbone
- image processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Image Processing (AREA)
Abstract
The invention discloses a kind of image processing IP core based on the Wishbone bus, it mainly comprises Host Controler Interface module, SDRAM control module, command interpretation module, display control module and bus arbitration module; Described each module is all passed through the Wishbone interface, adopts the mutual contact mode of shared bus, realizes the connection of each module and the exchange of data.Described Host Controler Interface module, SDRAM control module, command interpretation module, display control module all have the Wishbone bus interface, connect in the shared bus mode in the Wishbone standard, they all must be filed an application to the bus arbitration module when the contention bus right to use.This IP kernel is specifically applied to the Flame Image Process aspect, can realize the multiple algorithms such as convergent-divergent, rotation and Alpha Blending of image, and function is strong, simple in structure, and scalability is good.
Description
Technical field
The present invention is a kind of image processing IP core based on the Wishbone bus, relates to fields such as IP kernel design and Digital Image Processing.
Background technology
Digital image processing techniques are emerging technology fields that produce, develop and constantly grow up the sixties in 20th century.Enter 21 century, constantly perfect along with rapid development of computer technology and correlation theory, digital image processing techniques have a wide range of applications in fields such as Aero-Space, commercial production, medical diagnosis, resource environment, meteorology and Traffic monitoring, culture and educations, have created huge social value.
But traditional image processor is owing to limited by clock and inner structure, processing speed is slower, even adopt special-purpose picture processing chip to promote processing speed, but because it is non-programmable, thereby the product development personnel just can not revise fixed function hardware at an easy rate, make it support new standard or different functions, lack dirigibility.Secondly, traditional image processor function singleness generally is primarily aimed at specialized field and realizes the particular procedure function, and versatility is poor.In addition, traditional image processor construction cycle is long, device upgrade speed is slow, cost is high, cost performance is relatively low.
Summary of the invention
At the various deficiencies and the shortcoming of traditional picture processing chip, the invention provides the image processing IP core that a kind of function is strong, simple in structure and scalability is good, compatibility is good based on the Wishbone bus.
For solving the problems of the technologies described above, technical scheme provided by the invention is: a kind of image processing IP core based on the Wishbone bus, and it mainly comprises Host Controler Interface module, SDRAM control module, command interpretation module, display control module and bus arbitration module; Described each module is all passed through the Wishbone interface, adopts the mutual contact mode of shared bus, realizes the connection of each module and the exchange of data.Described Host Controler Interface module, SDRAM control module, command interpretation module, display control module all have the Wishbone bus interface, connect in the shared bus mode in the Wishbone standard, they all must be filed an application to the bus arbitration module when the contention bus right to use.Described bus arbitration module to the bus request of Host Controler Interface module, SDRAM control module, command interpretation module and display control module sort, the distribution bus right to use, solve bus master to the mutual competitions and conflicts of resource, realize the interconnection of IP kernel on the sheet.Described Wishbone bus is exactly the interconnection of shared bus and right-angled intersection mode.
Described Host Controler Interface module is mainly finished the data communication of external piloting control system device and IP kernel, and its communication mode has asynchronous handshake mode and dma mode.This inside modules comprises configuration register, command register and data register 3 class registers.Wherein configuration register is used for store configuration information to finish the parameter setting of SDRAM control module, command interpretation module and display control module; Command register is used for the memory image processing command so that store SDRAM into or read to external piloting control system device; Data register is used to store image transmitted data so that store SDRAM into or read to external piloting control system device.
Described SDRAM control module is used to finish the data access to SDRAM.This inside modules is provided with sdram controller, configuration register and SDRAM address register.Wherein sdram controller can be finished the basic operation such as read-write, precharge, self-refresh and mode register loading of SDRAM and the SDRAM address that can provide according to other modules and data according to the parameter that the value of configuration register is set SDRAM and finish visit to SDRAM.
Described command interpretation module is used to finish the explanation and the treatment of picture of order.This inside modules comprises Wishbone Master module, image processor and configuration register.Wherein configuration register is used to be provided with the base address that image processing command and view data are deposited, so that Wishbone Master finishes reading of order and image; Image processor is responsible for reading related command and explanation from the order buffer area, finishes the processing operation of required image at last; By Wishbone Master view data is deposited back SDRAM for the display control module reading displayed again after disposing.
Described display control module is used to finish the image output after the processing.This inside modules has VGA main equipment and groups of configuration registers.The VGA main equipment base address of depositing in SDRAM according to controlled variable such as the line frequency that obtains from groups of configuration registers, field frequency and view data wherein sends view data to DAC with correct way and handles and be converted to simulating signal and output to display and show.
Described SDRAM is divided into four districts, is respectively command queue district, raw image storage district and two frame buffer zones.
The Wishbone bus is to be proposed by Silicore company, is transferred to the OpenCores organizational protection now.Since its opening, existing now many user groups.Some free IP kernels particularly, great majority all adopt the Wishbone standard.These bus structure have public interface specification and make things convenient for Structured Design, have solved IP kernel portability, the multiplexing problem of design effectively.
The Wishbone bus provides configurable interconnection mode for the semiconductor kernel, can make the various kernels formation SOC (system on a chip) that interconnects.The Wishbone bus has very strong compatibility, and the interface that has improved the reusability Wishbone bus of design is independent of semiconductor technology, and its interconnection mode both can be supported FPGA equipment, also can support ASIC equipment; The Wishbone bus protocol is simple, understandable.
The Wishbone bus is a kind of bussing technique of master/slave interface architecture, if having effective arbitration mechanism, bus system can be supported a plurality of master/slave interfaces; The configurability of Wishbone bus is mainly reflected in the interconnection mode of supporting point-to-point, shared bus, data stream, cross bar switch type; The Wishbone bus protocol had both comprised the synchronous transmission agreement that a kind of easy use, reliability height, Easy Test, all bus transaction can be worked in coordination with in a clock period, also comprised the XON/XOFF in standard time clock cycle; The synchronous transmission agreement of Wishbone bus can be operated on the large-scale clock frequency.The Wishbone bus interface both can be synchronous with the kernel clock period like this, also can be synchronous with different target devices, and sequential is all very simple.In addition, in addition, when system comprised a plurality of MASTER interface, the Wishbone bus allowed User Defined bus arbitration mode and algorithm.
The Wishbone bus also has following characteristics:
Simply, compact hardware logic interface, need logic gate still less;
Support popular individual character read/write, piece read/write, the bus protocol of reading-revise-writing;
Adjustable bus and operand bit wide;
Support big end (big endian) and two kinds of data representation methods of small end (little endian);
Handshake Protocol can control data transmission speed;
Support the monocycle data transmission;
Part address decoder from interface;
According to system's needs, the user can self-defined increase interface signal;
When system comprised a plurality of MASTER interface, the user can self-defined bus arbitration mode and algorithm.
The variety of issue of the image processor that the appearance of IP kernel technology is can fine solution traditional, IP kernel has reusability, makes the construction cycle of chip shorten widely, and cost of development reduces, and favorable expandability, and the expansion of function is convenient and swift.
Compared with prior art, the present invention is based on the image processing IP core of Wishbone bus, and its primary structure comprises Host Controler Interface module, SDRAM control module, command interpretation module, display control module and five parts of bus arbitration module.This IP kernel has adopted the Wishbone bus structure, and each module adopts the mutual contact mode of shared bus, realizes the exchange of connection and data.This IP kernel is specifically applied to the Flame Image Process aspect, can realize the multiple algorithms such as convergent-divergent, rotation and Alpha Blending of image, can be according to actual needs the related algorithm of other Flame Image Process form with IP kernel be hung on the shared bus, thereby the expansion on implementation structure and the function is very convenient and practical.
Description of drawings
Accompanying drawing 1 is based on the image processing IP core inner structure synoptic diagram of Wishbone bus;
Accompanying drawing 2 is synoptic diagram of image processing system;
Accompanying drawing 3 is Flame Image Process schematic flow sheets.
Embodiment
Be elaborated below in conjunction with accompanying drawing, so that technical characterictic of the present invention is carried out more deep annotation.
As shown in Figure 1, a kind of image processing IP core based on the Wishbone bus, it mainly comprises Host Controler Interface module, SDRAM control module, command interpretation module, display control module and bus arbitration module; Described each module is all passed through the Wishbone interface, adopts the mutual contact mode of shared bus, realizes the connection of each module and the exchange of data.Described Host Controler Interface module, SDRAM control module, command interpretation module, display control module all have the Wishbone bus interface, connect in the shared bus mode in the Wishbone standard, they all must be filed an application to the bus arbitration module when the contention bus right to use.Described bus arbitration module to the bus request of Host Controler Interface module, SDRAM control module, command interpretation module and display control module sort, the distribution bus right to use, solve bus master to the mutual competitions and conflicts of resource, realize the interconnection of IP kernel on the sheet.Described Wishbone bus is exactly the interconnection of shared bus and right-angled intersection mode.
1, Host Controler Interface module
The Host Controler Interface module is used to finish the data communication of external piloting control system device and IP kernel, and its communication mode has asynchronous handshake mode and dma mode.This inside modules comprises 3 registers, is respectively configuration register, command register and data register.Wherein configuration register is used for store configuration information to finish the parameter setting of the inner sdram controller of described IP kernel, vga controller and command interpretation module.Command register block is used for the image processing command that buffer memory receives from external piloting control system device so that store SDRAM into or read to master controller.Data register bank is used to store image transmitted data that receive from external piloting control system device so that store SDRAM into or read to master controller.
2, SDRAM control module
The SDRAM control module is used to finish the data access to SDRAM.There are sdram controller, configuration register, SDRAM address register in its inside.Sdram controller can be set the parameter of SDRAM according to the value of configuration register, comprises CAS time-delay, burst-length and self-refresh interval etc.; Finish the basic operation of SDRAM, as read-write, precharge, self-refresh and mode register loading etc.; SDRAM address that provides according to other modules and data are finished the visit to SDRAM.When input and output, introduce 4 FIFO simultaneously, solved the inconsistent problem of clock frequency of sdram controller and Wishbone bus, guarantee the integrality and the correctness of data transmission in the cross clock domain.
3, command interpretation module
The command interpretation module is mainly finished two tasks: command interpretation and Flame Image Process.It comprises 1 Wishbone Master module, 1 image processor and 1 groups of configuration registers.Wherein groups of configuration registers is used to be provided with the base address that image processing command and view data are deposited, and WishboneMaster just can finish reading of order and image like this.The output of image has all been introduced FIFO as buffer zone after reading order, reading images and processing.In addition, Wishbone Master module also is responsible for the interpretation of images processing command.And all orders all will be encapsulated as an order bag, and WishboneMaster obtains will analyze after this order is wrapped the first 16bit of order bag from SDRAM, need to determine the processing of execution.The remaining every 16bit of part of order bag represents the concrete parameter of a processing command, as the display position of image, and size etc., the Master module is delivered to corresponding process nuclear in the image processor to parameter according to the processing that will carry out.And then, Wishbone Master reads raw image data to FIFO from SDRAM, deliver to then in the corresponding processing unit and handle.The back Wishbone Master that disposes deposits back view data SDRAM again for the display control module reading displayed.
4, display control module
Display control module is used to finish image output.There are 1 VGA main equipment, 1 groups of configuration registers in its inside.The VGA main equipment will obtain the base address that controlled variable such as line frequency, field frequency and view data are deposited in SDRAM from groups of configuration registers, so just can send view data to DAC with correct way and handle and be converted to simulating signal and output to display and show.
5, bus arbitration module
The above-mentioned Host Controler Interface module of mentioning, command interpretation module and display control module all need SDRAM is carried out accessing operation.Because each module has all adopted the Wishbone interface of standard, so each module can independently be seen an IP kernel as.In order to solve the contention problem of each module to SDRAM, the bus arbitration module will sort to the request of each module, realize the interconnection of IP kernel on the sheet.
Fig. 2 is the system chart of image processing platform, and wherein said image processing IP core based on the Wishbone bus makes up an image processing platform jointly as a coprocessor and master controller in system.Master controller is as a data source, is responsible for the order bag and the view data that transmit, then the order bag made an explanation based on the image processing IP core of Wishbone bus, and carries out corresponding Flame Image Process.View data after the processing will output to a CRT by the VGA interface and show.
System is in the process of carrying out Flame Image Process, continually SDRAM is read and write,, do not have influence on the process of Flame Image Process simultaneously again in order to effectively utilize the space of SDRAM, SDRAM is divided into four districts, is respectively command queue district, raw image storage district and two frame buffer zones.Wherein the command queue district is used for the related command that memory image is handled; The raw image storage district is used to store original texture image; Two frame buffer zones then are not influence each other and two buffer zones opening up for the normal demonstration that guarantees image and two processes of treatment of picture.Wherein, buffer zone 1 is used to deposit the image of current demonstration, is called prospect, and buffer zone 2 is used to deposit the image of handling back (to be shown), is called background.In addition, after the space of prospect and background is obtaining flip commands, exchange, thereby reach the effect that image is changed.As seen the method for this double buffering has not only improved the reliability that image shows, and has improved the validity of Flame Image Process.
System in the flow process of carrying out a Flame Image Process as shown in Figure 3, its step is as follows:
(step 301) system powers on, master controller and the configuration of finishing based on the image processing IP core of Wishbone bus separately.After finishing configuration, described IP kernel sends configuration and finishes signal; Master controller resets to described IP kernel after receiving this signal.
(step 302) master controller will carry out initialization to the configuration register of IP kernel internal module.
(step 303) master controller arrives SDRAM with pending image data storage.Treat that the view data transmission finishes, master controller stores image processing command into SDRAM.
(step 304) described IP kernel reads image processing command and the data of SDRAM, carries out command analysis, and according to the command process view data.
Image after (step 305) will be handled by the VGA interface is delivered to display and is shown.Return step 303 then, proceed Flame Image Process next time.
In a word, those skilled in the art can be to the various changes of carrying out based on the image processing IP core of Wishbone bus of the present invention and distortion and is not broken away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1, a kind of image processing IP core based on the Wishbone bus is characterized in that: it mainly comprises Host Controler Interface module, SDRAM control module, command interpretation module, display control module and bus arbitration module; Described each module is all passed through the Wishbone interface, adopts the mutual contact mode of shared bus, realizes the connection of each module and the exchange of data.
2, the image processing IP core based on the Wishbone bus according to claim 1, it is characterized in that: described Host Controler Interface module, SDRAM control module, command interpretation module, display control module all have the Wishbone bus interface, connect in the shared bus mode in the Wishbone standard, they all must be filed an application to the bus arbitration module when the contention bus right to use.
3, the image processing IP core based on the Wishbone bus according to claim 2, it is characterized in that: described bus arbitration module to the bus request of Host Controler Interface module, SDRAM control module, command interpretation module and display control module sort, the distribution bus right to use, solve the mutual competitions and conflicts of bus master, realize the interconnection of IP kernel on the sheet resource.
4, according to each described image processing IP core among the claim 1-3 based on the Wishbone bus, it is characterized in that: described Host Controler Interface module is mainly finished the data communication of external piloting control system device and external piloting control system device, and its communication mode adopts asynchronous handshake mode or dma mode.。
5, the image processing IP core based on the Wishbone bus according to claim 4 is characterized in that: described Host Controler Interface module comprises configuration register, command register and data register;
Described configuration register is used for store configuration information to finish the parameter setting of SDRAM control module, command interpretation module and display control module;
Described command register is used for the memory image processing command so that store SDRAM into or read to external piloting control system device;
Described data register is used to store image transmitted data so that store SDRAM into or read to external piloting control system device.
6, according to each described image processing IP core based on the Wishbone bus among the claim 1-3, it is characterized in that: described SDRAM control module is provided with sdram controller, configuration register SLAVE, address register SDRAM and inputoutput buffer FIFO;
Described sdram controller control configuration register SLAVE, address register SDRAM and FIFO, sdram controller can be finished read-write, precharge, self-refresh and the mode register FIFO load operation of SDRAM according to the parameter that the value of configuration register is set SDRAM.
7, the image processing IP core based on the Wishbone bus according to claim 6, it is characterized in that: described SDRAM is divided into command queue district, raw image storage district and frame buffer zone.
8, according to each described image processing IP core based on the Wishbone bus among the claim 1-3, it is characterized in that: described command interpretation module is provided with Wishbone Master module, image processor and configuration register;
Described configuration register is used to be provided with the base address that image processing command and view data are deposited, so that Wishbone Master finishes reading of order and image; Image processor is responsible for reading related command and explanation from the order buffer area, finishes the processing operation of required image at last; By Wishbone Master view data is deposited back SDRAM for the display control module reading displayed again after disposing.
9, according to each described image processing IP core based on the Wishbone bus among the claim 1-3, it is characterized in that: described display control module is provided with VGA main equipment and groups of configuration registers; The base address that described VGA main equipment is deposited in SDRAM according to controlled variable such as the line frequency that obtains from groups of configuration registers, field frequency and view data sends view data to DAC with correct way and handles and be converted to simulating signal and output to display and show.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910041725A CN101615287A (en) | 2009-08-06 | 2009-08-06 | A kind of image processing IP core based on the Wishbone bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910041725A CN101615287A (en) | 2009-08-06 | 2009-08-06 | A kind of image processing IP core based on the Wishbone bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101615287A true CN101615287A (en) | 2009-12-30 |
Family
ID=41494912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910041725A Pending CN101615287A (en) | 2009-08-06 | 2009-08-06 | A kind of image processing IP core based on the Wishbone bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101615287A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882419A (en) * | 2010-06-03 | 2010-11-10 | 大连海事大学 | Color gamut amending IP core of LED display screen video signal and method thereof |
| CN102036038A (en) * | 2011-01-07 | 2011-04-27 | 天津天地伟业数码科技有限公司 | Multi-channel OSD video superposition controller |
| CN102890667A (en) * | 2012-09-17 | 2013-01-23 | 广州英码信息科技有限公司 | Device and method for processing wiegand data |
| CN104915301A (en) * | 2015-06-01 | 2015-09-16 | 浪潮集团有限公司 | 8051 singlechip-based plug-in RAM (random access memory) interface data access system |
| CN109634707A (en) * | 2018-12-21 | 2019-04-16 | 深圳开立生物医疗科技股份有限公司 | Ultrasonic system GUI display method and device |
| CN110287136A (en) * | 2019-05-29 | 2019-09-27 | 广东天波信息技术股份有限公司 | Equipment, method and the storage medium of a variety of Wiegand signal mechanism can be compatible with |
| CN110704345A (en) * | 2019-09-06 | 2020-01-17 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | PCIE-based high-speed multi-serial-port card system and sending and receiving methods thereof |
| CN111639046A (en) * | 2020-05-11 | 2020-09-08 | 中国科学院国家空间科学中心 | System and method for caching and transmitting data of far ultraviolet aurora imager in real time |
| CN113419988A (en) * | 2021-08-25 | 2021-09-21 | 杭州博雅鸿图视频技术有限公司 | Heterogeneous multi-core data transmission method, device, equipment and storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2886683Y (en) * | 2006-04-17 | 2007-04-04 | 四川大学 | SoC chip with multimedia and network processing function |
-
2009
- 2009-08-06 CN CN200910041725A patent/CN101615287A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2886683Y (en) * | 2006-04-17 | 2007-04-04 | 四川大学 | SoC chip with multimedia and network processing function |
Non-Patent Citations (3)
| Title |
|---|
| 徐涛等: "MIPS整合芯片的FPGA设计与实现", 《高技术通讯》 * |
| 林晓敏等: "基于Wishbone-PCI核的红外图像实时处理仿真平台", 《半导体光电》 * |
| 邱志明: "基于ARM和FPGA的图像处理系统研究", 《万方数据知识服务平台》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882419A (en) * | 2010-06-03 | 2010-11-10 | 大连海事大学 | Color gamut amending IP core of LED display screen video signal and method thereof |
| CN101882419B (en) * | 2010-06-03 | 2012-01-11 | 大连海事大学 | Color gamut amending IP core of LED display screen video signal and method thereof |
| CN102036038A (en) * | 2011-01-07 | 2011-04-27 | 天津天地伟业数码科技有限公司 | Multi-channel OSD video superposition controller |
| CN102890667A (en) * | 2012-09-17 | 2013-01-23 | 广州英码信息科技有限公司 | Device and method for processing wiegand data |
| CN104915301A (en) * | 2015-06-01 | 2015-09-16 | 浪潮集团有限公司 | 8051 singlechip-based plug-in RAM (random access memory) interface data access system |
| CN104915301B (en) * | 2015-06-01 | 2017-11-10 | 浪潮集团有限公司 | A kind of plug-in RAM Interface data access system based on 8051 single-chip microcomputers |
| CN109634707A (en) * | 2018-12-21 | 2019-04-16 | 深圳开立生物医疗科技股份有限公司 | Ultrasonic system GUI display method and device |
| CN110287136A (en) * | 2019-05-29 | 2019-09-27 | 广东天波信息技术股份有限公司 | Equipment, method and the storage medium of a variety of Wiegand signal mechanism can be compatible with |
| CN110704345A (en) * | 2019-09-06 | 2020-01-17 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | PCIE-based high-speed multi-serial-port card system and sending and receiving methods thereof |
| CN111639046A (en) * | 2020-05-11 | 2020-09-08 | 中国科学院国家空间科学中心 | System and method for caching and transmitting data of far ultraviolet aurora imager in real time |
| CN113419988A (en) * | 2021-08-25 | 2021-09-21 | 杭州博雅鸿图视频技术有限公司 | Heterogeneous multi-core data transmission method, device, equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101615287A (en) | A kind of image processing IP core based on the Wishbone bus | |
| CN104881666B (en) | A kind of real-time bianry image connected component labeling implementation method based on FPGA | |
| US9824037B2 (en) | Memory mapping in a processor having multiple programmable units | |
| TW448363B (en) | High speed processor system with bus arbitration | |
| US10055807B2 (en) | Hardware architecture for acceleration of computer vision and imaging processing | |
| TW201918883A (en) | High bandwidth memory system and logic die | |
| JP5296061B2 (en) | Memory barrier directed to the device | |
| US20060177122A1 (en) | Method and apparatus for particle manipulation using graphics processing | |
| CN107392309A (en) | A kind of general fixed-point number neutral net convolution accelerator hardware structure based on FPGA | |
| CN103399833B (en) | Technology for transmitting interruption in computer systems | |
| CN103221937A (en) | Load/store circuitry for a processing cluster | |
| CN103714026B (en) | A kind of memory access method supporting former address data exchange and device | |
| JPH09251288A (en) | Computer system, graphics processor, instruction pre-fetch unit and method for pre-fetching operational code instruction | |
| CN108650136A (en) | A kind of design method of master/slave station card that realizing the communication of Powerlink industry real-time ethernets | |
| CN102314400B (en) | Method and device for dispersing converged DMA (Direct Memory Access) | |
| CN107077186A (en) | Low-power is calculated as picture | |
| CN106886690A (en) | It is a kind of that the heterogeneous platform understood is calculated towards gene data | |
| CN109711003A (en) | One kind is towards GPU graphics chip pipeline unit functional simulation method and platform | |
| CN109710229A (en) | One kind is towards GPU graphics chip pipeline unit framework verification method and platform | |
| CN103218343A (en) | Inter-multiprocessor data communication circuit adopting data driving mechanism | |
| CN101236488B (en) | Synergic distribution type processing method and device | |
| US20220224605A1 (en) | Simulating network flow control | |
| CN114168503A (en) | Interface IP core control method, interface IP core, device and medium | |
| Hussain | Memory resources aware run-time automated scheduling policy for multi-core systems | |
| CN103699517A (en) | 1-D/2-D hybrid architecture FFT (Fast Fourier Transform) processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20091230 |