CN103714026B - A kind of memory access method supporting former address data exchange and device - Google Patents
A kind of memory access method supporting former address data exchange and device Download PDFInfo
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- CN103714026B CN103714026B CN201410015782.6A CN201410015782A CN103714026B CN 103714026 B CN103714026 B CN 103714026B CN 201410015782 A CN201410015782 A CN 201410015782A CN 103714026 B CN103714026 B CN 103714026B
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Abstract
The invention discloses a kind of memory access method supporting former address data exchange and device, the read-write mode depositor of processor core is first all set to data exchange mode by the method, then from local storage, read data and store in transmission FIFO, again to on-chip interconnection network request for arbitration data exchange request, if agreeing to and distributing the data channel right to use, the data sent in FIFO are exported the reception data unwrapper unit to second and first processor core, and unpack storage to receiving in FIFO, read the data in local storage by Read Controller again and store in transmission FIFO, finally by writing controller by the local storage of the data write processor core received in FIFO.The present invention can not open up extra buffer, directly carries out internuclear data exchange operation in former address data memory, improves the performance of processor and the utilization rate of memorizer, has the advantage that performance is good, low in energy consumption, utilization rate is high, processing speed is fast.
Description
Technical field
The present invention relates to multi-core microprocessor field, particularly relate to a kind of memory access method supporting former address data exchange and device.
Background technology
Polycaryon processor generally includes internet, external memory storage and the interface of other chips on multiple same or different process core, sheet, and wherein on-chip interconnection network generally uses bus, traffic flow prediction or network-on-chip to carry out being connected and communicating to each processor core and interface.Each processor core generally comprises the internuclear memory access apparatus (or be direct memory access controller, DMA) of program storage, fetching and instruction decoding unit, performance element, local data memory and this locality.Local DMA is connected with the instruction decoding unit of processor, local data storage and on-chip interconnection network.Instruction decoding unit completes the decoding of instruction, and by configuring bus, decoding results such as performing the size of which kind of command operating (reading or write operation), source data address, purpose data address and moving data is sent to DMA device.DMA device accepts the operational order that decoding unit is sent, and is responsible for local data memory and the data storage of other processor cores on sheet, and the accessing operation of data between processor external memory storage.Each processor core is transferred a small block data in the middle of external memory storage and is processed, and may need the data that other processor cores produce in processing procedure, and it carries out data-moving operation by local DMA device.Traditional DMA typically has two passages, a write access and a read channel.During the moving of data, above-mentioned two passage can not be transmitted simultaneously, therefore in performing multicomputer system during the exchange of internuclear data, first in the middle of the local storage of processor core A and processor core B, open up the interim memory buffer of the size such as a piece respectively, when A produces the desired data of B, processor core A starts local DMA device and corresponding data is passed in the middle of the interim memory buffer of processor core B by on-chip interconnection network.If processor core B also creates the data required for processor core A, processor core B has to wait for processor core A and just beginning through its local DMA device after data end of transmission, corresponding data is transferred in the middle of the interim memory buffer of processor core A by on-chip interconnection network.This processor core A and B data exchange serial perform, postpone big, to reduce processor performance, cause on-chip memory utilization rate to reduce simultaneously, add the power consumption of processor.
Summary of the invention
The technical problem to be solved in the present invention is that the technical problem existed for prior art, and the present invention provides memory access method and the device of the support former address data exchange that a kind of performance is good, low in energy consumption, utilization rate is high, processing speed is fast.
For solve above-mentioned technical problem, the present invention by the following technical solutions:
A kind of memory access method supporting former address data exchange, comprises the following steps:
1) the local read-write mode depositor of first processor core and the second processor core is set to data exchange mode, from the local storage of first processor core and the second processor core, read data by the data read-write control device of first processor core and the second processor core, and data are respectively stored in the transmission FIFO of first processor core and the second processor core.The data packetization unit that sends of first processor core and the second processor core reads data respectively from the transmission FIFO of described first processor core and the second processor core, and respectively according to the read-write mode depositor of first processor core and the second processor core, the value of destination address register to on-chip interconnection network arbitration unit application first processor core to the second processor core, the data channel of the second processor core to first processor core；
2) described on-chip interconnection network arbitration unit receives described first processor core and time the second processor core carries out the channel request of data exchange mode at the same time, it is respectively allocated the first processor core data channel to the second processor core to first processor core, distributes second processor core data channel to first processor core to the second processor core；
3) exported by data channel after the data in the transmission FIFO of first processor core described in step 1) and the second processor core are packed by the local DMA device of described first processor core and the second processor core respectively and accept data unwrapper unit to the second processor core and first processor core, described reception data unwrapper unit carry out described packet unpacking and store in the reception FIFO of first processor core and the second processor core；
4) it is written and read controlling to the data sent and receive respectively by core this locality DMA device of first processor core described in step 3) and the second processor core, described data read-write control device is preferential to read operation, read the data of local storage by Read Controller, and store data in transmission FIFO；
5) when in the local storage of described first processor core and the second processor core, write address is less than reading address, writing controller starts to be respectively written in the middle of the local storage of described first processor core and the second processor core the data in the reception FIFO described in step 3), completes former address data exchange.
The further of memory access method as the support former address data exchange of the present invention is improved:
Described step 2) in, described transmission data packetization unit according to the destination address of data and read-write mode to first processor core described in on-chip interconnection network arbitration unit application to the data channel of the second processor core, if obtaining the right to use of passage, then first read-write mode information, source address information, destination address information and transmission byte number information are made up of described transmission data packetization unit data packet head and are sent to the second processor core, followed by retransmiting data to described second processor core.
In described step 3), the read-write mode information of described packet, destination address information and reception byte number information are respectively stored in and receive reading and writing data mode register, receives data destination address register and receive in the middle of byte number depositor by described reception data unwrapper unit, then receive and data are unpacked to store and arrive in the middle of described reception FIFO.
Technical solution of the present invention additionally provides a kind of memory access apparatus supporting former address data exchange, including data read-write control device, sends FIFO, reception FIFO, transmission data packetization unit and receives data unwrapper unit；
Described data read-write control device includes read-write mode depositor, source address register, destination address register, transmission byte number depositor, Read Controller, writing controller and address is compared and alternative pack, and described data read-write control device reads data in the middle of described reception FIFO according to the order of FIFO and sends the data to described local storage；
Described transmission FIFO is connected with described data read-write control device, transmission data packetization unit, receives the data exported from described local storage；
Described reception FIFO is connected with described reception data unwrapper unit, data read-write control device, receives the data from the output of described data unwrapper unit；
Described transmission data packetization unit includes a data packing state machine and a transmission data counter, described transmission data packetization unit is connected with described transmission FIFO, data read-write control device and on-chip interconnection network, and described transmission data packetization unit presses the order of FIFO from sending reading data in the middle of FIFO；
Described reception data unwrapper unit includes that receiving byte number depositor, reception data destination register, reception data WriteMode depositor, reception data counter and data unpacks state machine, described reception data unwrapper unit and reception FIFO, data read-write control device, and on-chip interconnection network is connected, the packet received is unpacked.
The further of memory access apparatus as the support former address data exchange of the present invention is improved:
The a width of W of data bus bit between described memory access apparatus and local storage is preferably at least twice a width of w-byte of data bus bit of described memory access apparatus and on-chip interconnection network.
Configuration bus, Read Controller and transmission data packetization unit and reception data unwrapper unit that described read-write mode depositor inputs with outside are connected, described read-write mode depositor accepts described configuration bus and reads the assignment operation of configuration bus from the strange land receiving data unwrapper unit, and the data value of depositor is exported described Read Controller and transmission data packetization unit by holding wire, the most also accept the clear operation of described Read Controller；
Configuration bus, Read Controller, transmission data packetization unit and reception data unwrapper unit that described source address register inputs with outside are connected, described source address register accepts configure bus and read the assignment operation of configuration bus from the strange land receiving data unwrapper unit, and the data value of depositor is exported Read Controller and transmission data packetization unit by holding wire.
Configuration bus, transmission data packetization unit and reception data unwrapper unit that described destination address register inputs with outside are connected, described destination address register accepts configuration bus and reads the assignment operation of configuration bus from the strange land receiving data unwrapper unit, and the data value of depositor is directly output to send data packetization unit by holding wire；
Configuration bus, Read Controller, transmission data packetization unit and reception data unwrapper unit that described transmission byte number depositor inputs with outside are connected, described transmission byte number depositor accepts configure bus and read the assignment operation of configuration bus from the strange land receiving data unwrapper unit, and the data value of depositor is exported Read Controller and transmission data packetization unit by holding wire.
Described Read Controller includes read states machine, read counter and reads address adder, compare with described read-write mode depositor, source address register, transmission byte number depositor, address and address choice parts and writing controller are connected, the value of described read counter is added with the value of source address register and obtains reading address by described reading address adder, and described reading address is exported to address compare and address choice parts, described Read Controller carries out the read access operation of local storage according to the pattern of read-write mode depositor；
Described writing controller includes write state machine, writes enumerator and write address adder, with read-write mode depositor, receive FIFO, receive data unwrapper unit, address and compare and address choice parts and Read Controller are connected, the reception data destination address inputted from described reception data unwrapper unit is added with the value writing enumerator and obtains write address by described write address adder, and the value of described write address exports address compares and address choice parts；
Described address is compared and is connected with described Read Controller, writing controller, reception data unwrapper unit and read-write mode depositor with address choice parts, receive the output of described Read Controller reads address signal and the writing address signal of writing controller output, reading address and write address are compared, and comparative result is returned to described writing controller, according to from the reception data WriteMode of described reception data unwrapper unit output and the value of read-write mode depositor, described reading address and write address are operated simultaneously.
Described transmission data packetization unit is connected with on-chip interconnection network and is connected, data counter is sent including a data packing state machine and one, in the middle of described transmission FIFO, data are read by the order of FIFO, and the data including a packet are sent to on-chip interconnection network, described packet includes read-write mode, destination address, source address and four kinds of information of transmission byte number.
Described reception byte number depositor, reception data destination address register, the value of reception reading and writing data mode register are directly output to described data read-write control device by holding wire.
Compared with prior art, it is an advantage of the current invention that:
1, the present invention directly supports that two-way internuclear independent data is moved, and decreases data communication expense, thus improves the performance of processor.
2, the present invention is not in the case of opening up extra buffer, directly carries out internuclear data exchange operation in former address data memory space, not only decreases data communication expense between multinuclear, and improves the utilization rate of memorizer.
3, the present invention is in the middle of internuclear data exchange operation, on-chip interconnection network arbitration unit keep synchronization to carry out the data exchange operation between two processor cores, further reduce extra data syn-chronization expense.
Accompanying drawing explanation
Fig. 1 is the memory access method schematic flow sheet of the support former address data exchange of the embodiment of the present invention.
Fig. 2 is the memory access apparatus of embodiment of the present invention position in the middle of polycaryon processor and interface diagram.
Fig. 3 is the memory access apparatus schematic diagram of the support former address data exchange of the embodiment of the present invention.
Fig. 4 is the data read-write control device schematic diagram in the memory access apparatus of the embodiment of the present invention.
Fig. 5 is the state transition graph of the inside read states machine of the DMA device of the embodiment of the present invention.
Fig. 6 is the state transition graph of the inside write state machine of the DMA device of the embodiment of the present invention.
Fig. 7 is the schematic diagram sending data packetization unit of the DMA device of the embodiment of the present invention.
Fig. 8 is the state transition graph of the data packing state machine of the DMA device of the embodiment of the present invention.
Fig. 9 is the reception data packetization unit schematic diagram of the DMA device of the embodiment of the present invention.
Figure 10 is the state transition graph that the data of the DMA device of the embodiment of the present invention unpack state machine.
Figure 11 is the schematic diagram using the DMA device of the embodiment of the present invention to carry out data exchange.
Marginal data: 1, data read-write control device；2, FIFO is sent；3, FIFO is received；4, data packetization unit is sent；5, data unwrapper unit is received；11, Read Controller；12, writing controller；13, read-write mode depositor；14, source address register；15, destination address register；16, transmission byte number depositor；17, address is compared and address choice parts；41, data packing state machine；42, data counter is sent；51, byte number depositor is received；52, data destination address register is received；53, data source address depositor is received；54, reading and writing data mode register is received；55, data unpack state machine；56, data counter is received；111, read states machine；112, read counter；113, address adder is read；121, write state machine；122, enumerator is write；123, write address adder.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 shows the access method steps flow chart carrying out former address data exchange in the memorizer of the embodiment of the present invention.Wherein first processor core and the second processor core represent any two in multiple processor core respectively.In the present embodiment, the quantity of processor core is four, and first processor core is processor core A, and the second processor core is processor core B.As it is shown in figure 1, the enforcement step carrying out the access method of former address data exchange in the memorizer of the embodiment of the present invention is as follows:
1) respectively the read-write mode depositor 13 of processor core A and processor core B is set to data exchange mode, from the local storage of processor core A and processor core B, data are read by the data read-write control device 1 of processor core A and processor core B, and data are respectively stored in the transmission FIFO 2 of processor core A and processor core B, the transmission data packetization unit 4 of processor core A and processor core B reads data from respective transmission FIFO 2, and to the exchange request of on-chip interconnection network arbitration unit request for data；
2), when on-chip interconnection network arbitrates the data exchange request simultaneously receiving processor core A and processor core B, agree to its data exchange request, and distribute the data channel right to use to processor core A and processor core B simultaneously.
3) data sent in step 1) in FIFO2 are exported respectively to the reception data unwrapper unit 5 of processor core B and processor core A by the local DMA device of processor core A and processor core B by data channel, are received by receiving data unwrapper unit 5 and data are unpacked in the reception FIFO3 being respectively stored into processor core B and processor core A.
4) in step 3), the data sent and receive are written and read controlling by the local DMA device of processor core A and processor core B, data read-write control device 1 priority treatment read operation, read the data in local storage by Read Controller 11, and store data in transmission FIFO2.
5) in the local storage of processor core A and processor core B, write address is less than when reading address, and writing controller 12 starts to be respectively written in the local storage of processor core A and processor core B the data received in FIFO3 in step 3), completes former address data exchange.
In the present embodiment, send data packetization unit 4 according to the destination address of data and read-write mode to the data channel of on-chip interconnection network arbitration unit application processor core A to processor core B, if obtaining the right to use of passage, then first by transmission data packetization unit 4 read-write mode information, source address information, destination address information and transmission byte number information are formed data packet head and is sent to processor core B, followed by retransmit data to processor core B.
In the present embodiment, receive data unwrapper unit 5 the read-write mode information of data packet head, destination address information and reception byte number information to be respectively stored in reception reading and writing data mode register 54, receives data destination address register 15 and receive in the middle of byte number depositor 51, then receive and storage of data being packed is to receiving in the middle of FIFO3.
Fig. 2 shows the memory access apparatus embodiment of the present invention in four core processors.As seen from the figure, each processor core is connected by on-chip interconnection network, and each processor core includes a program storage, a fetching and decoding unit, a performance element, a data storage and the memory access apparatus of a present invention.In the present embodiment, memory access apparatus is connected with instruction decoding unit, local storage and the on-chip interconnection network of processor core, receiving the configuration information that instruction decoding unit sends, the backward instruction decoding unit completing to operate accordingly returns an interrupt signal.Data bus bit a width of W byte between memory access apparatus and local storage in the present invention, a width of w-byte with the data bus bit of on-chip interconnection network, wherein W=n*w, n are greater than or equal to the positive integer of 2.Native processor is accessed by memory access apparatus and moves the local memory data of other processor cores.
As it is shown on figure 3, the memory access apparatus of the present invention includes data read-write control device 1, sends FIFO2, reception FIFO3, transmission data packetization unit 4 and receive data unwrapper unit 5.Wherein data read-write control device 1 is connected with transmission FIFO2, reception FIFO3, transmission data packetization unit 4 and reception data unwrapper unit 5 respectively, control the read and write operation of data, and preferentially enable read access operation, when only not starting when read operation or send FIFO2 for expiring, enable number of write access operations；Data read-write control device 1 reads data in the middle of reception FIFO3 according to the order of FIFO and sends the data to local storage, takies port memory to timesharing when controlling read and write operation；Sending FIFO2 to be connected with data read-write control device 1, transmission data packetization unit 4, its inputoutput data bit wide is W byte, receives the data from local storage output；Receive FIFO3 and receive data unwrapper unit 5, data read-write control device 1 is connected, and its inputoutput data bit wide is W byte, receives from the data receiving data unwrapper unit 5 output；Send data packetization unit 4 and send FIFO2, data read-write control device 1 and on-chip interconnection network are connected, sending a width of w the byte of data bus bit that data packetization unit 4 is connected with on-chip interconnection network, the packet being sent to on-chip interconnection network includes read-write mode, destination address, source address and transmission four kinds of information of byte number and other relevant informations；Receiving data unwrapper unit 5 and be connected with receiving FIFO3, data read-write control device 1, and on-chip interconnection network, its operation is contrary with sending data packetization unit 4, unpacks the packet received.
As shown in Figure 4, the data read-write control device 1 in memory access apparatus of the present invention includes that read-write mode depositor 13, source address register 14, destination address register 15, transmission byte number depositor 16, Read Controller 11, writing controller 12 and address are compared and address choice parts 17.When system reset enables effective, all of depositor is endowed null value, and read states machine 111 enters idle condition.When having the read-write operation to local storage at the same time, preferentially enable read operation.
In the present embodiment, read-write mode depositor 13 and the outside configuration bus inputted, Read Controller 11, and transmission data packetization unit 4 is connected with receiving data unwrapper unit 5, it accepts configuration bus and reads the assignment operation of configuration bus from the strange land receiving data unwrapper unit 5, its data value exported Read Controller 11 by holding wire and sends data packetization unit 4, reading while write mode register 13 and also accept the clear operation of Read Controller 11.By differently configured value, read-write mode depositor 13 has a Three models: local read data pattern, strange land read data pattern and data exchange mode；
In the present embodiment, source address register 14 and the outside configuration bus inputted, Read Controller 11, send data packetization unit 4 and be connected with receiving data unwrapper unit 5, accept configuration bus and read the assignment of configuration bus from the strange land receiving data unwrapper unit 5, its data value exported Read Controller 11 by holding wire and sends data packetization unit 4；
In the present embodiment, configuration bus, transmission data packetization unit 4 and reception data unwrapper unit 5 that destination address register 15 inputs with outside are connected, accept configuration bus and read the assignment of configuration bus from the strange land receiving data unwrapper unit 5, and being directly output to send data packetization unit 4 by holding wire by its data value；
In the present embodiment, configuration bus, Read Controller 11, transmission data packetization unit 4 and reception data unwrapper unit 5 that transmission byte number depositor 16 inputs with outside are connected, accept configuration bus and read the assignment of configuration bus from the strange land receiving data unwrapper unit 5, its data value exported Read Controller 11 by holding wire and sends data packetization unit 4；As shown in Figure 3, Read Controller 11 and read-write mode depositor 13, source address register 14, transmission byte number depositor 16, address compare and address choice parts 17 and writing controller 12 are connected, and the read access carrying out local storage according to the value of read-write mode depositor 13 operates.
In the present embodiment, Read Controller 11 includes read states machine 111, read counter 112 and reading address adder 113, wherein read address adder 113 carry out being added with the value of read counter 112 by the value of source address register 14 obtain read address, and export read address compare to address and address choice parts 17.Read states machine 111, by reading idle condition, is read data mode, is run through waiting state, writes complete four state compositions of waiting state, and its transformation process is as shown in Figure 5.When system reset enables effective, read states machine 111 enters reads idle condition, and read counter 112 resets, and all outputs enable invalidating signal.Read states machine 111 is in reading idle pulley, if the value of read-write mode depositor 13 is local reading mode or data exchange mode, read states machine 111 enters reads data mode, puts the busy enable of read states machine 111 effectively, and address is read in output, and read counter 112 adds W.Read states machine 111 is in reading data mode, if it is invalid to send the non-full enable of FIFO2, then suspends read operation, puts all output enables invalid.When the value of read counter 112 is equal to the value of transmission byte number depositor 16, read operation completes, the enable invalidating signal of all outputs.If being now local reading mode, or data exchange mode, and write data to complete to enable effectively, then the next clock cycle enters and runs through waiting state, read states machine 111 is in and runs through waiting state, if data have been packed when enabling effective, the next clock cycle proceeds to read idle condition, read counter 112 resets, and it is invalid that all outputs enable；If being now data exchange mode, and data have been packed and have been enabled effectively, then enter and write complete waiting state.Read states machine 111 is in and writes complete waiting state, if writing data when completing to enable effective, read states machine 111 enters reads idle condition, and read counter 112 clear 0, it is invalid that all outputs enable；
In the present embodiment, writing controller 12 and read-write mode depositor 13, receive FIFO3, receive data unwrapper unit 5, address is compared and address choice parts 17 and Read Controller 11 are connected, carries out write operation according to from the value receiving the reception data WriteMode signal that data unwrapper unit 5 exports.Writing controller 12 includes write state machine 121, write enumerator 122 and write address adder 123, wherein write address adder 123 will be added with the value writing enumerator 122 and obtains write address from receiving the value of reception data destination address signal that data unwrapper unit 5 exports, and write address exports address compares and address choice parts 17.Write state machine 121 is by writing idle condition and writing data mode and form, and its transformation process is as shown in Figure 6.When system reset enables effective, write state machine 121 enters and writes idle condition, writes enumerator 122 and reset, and all outputs enable invalidating signal.Write state machine 121 is in writes idle condition, if reception FIFO3 non-NULL enables effectively, then next cycle enters and writes data mode, if now the busy enable of read states machine 111 is invalid, then writes enumerator 122 and adds W, write address output, carry out memory write operation.Write state machine 121 is in writes data mode, if received, FIFO3 non-NULL enable is invalid or the busy enable of read states machine 111 is effective, then suspend write operation, and all outputs enable invalidating signal.When receiving FIFO3 non-NULL enable, effectively and read states machine 111 hurries when enabling invalid, continues write operation.Until write the value of enumerator 122 equal to from the reception data word joint number receiving data unwrapper unit 5 output time, enter and write idle condition, put and write data and complete to enable effectively, write enumerator 122 and reset, other outputs enable invalidating signals；As shown in Figure 4, address is compared and is connected with Read Controller 11, writing controller 12, reception data unwrapper unit 5 and read-write mode depositor 13 with address choice parts 17, complete reading address and the comparison of write address and selecting output function, and comparative result is returned to writing controller 12.According to the value from the reception data WriteMode and read-write mode depositor 13 receiving data unwrapper unit 5 input, reading address and write address are operated simultaneously.When the busy enable of read states machine 111 is invalid, and in the case of the value of read-write mode depositor 13 and reception data WriteMode are all data exchange mode, and write address is less than reading address, selection write address also exports and arrives external memory address EBI；When the busy enable of read states machine 111 is invalid, and when receiving data WriteMode for local read data pattern, select write address also to export and arrive external memory address EBI.Remaining situation operates according to the busy signal that enables of read states machine 111.Enabling effectively if read states machine 111 hurries, select output reading address to memory address bus port, otherwise putting memory address bus is 0.
As it is shown in fig. 7, the transmission data packetization unit 4 in memory access apparatus of the present invention is connected with sending FIFO2, data read-write control device 1 and on-chip interconnection network, it includes a data packing state machine 41 and a transmission data counter 42.Send a width of w the byte of data bus bit that data packetization unit 4 is connected with on-chip interconnection network, the data being sent to on-chip interconnection network include a data packet head and data immediately after, and wherein data packet head includes read-write mode, destination address, source address and transmission four kinds of information of byte number.
In the present embodiment, data packing state machine 41, by idle, bus application, sends packet header and sends four states of data, and its State Transferring is as shown in Figure 8.When system reset enables effective, data packing state machine 41 enters idle condition, and it is invalid that all outputs enable, and sends data counter 42 and resets.Data packing state machine 41 is in idle condition, if the read-write mode depositor in the middle of data read-write control device 1 13 is local reading data, data exchange or strange land read data pattern, data packing state machine 41 enters bus application status, puts packet transmission request signal effective.Data packing state machine 41 is in bus application status, if packet sends enable, signal is effective, then enter and send packet header state, start to send header packet information: the information in the middle of transmission byte number depositor 16, destination address register 15, source address register 14 and read-write mode depositor 13 reading in data read-write control device 1 is packed, it is sent to send on data packet bus, and enables transmission packet useful signal.Data packing state machine 41 is in transmission packet state, if the value of read-write mode depositor 13 is strange land read data pattern, then proceeds to idle condition after having sent packet information, put data pack enable effectively, it is invalid that other export enable；If the value of read-write mode depositor 13 is local reading data or data exchange mode, then proceed to send data mode after having sent packet information, if now sending FIFO2 is non-NULL, so read the data sending FIFO2, data by address order from small to large is split into the small data of multiple w-byte and is sent on data packet bus, often send w-byte data, send data counter 42 and add w.During until sending the value of data counter 42 equal to transmission byte number, this secondary data pack, put data pack enable effectively, other output enables are invalid, and state machine proceeds to idle condition, transmission data counter 42 clear 0.
As shown in Figure 9, reception data unwrapper unit 5 in memory access apparatus of the present invention is connected with receiving FIFO3, data read-write control device 1 and on-chip interconnection network, its operation principle is contrary with sending data packetization unit 4, packet is received from bus, and the information of data is unpacked, data storage is receiving in the middle of FIFO3.In the present embodiment, reception data unwrapper unit 5 includes that receiving byte number depositor 51, reception data destination address register 52, reception data source address depositor 53, reception reading and writing data mode register 54, reception data counter 56 and data unpacks state machine 55.Wherein, reception byte number depositor 51, reception data destination address register 52, the value of reception reading and writing data mode register 54 are directly output to data read-write control device 1 by holding wire.
In the present embodiment, data unpack state machine 55 and include the free time, agree to that packet receives request, reception packet header, reception data and wait and writes complete five states, and its State Transferring is as shown in Figure 10.When system reset enables effective, data unpack state machine 55 and enter idle condition, receive data counter 56 and reset, and all outputs enable invalidating signal.Data unpack state machine 55 and are in idle condition, if packet receives request effectively, and judge to receive the type of request.If strange land read request, check that the read-write mode signals sent from data read-write control device 1 is now idle (the most whether equal to 0).If idle, then enter and receive data packet head state, put packet and receive and enable effectively, otherwise put packet and receive and enable invalid, wait that the read operation of data read-write control device 1 completes；If the type receiving request is local reading data or data exchange mode, puts packet reception and enable effectively, enter reception data packet head state.Data unpack state machine 55 and are in reception data packet head state, start reception and decode data packet header information: if strange land read data request, the source address information then packet included, destination address information, transmission byte number information, and read-write mode information is respectively written into the destination address register 15 of data read-write control device 1, source address register 14, transmission byte number depositor 16 and read-write mode depositor 13 by strange land reading configuration bus, after writing, data unpack state machine 55 and turn such as idle condition in the next clock cycle；If local read data pattern or data exchange mode, the destination address information then packet included, transmission byte number information, and read-write mode information is respectively written into reception data destination address register 52, receives byte number depositor 51 and receive reading and writing data mode register 54, after writing, data unpack state machine 55 and enter reception data mode, start to receive data.Often receiving w-byte data, receive data counter 56 and add w, until receiving the value of data counter 56 equal to the value receiving byte number depositor 51, data unpack state machine 55 and enter wait and write complete state.Data unpack state machine 55 and are in wait and write complete state, complete to enable effectively if writing data, then data unpack state machine 55 and enter idle condition, and putting reception data calculator is 0, and it is invalid that all outputs enable.
Figure 11 shows that the memory access apparatus using the present invention carries out internuclear data exchange operation process.The memory access apparatus of the present invention passes through the transmission FIFO2 within processor core A and the reception FIFO3 within processor core B, reception FIFO3 within processor core A and the transmission FIFO2 within processor core B stores data block B1 and a part of data to be moved of B3 respectively, in the local memory access device of processor core A and processor core B, data exchange is the most directly carried out at former address data memory, data read-write control device 1 only just can write the data to local storage at write address less than in the case of reading address, ensure that each data write-after-read in the middle of memorizer.So can be achieved with exchanging data double-way transmission, both accelerated data signaling rate, thus improve processor performance, make again data exchange be able on former address carry out, improve memorizer utilization rate.
Below being only the preferred embodiment of the present invention, protection scope of the present invention is not limited merely to above-described embodiment, and all technical schemes belonged under thinking of the present invention belong to protection scope of the present invention.It should be pointed out that, for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, should be regarded as protection scope of the present invention.
Claims (10)
1. the memory access method supporting former address data exchange, it is characterised in that comprise the following steps:
null1) the local read-write mode depositor (13) of first processor core and the second processor core is set to data exchange mode，From the local storage of first processor core and the second processor core, data are read by the data read-write control device (1) of described first processor core and the second processor core，And data are respectively stored into the transmission FIFO(2 of first processor core and the second processor core) in，Again by the transmission data packetization unit (4) of first processor core and the second processor core respectively from the transmission FIFO(2 of first processor core and the second processor core) read data，And respectively according to the read-write mode depositor (13) of first processor core and the second processor core、The value of destination address register (15) to on-chip interconnection network arbitration unit application first processor core to the second processor core、Second processor core is to the data channel of first processor core；
2) described on-chip interconnection network arbitration unit receives described first processor core and time the second processor core carries out the channel request of data exchange mode at the same time, it is respectively allocated the first processor core data channel to the second processor core to first processor core, distributes second processor core data channel to first processor core to the second processor core；
3) the local DMA device of described first processor core and the second processor core is respectively by the transmission FIFO(2 of first processor core described in step 1) and the second processor core) in data packing after export to reception data unwrapper unit (5) of the second processor core and first processor core by data channel, described reception data unwrapper unit (5) described packet carries out unpacking and storing the reception FIFO(3 of first processor core and the second processor core) in；
4) it is written and read controlling to the data sent and receive respectively by the local DMA device of first processor core described in step 3) and the second processor core, data read-write control device (1) is preferential to read operation, read the data of local storage by Read Controller (11), and store data into transmission FIFO(2) in；
5) when in the local storage of described first processor core and the second processor core, write address is less than reading address, writing controller (12) starts to receive FIFO(3 described in step 3)) in data be respectively written in the middle of the local storage of described first processor core and the second processor core, complete the exchange of former address data.
nullThe memory access method of support former address the most according to claim 1 data exchange，It is characterized in that: described step 2) in，The transmission data packetization unit (4) of described first processor core according to the destination address of data and read-write mode to first processor core described in on-chip interconnection network arbitration unit application to the data channel of the second processor core，During the data exchange request that the arbitration of described on-chip interconnection network receives first processor core at the same time and the second processor core sends，The data channel of free time will be respectively allocated to first processor core and the second processor core，If obtaining the right to use of passage，Then by described transmission data packetization unit (4) first by read-write mode information、Source address information、Destination address information and transmission byte number information composition data packet head are sent to the second processor core，Followed by retransmit other data to described second processor core.
The memory access method of support former address the most according to claim 2 data exchange, it is characterized in that: in described step 3), described reception data unwrapper unit (5) is by the read-write mode information of described data packet head, destination address information and receives byte number information and is respectively stored in reception reading and writing data mode register (54), receives data destination address register (52) and receive in the middle of byte number depositor (51), then receives and data unpacked storage to described reception FIFO(3) central.
4. the memory access apparatus supporting the exchange of former address data, it is characterised in that: include data read-write control device (1), send FIFO(2), receive FIFO(3), send data packetization unit (4) and receive data unwrapper unit (5)；
Described data read-write control device (1) includes that read-write mode depositor (13), source address register (14), destination address register (15), transmission byte number depositor (16), Read Controller (11), writing controller (12) and address are compared and address choice parts (17), described data read-write control device (1) according to the order of FIFO from described receptions FIFO(3) in the middle of reading data send the data to local storage；
Described transmission FIFO(2) it is connected with described data read-write control device (1), transmission data packetization unit (4), receive the data exported from described local storage；
Described reception FIFO(3) it is connected with described reception data unwrapper unit (5), data read-write control device (1), receive the data exported from described reception data unwrapper unit (5)；
Described transmission data packetization unit (4) includes data packing state machine (41) and transmission data counter (42), described transmission data packetization unit (4) and described transmission FIFO(2), data read-write control device (1) and on-chip interconnection network be connected, described transmission data packetization unit (4) presses the order of FIFO from sending FIFO(2) in the middle of read data；
Described reception data unwrapper unit (5) includes that receiving byte number depositor (51), reception data destination address register (52), reception data source address depositor (53), reception reading and writing data mode register (54), reception data counter (56) and data unpacks state machine (55), described reception data unwrapper unit (5) and receive FIFO(3), data read-write control device (1) and and on-chip interconnection network be connected, the packet received is unpacked.
The memory access apparatus of support former address the most according to claim 4 data exchange, it is characterized in that: the data bus bit a width of W byte between described memory access apparatus and local storage, described memory access apparatus and a width of w-byte of data bus bit of on-chip interconnection network, W is at least the twice of w.
The memory access apparatus of support former address the most according to claim 4 data exchange, it is characterised in that:
Described read-write mode depositor (13) is connected with configuration bus, Read Controller (11) and transmission data packetization unit (4) and reception data unwrapper unit (5) of outside input, described read-write mode depositor (13) accepts described configuration bus and reads the assignment operation of configuration bus from the strange land receiving data unwrapper unit (5), and the data value of described read-write mode depositor (13) is exported described Read Controller (11) and transmission data packetization unit (4) by holding wire, the most also accept the clear operation of described Read Controller (11)；
Described source address register (14) is connected with configuration bus, Read Controller (11), transmission data packetization unit (4) and reception data unwrapper unit (5) of outside input, described source address register (14) acceptance configuration bus and the assignment operation from the strange land reading configuration bus receiving data unwrapper unit (5), and the data value of described source address register (14) is exported Read Controller (11) and transmission data packetization unit (4) by holding wire.
The memory access apparatus of support former address the most according to claim 4 data exchange, it is characterized in that: described destination address register (15) is connected with configuration bus, transmission data packetization unit (4) and reception data unwrapper unit (5) of outside input, described destination address register (15) accepts configuration bus and reads the assignment operation of configuration bus from the strange land receiving data unwrapper unit (5), and the data value of described destination address register (15) is directly output to send data packetization unit (4) by holding wire；
Described transmission byte number depositor (16) is connected with configuration bus, Read Controller (11), transmission data packetization unit (4) and reception data unwrapper unit (5) of outside input, described transmission byte number depositor (16) acceptance configuration bus and the assignment operation from the strange land reading configuration bus receiving data unwrapper unit (5), and the data value of described transmission byte number depositor (16) is exported Read Controller (11) and transmission data packetization unit (4) by holding wire.
nullThe memory access apparatus of support former address the most according to claim 4 data exchange，It is characterized in that: described Read Controller (11) includes read states machine (111)、Read counter (112) and reading address adder (113)，With described read-write mode depositor (13)、Source address register (14)、Transmission byte number depositor (16)、Address is compared and is connected with address choice parts (17) and writing controller (12)，The value of described read counter (112) is added with the value of source address register (14) and obtains reading address by described reading address adder (113)，And described reading address is exported to address compare and address choice parts (17)，Described Read Controller (11) carries out the read access operation of local storage according to the pattern of read-write mode depositor (13)；
Described writing controller (12) includes write state machine (121), write enumerator (122) and write address adder (123), with read-write mode depositor (13), receive FIFO(3), receive data unwrapper unit (5), address is compared and is connected with address choice parts (17) and Read Controller (11), the reception data destination address inputted from described reception data unwrapper unit (5) is added with the value writing enumerator (122) and obtains write address by described write address adder (123), and the value of described write address is exported to address compare and address choice parts (17)；
Described address is compared and address choice parts (17) and described Read Controller (11), writing controller (12), receive data unwrapper unit (5) to be connected with read-write mode depositor (13), receive reading address signal that described Read Controller (11) exports and the writing address signal that writing controller (12) exports, reading address and write address are compared, and comparative result is returned to described writing controller (12), according to the value of the reception data WriteMode information exported from described reception data unwrapper unit (5) and read-write mode depositor (13), described reading address and write address are operated simultaneously.
The memory access apparatus of support former address the most according to claim 4 data exchange, it is characterized in that: described transmission data packetization unit (4) is connected with on-chip interconnection network and is connected, data counter (42) is sent including data packing state machine (41) and one, by the order of FIFO from described transmission FIFO(2) central reading data, and it being sent to on-chip interconnection network after the data of reading being packed, described packet includes read-write mode, destination address, source address and four kinds of information of transmission byte number.
The memory access apparatus of support former address the most according to claim 4 data exchange, it is characterised in that: described reception byte number depositor (51), reception data destination address register (52), the value of reception reading and writing data mode register (54) are directly output to described data read-write control device (1) by holding wire.
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| CN104182360B (en) * | 2014-08-18 | 2017-12-08 | 记忆科技(深圳)有限公司 | The trace log output processing method and system of multi-core environment |
| DE102015211320A1 (en) * | 2015-06-19 | 2016-12-22 | Robert Bosch Gmbh | Storage unit for automatically multiplying the contents of a storage location, and data network with storage unit |
| US10222853B2 (en) * | 2016-03-03 | 2019-03-05 | Qualcomm Incorporated | Power saving techniques for memory systems by consolidating data in data lanes of a memory bus |
| WO2019084789A1 (en) * | 2017-10-31 | 2019-05-09 | 深圳市大疆创新科技有限公司 | Direct memory access controller, data reading method, and data writing method |
| EP3877864A1 (en) * | 2018-11-09 | 2021-09-15 | Xilinx, Inc. | Streaming platform flow and architecture |
| CN111061671B (en) * | 2019-12-13 | 2021-08-17 | 上海灵动微电子股份有限公司 | SPI transmission control method, sending equipment and receiving equipment |
| CN111124953B (en) * | 2019-12-18 | 2021-04-27 | 海光信息技术股份有限公司 | Data exchange method, device, processor and computer system |
| CN115327586B (en) * | 2022-10-13 | 2023-02-10 | 北京凯芯微科技有限公司 | Processing device and signal processing method for navigation satellite signals |
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