CN101593705B

CN101593705B - Manufacturing method of chip support plate

Info

Publication number: CN101593705B
Application number: CN2008101087774A
Authority: CN
Inventors: 陈昌甫
Original assignee: Xinxing Electronics Co Ltd
Current assignee: Xinxing Electronics Co Ltd
Priority date: 2008-05-29
Filing date: 2008-05-29
Publication date: 2011-07-13
Anticipated expiration: 2028-05-29
Also published as: CN101593705A

Abstract

The invention discloses a manufacturing method of a chip support plate. Firstly, a cladding plate comprising a first metal layer, a second metal layer and an etching stopping layer is provided, the first metal layer is defined as a first lead pattern, and an isolating layer is pressed and combined on the first lead pattern; then the second metal layer is defined as a plurality of projection weld pads, the etching stopping layer which is not covered by the projection weld pads is removed to form a weld resisting layer, clearances among the plurality of projection weld pads are filled, the upper surface of each projection weld pad is exposed, and finally the upper surface of the projection weld pad is etched, and a plurality of joint concave holes are formed by automatically aiming.

Description

The manufacture method of chip support plate

Technical field

The present invention relates to a kind of manufacture method of chip support plate, be particularly related to the manufacture method of a kind of crystal covered carrier-board (flip-chipsubstrate), can form on the crystal face covering of support plate in automatic aligning (self-aligned) mode and engage shrinkage pool (bonding aperture), promote welding resistance aligning accuracy (solder mask registrationaccuracy) thus.

Background technology

As is known to the person skilled in the art, chip support plate is the potted element that often uses in the semiconductor back-end technology, and its function comprises binding chip and motherboard (motherboard), protection chip and heat radiation.Chip support plate mainly is to be formed by stacking by multi-layered patterned conductor layer and multilayer dielectric layer, and the conductor layer of different layers then is to constitute electric binding by the plating via (plated through hole) that is formed in the insulating barrier.

In the past chip-packaging structure, chip mainly is that the mode with wire-bonded (wire bonding) is connected with chip support plate.Along with chip technology constantly develops towards high frequency, high pin number, the requirement on the conventional wire bond package can't satisfy electrically gradually chip package (flip chip) technology so industry develops.Compared to the conventional wire joining technique, chip package is the encapsulation technology that adopts Solder Bumps (solder bump) to be connected with chip support plate as chip, except the density that can increase substantially the chip pin, more can reduce interference of noise, strengthen electrical usefulness, improve heat-sinking capability and reduction encapsulation volume.

Yet the manufacturing technology of crystal covered carrier-board still has bottleneck further to overcome and improves at present.For instance, known technology is after forming welding resistance (solder mask) layer, need in solder mask, to form the welding resistance opening with the exposure (exposure) and (development) technology of development more in addition, expose the metal gasket of below, but such practice is met but just before insoluble contraposition deviation (misalignment) problem.

Summary of the invention

Main purpose of the present invention is promptly in the manufacture method of the crystal covered carrier-board that a kind of innovation is provided, with deficiency and the shortcoming that solves above-mentioned prior art.

For reaching above-mentioned and other purpose, the invention provides a kind of manufacture method of chip support plate, cladding sheet at first is provided, it is by the first metal layer, the stacked formation of second metal level and etching stopping layer, this etching stopping layer folder is established between this first metal layer and this second metal level, then this first metal layer is defined as first wire pattern, wherein this first wire pattern comprises a plurality of metal gaskets, follow pressing insulating barrier on this first wire pattern, then this second metal level is defined as a plurality of convex pads, remove not this etching stopping layer subsequently by this a plurality of convex pads covered, expose this insulating barrier and this first wire pattern of part, on this insulating barrier that exposes and this first wire pattern, form solder mask again, wherein this solder mask fills up the space between these a plurality of convex pads, and exposing the respectively upper surface of this convex pads, the upper surface of respectively this convex pads that will expose at last etches away the thickness of a part, aims at automatically thus and forms a plurality of joint shrinkage pools.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, better embodiment cited below particularly, and conjunction with figs. are described in detail below.Yet following better embodiment and graphic only for reference and explanation usefulness are not to be used for the present invention is limited.

Description of drawings

Fig. 1 to Figure 10 is the generalized section according to the preferred embodiment of the present invention illustrated.

Description of reference numerals

1 cladding sheet, 10 the first metal layers

10a first wire pattern 12 etching stopping layers

14 second metal levels, 20 look edge layers

22 the 3rd metal level 22a, second wire pattern

24 copper electroplating layers, 100 crystal covered carrier-boards

Second of first 100b of 100a

102 interlayer contact mats, 104 metal gaskets

142 convex pads, 202 interlayer through holes

202a conductive through hole 222 tin ball pad

224 fine rule roads, 302 solder masks

The 312 welding resistance perforates of 304 solder masks

322 engage shrinkage pool

Embodiment

See also Fig. 1 to Figure 10, it is the generalized section that manufacture method illustrated according to a kind of crystal covered carrier-board of the preferred embodiment of the present invention.As shown in Figure 1, cladding sheet (cladding sheet) 1 at first is provided, it is made of the first metal layer 10, etching stopping layer (etching stop layer) 12 and second metal level 14, and etching stopping layer 12 is located between the first metal layer 10 and second metal level 14.Wherein preferably, the first metal layer 10 and second metal level 14 are Copper Foil, and etching stopping layer 12 is nickel foil or silver foil, but are not limited thereto.According to a preferred embodiment of the invention, cladding sheet 1 can be copper-nickel-copper (Cu/Ni/Cu) three ply board or copper-Yin-copper (Cu/Ag/Cu) three ply board.

According to a preferred embodiment of the invention, the thickness of the first metal layer 10 is approximately between 10 microns to 30 microns, for example 18 microns, the thickness of etching stopping layer 12 is approximately between about 1 micron to 2 microns, the thickness of second metal level 14 is approximately between 40 microns to 120 microns, for example, and 60 microns or 80 microns.Wherein, preferably, the thickness of second metal level 14 is greater than the thickness of the first metal layer 10.

As shown in Figure 2, then utilize photoetching and etch process, the first metal layer 10 is defined as the first line pattern 10a, wherein the first line pattern 10a comprises interlayer contact mat 102 and metal gasket 104.Aforesaid photoetching and etch process are included in and form the first photoresist dry film (figure does not show) on the first metal layer 10, on second metal level 14, form the second photoresist dry film (figure does not show), then, only to this exposure of first photoresist dry film and development, on the first metal layer 10, form etching mask patterns, then, optionally with the first metal layer 10 ablations that do not covered by this etching mask patterns, expose the etching stopping layer 12 of part, at last, this etching mask patterns and the second photoresist dry film are removed.

As shown in Figure 3, then forming insulating barrier 20 on the first line pattern 10a and on the etching stopping layer 12 that exposes, for example, preimpregnation material (prepreg), ABF resin (Ajinomoto Build-upFilm), epoxy resin, pi (polyimide) etc.On insulating barrier 20, be formed with the 3rd metal level 22, for example, Copper Foil.Certainly, also can be directly at pressing gum Copper Foil (RCC) on the first line pattern 10a and on the etching stopping layer 12 that exposes.

As shown in Figure 4, then carry out bore process, for example, laser drill or machine drilling technology, in the 3rd metal level 22 and insulating barrier 20, correspond to the position of interlayer contact mat 102, get out a plurality of interlayer through holes 202, use the interlayer contact mat 102 that exposes part.

As shown in Figure 5, carry out electroplating technology, for example electroless-plating technology forms copper electroplating layer 24 in interlayer through hole 202 and on the surface of the 3rd metal level 22, so forms conductive through hole 202a in insulating barrier 20.

As shown in Figure 6, carry out the thick reduction of copper (copper reduction) technology, utilize as technology such as polishing or grinding, the thickness that reduces second metal level 14 and the 3rd metal level 22 respectively is to desired thickness range, for example, subtract thick after, the thickness of second metal level 14 is preferable approximately between 15 microns to 25 microns, the thickness of the 3rd metal level 22 is preferable approximately between 15 microns to 25 microns.

As shown in Figure 7, then utilize photoetching and etch process, the 3rd metal level 22 is defined as the second line pattern 22a, comprising tin ball pad 222 and fine rule road 224, and second metal level 14 is defined as convex pads (bump pad) 142, and expose the etching stopping layer 12 of part.Convex pads 142 corresponds to the position of metal gasket 104.Same, aforesaid photoetching and etch process comprise formation photoresist dry film (figure does not show), to this exposure of photoresist dry film and development, to form etching mask patterns, then, optionally the metal level ablation that will do not covered by this etching mask patterns is last, and this etching mask patterns is removed.

Then, as shown in Figure 8, etching stopping layer 12 ablations that optionally will expose only keep the etching stopping layer 12 under the convex pads 142.At this moment, a plurality of convex pads 142 of being connected with crystal covered chip of being used for have been formed with on first (or covering crystal face) 100a of crystal covered carrier-board 100, and in be embedded in metallic circuit pattern 10a in the insulating barrier 20, corresponding metal gasket 104 constitutes electrically connects among etching stopping layer 12 and the metallic circuit pattern 10a and convex pads 142 promptly sees through.On second (or motherboard face) 100b of crystal covered carrier-board 100, be formed with the metallic circuit pattern 22a that comprises tin ball pad 222, wherein metallic circuit pattern 22a is formed on the surface of insulating barrier 20.

As shown in Figure 9, then on first 100a of crystal covered carrier-board 100, form solder mask 302, its execution mode can be to adopt coating or printing process, make solder mask 302 fill up space between these a plurality of convex pads 142, cooperate follow-up strickling step, make the surface of the upper surface of last convex pads 142 and solder mask 302 with high.In other words, must make the upper surface of convex pads 142 to be exposed, and can not be covered by solder mask 302.On second 100b of crystal covered carrier-board 100, then be formed with solder mask 304, and, in solder mask 304, define welding resistance perforate 312 by exposure and developing process, expose the tin ball pad 222 of part.

As shown in figure 10, on first 100a of crystal covered carrier-board 100, carry out etch process at last, etch away the convex pads 142 of segment thickness, form with automatic alignment so and engage shrinkage pool 322.When etching convex pads 142, can utilize photoresist dry film (figure does not show) to cover and protect first 100a of crystal covered carrier-board 100.The invention has the advantages that the joint shrinkage pool 322 that covers on the crystal face 100a forms with automatic alignment so, but not form with exposure imaging technology as Prior Art, therefore, engaging shrinkage pool 322 can be fully and convex pads 142 accurate contrapositions and do not have skew, has effectively promoted the welding resistance aligning accuracy.

The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. the manufacture method of a chip support plate includes:

Cladding sheet is provided, and it is by the first metal layer, second metal level and etching stopping layer is stacked constitutes, and this etching stopping layer is located between this first metal layer and this second metal level;

This first metal layer is defined as first wire pattern, comprises a plurality of metal gaskets;

Pressing insulating barrier on this first wire pattern;

This second metal level is defined as a plurality of convex pads;

Remove not by this etching stopping layer that this a plurality of convex pads covered, expose this insulating barrier and this first wire pattern of part;

Form solder mask on this insulating barrier that exposes and this first wire pattern, wherein this solder mask fills up the space between these a plurality of convex pads, and exposes the respectively upper surface of this convex pads; And

The upper surface of respectively this convex pads that will expose etches away the thickness of a part, aims at automatically thus and forms a plurality of joint shrinkage pools.

2. the manufacture method of chip support plate as claimed in claim 1, wherein this second metal layer thickness is greater than the thickness of this first metal layer.

3. the manufacture method of chip support plate as claimed in claim 1, wherein the thickness of this etching stopping layer is between 1 micron to 2 microns.

4. the manufacture method of a chip support plate includes:

This first metal layer is defined as first wire pattern, comprises a plurality of interlayer contact mats and metal gasket;

Pressing insulating barrier and the 3rd metal level on this first wire pattern;

In this insulating barrier, form a plurality of conductive through holes, make the 3rd metal level be electrically connected this interlayer contact mat;

The 3rd metal level is defined as second line pattern;

This second metal level is defined as a plurality of convex pads;

5. the manufacture method of chip support plate as claimed in claim 4, wherein this second metal layer thickness is between 40 microns to 120 microns.

6. the manufacture method of chip support plate as claimed in claim 4, wherein the thickness of this first metal layer is between 10 microns to 30 microns.

7. the manufacture method of chip support plate as claimed in claim 4, wherein this insulating barrier comprises the preimpregnation material.

8. the manufacture method of chip support plate as claimed in claim 4, wherein this insulating barrier comprises ABF resin, epoxy resin or pi.

9. the manufacture method of chip support plate as claimed in claim 4 wherein includes respectively this second metal level and the 3rd reducing thickness of metal layer in addition to predetermined thickness range.

10. the manufacture method of chip support plate as claimed in claim 9, wherein this predetermined thickness range is between 15 microns to 25 microns.

11. the manufacture method of chip support plate as claimed in claim 4, wherein this second line pattern comprises tin ball pad and fine rule road.