CN101458559B - Apparatus and method for power management control - Google Patents
Apparatus and method for power management control Download PDFInfo
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- CN101458559B CN101458559B CN2008102136320A CN200810213632A CN101458559B CN 101458559 B CN101458559 B CN 101458559B CN 2008102136320 A CN2008102136320 A CN 2008102136320A CN 200810213632 A CN200810213632 A CN 200810213632A CN 101458559 B CN101458559 B CN 101458559B
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- G06F1/26—Power supply means, e.g. regulation thereof
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- G—PHYSICS
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Abstract
A power management control apparatus including a memory unit configured to store a program for disabling a previously determined Link power management state when a system enters a specific operating state and for enabling the disabled Link power management state when the system is resumed, a processor configured to access the memory unit and to execute the program, and a control unit connected to the processor and the memory unit and configured to manage Link power based on a result of executing the program.
Description
Draw on the side of association request
The application requires to be filed in the right of priority of on Dec 12nd, 2007 at the korean application No.10-2007-0128724 of Korea S's submission, and its full content is intactly quoted is contained in this.
Technical field
The present invention relates to power management control; Relate more specifically to a kind of apparatus and method of power management control; Wherein---for example L0s and L1 state of the active-state power management (ASPM) of the power management standard of being correlated with of the link between conduct and chipset and the device---is disabled when system gets into the predetermined work state of S3 for example or S4 with being in each relevant power management state of link of active state between chipset and the device; And when system recovery, activate the ASPM state of being forbidden (L0s or L1) once more, support L0s and L1 state thus as the link power management state between chipset and the device.
Chipset, i.e. control module, and the link between the device is the link of high-speed PCI (PCI-E) scheme, and power management ASPM state (L0s and L1) is the power management state of PCI-E.
Background technology
Below, will describe prior art of the present invention.
Recently, set up with high-speed PCI (being referred to as PCI-E hereinafter) scheme such as the link between each device of the chipset of north bridge and south bridge and computer system.Through introducing PCI-E, the performance condition between chipset and the device, for example data rate will greatly improve.Yet the problem of existence is that the power that all links are consumed also can increase.
Therefore, the power management standard of ASPM as the link between chipset and the device proposed.The power management state of ASPM definition L0, L0s, L1, L2 and L3.When system is in normal operating conditions, promptly when system does not get into standby mode, can support these three states of L0, L0s and L1 in all power management states.
Routinely, the ASPM state of system is launched or is forbidden through BIOS basically, and the duty of guard system is not how.Although L0s that (the for example S0 state of ACPI power management standard) supported when system is in normal operating conditions and L1 state are the functions of being supported by chipset manufacturer basically; Yet the state by the chipset manufacturer support depends on that the integrity of system possibly be different, and is causing system unstable sometimes.
Particularly; At the control module of system and the link power management state between the device---be L0s or the L1 of ASPM; Perhaps they both---under the situation that when system is in normal operating conditions, is activated, if working state of system gets into standby mode (S3 or S4 in the ACPI power management standard), the link management state also gets into L2 or L3.Then, in the process of recovery system duty, the link power management state can be any in L0, L0s, the L1 state, and this causes the instability of system, and so generation systems hang-up frequently (phenomenon that a kind of system stops) or blue screen.
Therefore, BIOS often is designed to not support ASPM function or chipset (south/north bridge) between---being control module and high-speed PCI device (for example Video Controller, Ethernet device and WLAN)---L0s and L1 state.
Although above-mentioned term and work and power rating be mainly with reference to the standard of our company, yet also can under particular condition, select some terms arbitrarily by the applicant.Because their utilization and implication are specified in corresponding description of the present invention, therefore note and to understand the present invention through the utilization and the implication of these terms, rather than only stick to these terms itself.
Summary of the invention
The present invention proposes based on the mode switch of system's particular job state the power management state of the link between control module (chipset) and the device to be controlled.
According to the present invention; A kind of power management apparatus and method have been proposed; When the for example S3 that wherein in system gets into ACPI for example, defines or the predetermined work state of S4 state; Disabled with the relevant power management state of link---for example L0s and L1 state---between control module and the device; And the power management state of when system recovery, being forbidden in the active link (L0s and L1) prevents unsettled system recovery thus and supports L0s and the L1 state as the power management state of the link between control module and the device.
In the present invention; In S3 or S4 state as working state of system; The link power management state of ASPM is designed to: along with chipset (south/north bridge), promptly the PCI-E power management state of the link between control module and the device gets into S3 or S4 state, makes it support L2 or L3 state.
Therefore; Although when system gets into S3 or S4 state; The ASPM of the power management state that is used for managing L0s and L1 state---for example as---is disabled with each the relevant power rating of link between chipset and the device, but owing to L2 and L3 state are supported, so do not have problems.
When system turned back to normal operating conditions, L0s and L1 state do not supported, returns normal operating conditions so that till the link power management state also can stably get back to a state (for example getting back to the L0 state) up to system.
Yet, when the duty of system recovery and system turns back to the S0 state, activated for use once more according to the L0s and the L1 state of the link power management state of ASPM.
Realizing when of the present invention and since the ASPM of PCI-E input and output interface work by the BIOS guiding, propose a kind of can with the driver of BIOS co-operating ASPM.
The present invention proposes in addition; When the duty of related device continuous alert status one predetermined amount of time or more time and each device of being connected simultaneously for example is in the predetermined state of D0 state (full conducting or device activate); ASPM mechanism is converted to lower power state with the link power of the device that is in holding state in the PHY, for example L0 or L1 state.
Propose simultaneously, when because produce traffic data (traffic) and when making the duty of device change into D0 and ASPM to be in L0s or L1 state, ASPM is converted to the L0 state from arbitrary part (chipset or device) of link.
Variation through the duty of driver detection system and/or device is proposed, and based on the power rating that changes ASPM from the order of WMI-ACPI driver through BIOS.
The present invention proposes in addition, based on the user mode of system, power type, remaining power amount etc., through control ASPM such as related application, BIOS, users.
Be used to realize that the power management control device according to the present invention of these purposes comprises: storage unit; Be used for stored programme; The link power management state of confirming before the forbidding when this program gets into the particular job state in system is launched the link power management state of being forbidden when system recovery; Processor is used for storage unit access and executive routine; And control module, it is connected in processor and storage unit with based on program execution result link management power.
In addition, power management control method according to the present invention comprises the following steps: the variation of (A) detection system duty; (B) broadcast the duty that is changing; (C) receive said broadcasting; (D) confirm that current link management state is activated still forbidding; And (E) according to the reception of step C and D with confirm the link power management state that the result leads and confirms before launching or forbidding.
Be according to the beneficial effect of power management control device of the present invention and method as stated; The predetermined link power management state of forbidding when system gets into particular state; Therefore and after system turns back to normal operating conditions, then launch the power rating of being forbidden, generation systems is hung up when preventing to get back to normal operating conditions in system; And therefore various link power management states (for example L0, L0s and L1) can be provided in normal operation, thereby practice thrift link power.
In addition, in the present invention, the link power management state is based on working strategies and/or the power supply type of system, according to conducting or break off control setting, can effectively use power thus.
Description of drawings
Fig. 1 be chipset (south/north bridge)---be control module---and device between the system chart of an embodiment realizing with the PCI-E method of link.
Fig. 2 be illustrate as one embodiment of the invention, to transmit and receive data, 23 and 24 block diagram for example divides into groups through the PCI-E link for components A and B.
Fig. 3 illustrates the view of PCI-E structure (structural topology) according to another embodiment of the present invention.
Fig. 4 and Fig. 5 are illustrated in the middle situation of using the situation of interchanger and not using interchanger of PCI-E structure (structural topology) of Fig. 3 respectively.
Fig. 6 is the general view that transaction layer is shown, wherein the transmission of data and be received in Fig. 1, Fig. 2 and two parts shown in Figure 4 between carry out for example control module and device, components A and B, root complex and end points (endpoint).
Fig. 7 a comprises and the block diagram of BIOS collaborative work with the driver of the for example battery management software (a kind of application program of link power management) of the power management ASPM of realization PCI-E.
Fig. 7 b illustrates to use battery management software, depend on that system state launches or forbid the embodiment of ASPM.
Fig. 8 is the figure that the user interface of the ASPM that uses battery management software that each device that is connected in control module is set is shown.
Fig. 9 is the process flow diagram that illustrates when the duty of system gets into S3 or S4 state through the step of L0s in the ASPM state of BIOS forbidding PCI-E or L1 state.
Figure 10 is a process flow diagram of launching the step of L0s or L1 state the ASPM state of PCI-E when duty when system is shown from S3 or S4 recovering state through BIOS.
Embodiment
Below, describe in detail according to power management control device of the present invention and method with reference to accompanying drawing.
At first, the power management of the chipset (south bridge or north bridge are called control device hereinafter) of the term of mentioning among the present invention " ASPM " expression PCI-E scheme and the link between the device.
Hereinafter, working state of system representes that the state according to the power that offers system, clock etc. is divided into the system state of various modes, for example, is categorized into for example S0-S5 state with system state in the ACPI power management.
In addition, the device duty representes to be divided into according to the states such as power that offer this device the state of the device of various modes, for example, in the ACPI power management, system state is categorized into for example D0-D3 state.
L0, L0s, L1, L2 and L3 represent by the power management state of the PCI-E of ASPM support separately and are called as the link power management state.
If possible, select nowadays widely used general terms as the term that uses among the present invention as far as possible.Yet some terms are optional by the applicant under some particular condition, and their utilization and implication detailed presentations are in corresponding description of the present invention.Therefore, note and to understand the present invention through the utilization and the implication of these terms, rather than only stick to the general sense of these terms.
Based on an embodiment the present invention is carried out general description.
Because the appearance of PCI-E, the speed and the performance of data bus scheme greatly improve.
Yet, chipset---be control module---and device between PCI-E link (bus) power locating to consume correspondingly greatly increase.
ASPM is the power management standard of the PCI-E link between control module and the PCI-E device.
In ASPM, can state be divided into L0, L0s, L1, L2 and L3, and system can get into L0, L0s or L1 state in work.Therefore, entering is up to the requirement that the L1 state is the power management aspect.
Yet this performance that can be depending on the PCI-E chain circuit device is supported or is not supported.
Most problems betide system after getting into S3 state (on-hook), S4 state (dormancy), S5 state states such as (whole power down except that ICH revives), recover in.When ASPM supports to reach to L0s or L1 state, the fatal error of for example system's hang-up or blue screen can take place, and because this problem causes many systems not support L0s and L1 state.
When the L0s of ASPM and L1 state receive when supporting, can not produce any problem when system is in running order.Yet; If when after system is getting into S3 state (on-hook), S4 state (dormancy) or S5 state, recovering; ASPM supports to be up to the state of L0s or L1, owing to can have problems as described above, therefore an object of the present invention is the unreasonable part that the removal system does not support ASPM.
Therefore, in the present invention, when system got into S3 or S4 state, enabled L0s of ASPM or L1 state were disabled, and launch L0, L2 or the L3 state of ASPM.Therefore, prevent the generation of fault in the system operation.
Promptly; Utilization comprises the application program (hereinafter being referred to as battery management software) that can support the driver of ASPM through form management tool-advanced configuration and power interface (WMI-ACPI); Operating system combines each link power management state of BIOS control ASPM, thereby normally uses the function of ASPM.
The management function of ASPM can be applicable to all types of current power supplys, for example battery supply and AC power supplies.
Foregoing the present invention is the most effective when using external graphic card, can obtain 1-3 watt energy-saving effect in this case.
In addition, the device that connects through PCI-E obtains the proportional energy-saving effect of power consumption degree with device.In addition, the present invention can be used for when AC power is provided, observing Energy Star standard.
Hereinafter, the present invention will be described in conjunction with accompanying drawing.
Fig. 1 be wherein with the PCI-E scheme realize chipset (south/north bridge)---be control module---and device between the system chart of an embodiment of link.
As shown in the figure, come configuration-system through interconnection central processing unit (CPU) 10, north bridge 11 and south bridge 14.At this moment, Video Controller 13 is connected in CPU10 and handles with control of video, and connects through north bridge 11 and controlled by it such as the system storage 12 of RAM etc.Except being connected by south bridge 14 and receiving, peripherals such as for example hard disk drive (HDD) 15, Audio Controller 16, BIOS ROM17 and Ethernet/WLAN/miniature cards/turbine storer 18, USB (USB) 19 also are provided for controlling the for example embedded controller 110 of the input media of keyboard, touch pads etc. its control.
Control module (south/north bridge) 11 or 14 and the high-speed PCI device between chain route PCI-E set up, and PCI-E supports to be called the power management of active-state power management (ASPM).Simultaneously, because the appearance of PCI-E, speed and performance greatly improve, however chipset---be control module---and install between the power consumption at PCI-E link place also greatly increase.Therefore, propose the power management standard of ASPM, and the power management state among the ASPM generally is classified into L0, L0s, L1, L2, and L3 as link.
In most cases because the ASPM of PCI-E is like the such work in BIOS guiding ground, if BIOS do not support, even Windows instructs power management, also can not its operation of execution in the practice.Therefore, the driver that links to each other with BIOS---for example battery management software---combines ground operation A SPM with BIOS.
In the present invention, BIOS is set to launch or forbid according to the link power management state of the control command ASPM of driver.
In aforementioned arrangements; HDD15 storage battery management software program; This battery management software program comprises the driver that combines ground operation A SPM with BIOS and/or is used for the device of current use in the detection system and/or the filter driver of program, and they are worked as the Windows application in the system storage 12.
That is to say that the operating system execution of being carried out by CPU10 is stored in the battery management software in the system storage 12, and this battery management software is carried out link power management with filter driver and/or BIOS with combining.
Perhaps, be provided for carrying out the program that comprises the driver that is used for operation A SPM, battery management software for example, Attached Processor to carry out link power management.
Also possibly use the current high-speed PCI device of working of filter driver identification and in these devices each is provided with ASPM.
Here, filter driver is expressed as followsin through the function that its identification is used to carry out the device of ASPM function:
Boolean is provided with ASPM () to device;
Rreturn value
If install successfully then be non-zero; Otherwise be zero.
For realizing power management, on current device of working, carry out this function according to ASPM.Therefore, filter driver can link this function, thereby finds out current device of working.
In addition; The present invention is provided with BIOS ROM17; It is embedded with BIOS, and wherein BOIS discerns after guidance system, disposal system guiding, search and running operating system and the hardware unit in the system is set, and combines to control (launching/forbid) ASPM with battery management software.
Data between control module among Fig. 1 and each device are sent and are received and carry out through PCI-E.
Fig. 2 be illustrate as one embodiment of the invention, to transmit and receive data, 23 and 24 block diagram for example divides into groups through the PCI-E link for components A and B.
As shown in the figure, receiving block data 23 between components A 20 and the part B 21 and 24 transmission and reception realize through the PCI-E scheme.
The PCI-E link is to be realized by the duplexing single file communication channel between components A 20 and the part B 21 (this is a kind of structure that is configured to two right unidirectional data bus, and one of them bus only is used for receiving, and another bus only is used for sending data).
Link is represented the duplexing single file communication channel between two parts.Basic high-speed PCI link comprises that the signal of differential driving of two low-voltages is right: transmission shown in Figure 2 to receive right.
The connection details of the PCI-E link of Fig. 2 is described below.
Basic link: the PCI high-speed link is by being embodied as transmission to constituting with the right duplex one way differential link of reception.Use encoding scheme to embed data clock to obtain very high data rate.
Signal transmission rate: in case be initialised, each link must be only worked on one of them of all transmitting signal levels of being supported.For first generation high-speed PCI technology, only defined a signal transmission rate, it provides the former bandwidth of effective 2.5 gigabit/sec/passage/direction.Along with the development of technology in future, this data rate is expected to improve.
Passage: a link must be supported at least one passage: each passage represents one group of differential signal to (a pair of being used for transmits, and a pair of being used for receives).For scalable bandwidth, a link can be assembled a plurality of passages of being represented by xN, and wherein N can be any one in the link bandwidth of being supported.The x8 link is represented the aggregate bandwidth of 20 gigabit/sec on per 20 directions.This instructions has been put down in writing the example of x1, x2, x4, x8, x12, x16 and x32 channel width.
Initialization: during hardware initialization, each high-speed PCI link is acted on behalf of the negotiation of setting up following channel width and frequency of operation through two of each end of link.
Symmetry: each link is supported symmetry number purpose passage on each direction, and promptly to represent to have 16 differential signals along each direction right for the x16 link.
Fig. 3 illustrates the view of PCI-E structure (structural topology) according to another embodiment of the present invention.
As shown in the figure, PCI-E comprises central processing unit (CPU) 30, is connected in the root complex 31 of CPU, storer 32 and installs 33 and 34.
Simultaneously, owing to, can use switch 35 to be connected with other device only with pure point-to-point (P2P) form (serial communication) PCI allocation-E.That is, root complex 31 can comprise virtual or real switch 35, is connected thereby form P2P with other device 36-39.
In addition, can switch be configured to the form of separating with root complex.Therefore, PCI-E can guarantee high I/O performance and high dilatation ability through the structure of switch.
Be supplementary notes below to the PCI-E block diagram of Fig. 3.
Structure shown in Figure 3 is made up of the point-to-point link with one group of component interconnect.This illustrates a structure example that is called as hierarchy: it is made up of root complex (RC), a plurality of end points (I/O device), interchanger and high-speed PCI-PCI bridge, and all these parts are all via the high-speed PCI link interconnect.
(1) root complex
Root complex (RC) expression is connected in the CPU/ memory sub-system root of the I/O hierarchy of I/O.As shown in Figure 3, root complex can be supported one or more PCI ports.The hierarchy territory that each interface definition one is independent.Each hierarchy territory can be made up of single endpoint or the sublayering structure that comprises one or more exchanger parts and end points.Realization can chosen and depend on to ability through root complex routing peer affairs between the hierarchy territory wantonly.For example, a kind of reality or Virtual switch of realizing being included in root complex inside, thus realize full equity support with the software transparent mode.Regular different with interchanger, the general permission of root complex becomes some less groupings (except each service load) with a packet fragmentation when routing peer affairs between the hierarchy territory.The restriction of the normal packets formation rule that resulting grouping receives to comprise in this standard (for example Max_Payload_Size (Maximum Payload size), read and accomplish border etc.).Component Design person should be noted that and become some less groupings possibly have passive performance consequence packet fragmentation, and is especially all the more so to the affairs of the addressing of the device of high-speed PCI to the PCI/PCI-X bridge.
Exception: support the root complex of the reciprocity route of Vendor_Defined (seller's definition) not allow Vendor_Defined message packet fragmentation is become some less groupings; Be positioned at 128 byte boundaries except (being that resulting all groupings except last must be 10 word length integral multiples of 128 bytes), to keep that message is striden the ability that pci bus is forwarded to the PCI/PCI-X bridge.Root complex must be supported the generation of configuring request as the requesting party.Root complex allows to support the generation of I/O request as the requesting party.Root complex can not be as completion side's support lock attribute justice.Root complex is allowed to support as the requesting party generation of locked request.
(2) end points
End points refers to that a kind of ability representative is own or represent different non-high-speed PCI devices (being different from PCI device or host CPU) as the requesting party of high-speed PCI affairs or the device of completion side, and said non-high-speed PCI device comprises for example attached graphics controller or the high-speed PCI-USB20 console controller of high-speed PCI.End points be classified as legacy endpoints, high-speed PCI end points or with the integrated end points of root complex.
Fig. 4 and Fig. 5 are illustrated in the middle situation of using the situation of interchanger and not using interchanger of PCI-E structure (structural topology) of Fig. 3 respectively.
At first Fig. 4 is described, in Fig. 4, do not use interchanger to realize PCI-E scheme of the present invention.
In the ASPM of PCI-E, L0s and L1 state are supported in energy-conservation among working state of system S0 or the device equipment D0.
As shown in Figure 4, root complex 41 is corresponding to the control module (north bridge or south bridge 11 or 14) of Fig. 1, end points 48 and 49 devices 13,16 and 18 corresponding to Fig. 1.
For example, when each device 48 in root complex 41 and the PCI-E scheme when 49 communicate by letters, be the D0 state although install duty, also possibly can't on both direction, continue data communication.
That is, if under the D0 state link idle time be longer than the schedule time, then one or more PCI communications interface units of two end points of PCI-E and PCI-E link can get into L0s or L1 state with energy-conservation.
For example, if the ASPM state of PCI-E gets into L0s or L1 state, then the clock of the PCI communication interface of control module and device is controlled as the clock that is lower than under S0 or the D0, thereby saves the power consumption in realizing PCI-E.
Simultaneously, if learn through a certain interruption in process such as transmit and receive data and to have bidirectional data communication, then the PCI communication interface is converted to the L0 state once more to begin communication.
Here, will be discussed in more detail below the power rating that defines among the power management ASPM of PCI-E.
High-speed PCI-PM (ASPM) defines following link power management state:
(1) L0: active state
All high-speed PCI affairs are activated with other operation.All need L0 to support to ASPM and the compatible power management of PCI-PM.
L0s: low stand-by period, the energy-saving standby state of recovering.ASPM needs L0s to support.It is not suitable for the compatible power management of PCM-PM.The inside PLL (phaselocked loop) of all primary powers, parts reference clock and parts must keep activating during L0s always.The TLP (transaction layer packet) of the transmitter through being in the L0s state communicates by letter with DLLP (data link layer packets) and is under an embargo.ASPM uses the L0s state exclusively.The high-speed PCI Physical layer provides from the mechanism of this state fast transition to L0 state.When using common (distribution) reference clock in given link both sides, be generally less than 100 symbol times from the fringe time of L0s to L0.
Simultaneously, can make the transmitting terminal of parts on the link be in L0s, make the transmitting terminal of another parts on the link be in L0 simultaneously.
(3) L1: high stand-by period, low-power standby state.The compatible power management of PCI-PM needs L1 to support.L1 chooses wantonly ASPM, only if need specially because of concrete waveform factor.Primary power that all platforms provide and parts reference clock must keep activating during L1 always.The inside PLL of parts must cut off during L1, and withdrawing from the stand-by period with increase is that the cost realization is energy-conservation greatly.The all functions of the components downstream on given high-speed PCI link or be programmed to comprise the D state of D0, when perhaps components downstream request L1 gets into (ASPM) and receives sure responses to request, entering L1 state.Withdrawing from from L1 is through being that the upper reaches of target are initiated affairs or components downstream and wanted to initiate affairs in the face of the upper reaches and inspire with the components downstream.Generally need several microseconds from the transformation of L1 to L0.The TLP that is in the L1 state on the link communicates by letter with DLLP and also is under an embargo.
Simultaneously; In the process that between two parts shown in Figure 4, transmits and receive data; The upper reaches represent that the root complex corresponding with the control module of Fig. 1 41 receives data (Rx) from the end points 48 or 49 of current operation PCI communication interface, and downstream represent that the root complex corresponding with the control module of Fig. 1 41 sends data (Tx) to the end points 48 or 49 corresponding with device.
Therefore, if BIOS launches the ASPM of root complex, represent that then the interface unit of Tx unit 41a/41b and Rx unit 41c/41d is activated to get into L0s or the L1 state among Fig. 4.
In addition, if launch ASPM, represent that then Tx unit 48a/49b and Rx unit 48c/49d are activated to get into L0s or the L1 state among Fig. 4 in the end points side.
Power management state changes as described above, and the link power management state among Rx and the Tx gets into L0s or L1 state by this, and therefore realizes energy-conservation.
Fig. 5 is the middle block diagram that uses the situation of interchanger of PCI-E structure (structural topology) that is illustrated in Fig. 3.
As shown in the figure, the PCI-E structure is configured to comprise: with chipset---being control module---corresponding root complex 51; The end points 58 and 59 corresponding with device; And the switch 55 that connects root complex and end points.
Switch is used for realizing the P2P among the PCI-E as shown in Figure 3.
Fig. 6 illustrates the general view of transaction layer, and wherein the transmission of data and reception are between Fig. 1, Fig. 2 and two parts shown in Figure 4, to carry out, for example control module and device, components A and B, root complex and end points.
As shown in the figure, each transmitter and receiver storing communication layer 60 and 61, said communication layers 60 and 61 is confirmed to send and to receive needed data of each layer and communication protocol in advance.
In the drawings; Data link layer 60a will make an addition to data and the information that upper strata from transmitter side 60 (for example network layer etc.) (not shown) receives about the information of receiver side 61 with the form of following procotol, and the Physical layer 60b data that will receive from data link layer and information translation be encoded into signal (for example binary number) and will be sent to the Physical layer 61b of receiver side 61 through conversion and coded data.
The Physical layer 61b of receiver side 61 becomes the conversion of signals that is received data and will be sent to data link layer 61a through data converted.
Simultaneously, since transmission/receiver side is changed into reception/transmitter side based on the two-way communication in the above-mentioned affairs, the role of transmitter and receiver changes (Rx/Tx) and subsequent working.
Fig. 7 a comprises and the block diagram of BIOS collaborative work with the driver of the for example battery management software of the power management ASPM of realization PCI-E.
As shown in the figure, the operating system 70a that storage unit 70 (for example HDD or RAM) storage is used to operate ASPM of the present invention is together with BIOS with as the battery management software 70b of application program, and wherein battery management software is the RAM resident program.
In addition, BIOS ROM71 storage is used for interface (WMI-ACPI) unit 71a that between all devices, transmits and receive data and the BIOS service routine 71b that is used to control ASPM of the present invention.
Through the work of battery management software, BIOS and filter driver, ASPM is controlled with the dump energy of the state of considering each device, input power supply and/or any one or a plurality of input power supplys and launches or forbid ASPM.
Obviously, ASPM's launches or forbids control and can at random be carried out by the user.
Battery management software obtains the duty of system and transfers commands to BIOS with based on duty setting (launch or forbid) ASPM.Receive setting and the register through set ASPM information setting control module of the BIOS control ASPM of order.
That is, depend on that the link power management state (for example one of them state can be L0s or L1, or ASPM function itself can be disabled) that confirming as in advance of working state of system launched or forbidden can change as being provided with in advance.Then, the respective link supervisor status is set and is activated still forbidding in register according to setting.
Fig. 7 b illustrates to use battery management software to depend on that system state launches or forbid the embodiment of ASPM.
At first, when the duty of system 74 when S0 gets into S3, S4 or S5, S1 or S2, ASPM are disabled.
On the other hand, when system state when S3, S4 or S5 recover, ASPM is activated.
Can be set to launched automatically or forbidden by battery management software or BIOS based on working state of system by ASPM, perhaps the user can be through importing one or more predetermined key controls to launch or to forbid ASPM.
Said that working state of system S0-S5 etc. were based on advanced configuration and power interface standard (ACPI) state by several companies definition that comprises our company.
Fig. 8 is the view that the user interface of the ASPM that uses battery management software that each device that is connected in control module is set is shown.
Basically, system transmits and receive data based on the PCI-E scheme with each device (WLAN, ethernet lan, video card, turbine storer etc.).
Whether battery management software certification system state changes and changes subsequently the PCI-E Link State.For example, when working state of system when S0, S1 or S2 change into S3, S4 or S5, battery management software notice BIOS is defined in the particular link power management state (for example L0s or L1) among ASPM or the ASPM, perhaps ASPM function itself with forbidding.
On the other hand, after working state of system recovered from S3, S4 or S5, the L0s of ASPM or L1 state were activated.
Can install launching or deactivation operation of (WLAN, ethernet lan, video card, turbine storer etc.) 81 control ASPM to each.
In addition, described, but the duty of the duty of taking into account system and/or each device is provided with ASPM.
Although in general ASPM launches automatically or forbids through the for example application program of battery management software or BIOS, ASPM also can be launched or forbidden by the user.
For example, the user can use one or more predetermined input medias (the for example combination of hot key setting or predetermined key) to change the PCI-E Link State of ASPM.In addition, even also the PCI-E Link State can be set to each device 81b or 81c.
Can process that launch or forbid ASPM and/or its state of launching or forbidding be presented on the output unit.
Simultaneously, in the process of the ASPM that realizes PCI-E, can consider working power type and current state and system and each device state and launch or forbid ASPM.In addition, can manually or automatically launch or forbid ASPM with reference to type and/or the method for the aforementioned ASPM of setting.
Table 1 illustrates the type based on the input power supply of form power policy how to utilize system operation and ASPM setting.
[table 1]
ASPM based on system works strategy (form power policy) is provided with
| Power input | High-performance | Balance | Energy-conservation | Note |
| AC | Close (forbidding) | L0s | L0s/L1 | |
| DC | Close (forbidding) | L0s/L1 | L0s/L1 |
Shown in preceding, if system requirements is worked, system is remained on be not provided with the off state of ASPM (forbidding) under the high-performance of system works strategy, thereby system is capable of fast starting with work.
On the other hand, if system requirements in equilibrium state work, then correspondingly is provided with ASPM.In this case, although can ASPM be set the power supply (AC/DC) to every type as shown in table 1 differently, be not limited only to this.
In addition, if system requirements in energy saver mode work, then correspondingly is provided with ASPM.In this case, although can it is as shown in the table ASPM is set, be not limited only to this.
In the process that ASPM is set, can consider the current state of the power that uses, according to system works strategy of this power rating etc. shown in Fig. 8 and table 1.
[table 2]
Note about the ASPM setting of considering battery capacity and system works strategy
| Battery capacity | The system works strategy | ASPM is provided with | Note |
| Be higher than 75% | High-performance | Forbidding | |
| 50％～75％ | Balance | Keep preset condition | |
| Be lower than 50% | Energy-conservation | Launch |
Can use battery management software and BIOS and/or use to carry out setting of the present invention and setting operation by the pre-determined one or more input medias of user.
Fig. 9 is the process flow diagram that illustrates when the duty of system gets into S3 or S4 state through the step of L0s in the ASPM state of BIOS forbidding PCI-E or L1 state.
As shown in the figure, when the duty of system gets into predetermined S3 or S4 state, broadcast the entering of this state, and be stored in this state of battery management software detection (step S901 and S903) among the HDD.
When the duty of system becomes S3 or S4 state, through the entering of operating system broadcasting S3 or S4 state.When operating system when the duty of S0 state gets into S3, S4 or S5, operating system provides when advancing into information, and when resume work state entering S0 state.
Then, the current ASPM state (step S905) of battery management software certification PCI-E.
As confirming the result,, then indicate the BIOS forbidding to the entering of L0s or L1 state or close ASPM function itself (step S907 and S908) if L0s or L1 state are launched ASPM.
BIOS is provided with the register value of control module (north/south bridge) based on control command, thereby can forbid the ASPM of Set For Current.
System gets into S3 or S4 state, and keeps this state (step S913).
Step S903-S909 is by the battery management software executing.
Figure 10 is a process flow diagram of launching the step of L0s or L1 state the ASPM state of PCI-E when duty when system is shown from S3 or S4 recovering state through BIOS.
As shown in the figure, through user input data receive make system duty from S3 or S4 recovering state, pilot operationp system then (step S1001 and S1003).
The current ASPM state (step S1005) of battery management software certification PCI-E.
As confirming the result, if forbidding ASPM, battery management software guiding BIOS launches ASPM state (step S1007 and S1009).
BIOS is provided with the register value of control module (north/south bridge) based on control command, thereby can launch the ASPM (step S1011) of Set For Current, and system is based on this setting start working (step S1001 and S1003).
Step S1005 and S1009 are by the battery management software executing.
On the other hand, owing to when system recovery, possibly launch ASPM,,, make ASPM in initiate mode work and without any need for additional operation then through confirming process from the ASPM settings of register if ASPM launches.
Aforementioned circumstances also is applicable to the situation of when system gets into S3 or S4 state, not forbidding ASPM.That is,,,, make ASPM in disabled status work and without any need for additional operation then through confirming process from the ASPM settings of register if ASPM is disabled owing to when system gets into S3 or S4 state, possibly forbid ASPM.
As stated; In power management control device and method according to various embodiments of the present invention; Be in the link power management state of active state between chipset and the device as control module; For example get into the predetermined work state when system---disabled as the active-state power management (ASPM) of the power management state of management L0s and L1 state for example when S3 or S4 state, and when system recovery; Disabled ASPM state (L0s or L1) is activated once more, thereby supports L0s and L1 state as the link power management state between chipset and the device.
In addition, can be depending on the control power management ASPM of the present invention such as user mode, power supply type, remaining power amount of system.
The present invention should use according to the conventional multi-purpose computer or the microprocessor of the religious doctrine programming of this instructions and realize, as the technician knows in the computer realm.Senior programmer can easily provide suitable software coding based on religious doctrine of the present disclosure, as the technician knows in the software field.The present invention also can be through interconnection traditional calculations machine circuit the special IC of suitable network realize, as those skilled in that art know.
Any part of the present invention that on universal digital computer or microprocessor, realizes comprises computer program, and this computer program is to comprise being used for to the storage medium of computer programming with the instruction of carrying out process of the present invention.This storage medium can include, but are not limited to, and the dish of any kind comprises floppy disk, CD, CD-ROM and magneto-optic disk, ROM, RAM, EPROM, EEPROM, magnetic or optical card or is suitable for the medium of any kind of store electrons instruction.
Aforementioned preferred embodiment of the present invention is disclosed with the example purpose.Obviously, those skilled in that art can be in appended claims make various modifications, variation in disclosed technical spirit of the present invention and the scope, substitute or add to this.
Claims (8)
1. power management control device comprises:
If being used for detecting system state gets at S3 that advanced configuration and power interface ACPI standard define or S4 state then the module of definite link power management state before forbidding from normal operating conditions; Wherein, the S0 state that defines in said normal operating conditions and the said ACPI standard is corresponding; And
Return said normal operating conditions then the module of launching the link power management state of confirming before said if be used for detecting said system state from said S3 or S4 state; Wherein, the link power management state of confirming before said is the L0s that in active-state power management ASPM standard, defines or L1 state and is set to launch or forbid.
2. power management control method comprises:
Get into S3 or the S4 state that advanced configuration and power interface ACPI standard, defines if detect system state from normal operating conditions; The link power management state of then confirming before the forbidding; Wherein, the S0 state that defines in said normal operating conditions and the said ACPI standard is corresponding; And
Return said normal operating conditions if detect said system state from said S3 or S4 state; Then launch the said link power management state of confirming before; Wherein, the link power management state of confirming before said is the L0s that in active-state power management ASPM standard, defines or L1 state and is set to launch or forbid.
3. method as claimed in claim 2 is characterized in that, the step of the said link power management state of confirming before launching or forbidding is based on that one or more conditions in system works strategy, power supply status and the remaining power amount confirm.
4. method as claimed in claim 2 is characterized in that, and is further comprising the steps of before the step of the link power management state that said method was confirmed before launching or forbidding:
When the duty of system becomes S3 or S4 state or when said S3 or S4 state get into said S0 state from the S0 state, the variation of detection system duty; With
Confirm that current link power management state is launched or forbidding.
5. method as claimed in claim 4 is characterized in that, that said method is launched at the current link power management state of said affirmation or the forbidding step after further comprising the steps of:
Give application program with the information broadcast that indicating operating status changes,
Wherein one receive said broadcasting information, said application program is just carried out the step that result based on said affirmation step launched or forbade the link power management state of confirming before said.
6. method as claimed in claim 5 is characterized in that, said application program indication basic input/output BIOS launches or forbid the said link power management state of confirming before.
7. method as claimed in claim 6 is characterized in that, the register value that said BIOS is provided with control module is with according to the link power management state of launching or forbid Set For Current from the instruction of said BIOS.
8. method as claimed in claim 4; It is characterized in that it still is the said link power management of confirming before of forbidding that the said step of launching or forbid the link power management state of confirming is before confirmed to launch based on the one or more conditions in system works strategy, power supply status and the remaining power amount.
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| KR1020070128724A KR101464741B1 (en) | 2007-12-12 | 2007-12-12 | Apparatus and Method for controlling Power Management |
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| KR101581858B1 (en) * | 2009-06-18 | 2016-01-21 | 삼성전자주식회사 | Storage device and data processing system having the same |
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| KR20110041286A (en) * | 2009-10-15 | 2011-04-21 | 삼성전자주식회사 | Computer system and control method thereof |
| CN102375522A (en) * | 2010-08-27 | 2012-03-14 | 鸿富锦精密工业（深圳）有限公司 | Power supply system of electronic device |
| US9256268B2 (en) * | 2012-04-24 | 2016-02-09 | Intel Corporation | Adaptive low-power link-state entry policy for active interconnect link power management |
| US9323315B2 (en) * | 2012-08-15 | 2016-04-26 | Nvidia Corporation | Method and system for automatic clock-gating of a clock grid at a clock source |
| US9563256B2 (en) * | 2013-01-04 | 2017-02-07 | Intel Corporation | Processor hiding its power-up latency with activation of a root port and quickly sending a downstream cycle |
| US10496152B2 (en) * | 2013-09-27 | 2019-12-03 | Intel Corporation | Power control techniques for integrated PCIe controllers |
| US9880601B2 (en) * | 2014-12-24 | 2018-01-30 | Intel Corporation | Method and apparatus to control a link power state |
| KR102309110B1 (en) * | 2017-03-24 | 2021-10-06 | 삼성전자 주식회사 | Electronic device and method for controlling external electroinc device connected to usb type-c connector |
| US10353455B2 (en) | 2017-07-27 | 2019-07-16 | International Business Machines Corporation | Power management in multi-channel 3D stacked DRAM |
| US11314578B2 (en) * | 2019-03-06 | 2022-04-26 | Dell Products L.P. | Information handling system and method to detect and recover from spurious resets of PCIe devices |
| US11296904B1 (en) * | 2019-05-22 | 2022-04-05 | Marvell Asia Pte Ltd | Asymmetric energy efficient ethernet |
| WO2022213963A1 (en) * | 2021-04-09 | 2022-10-13 | 上海朗帛通信技术有限公司 | Method and apparatus for communication node used in wireless communication |
| US11784779B2 (en) | 2021-12-09 | 2023-10-10 | Marvell Asia Pte Ltd | Automotive asymmetric ethernet using a frequency-division duplex scheme with a low-rate echo cancelation |
| US20230324978A1 (en) * | 2022-04-06 | 2023-10-12 | Hewlett-Packard Development Company, L.P. | Power saving feature controls for add-in cards |
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| KR100306697B1 (en) | 1998-07-23 | 2001-11-30 | 윤종용 | Portable computer system for controlling the power supply of the universal serial bus and its control method |
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