CN101398666A - Big dipper satellite synchronizing clock time signal B code generating method and apparatus - Google Patents
Big dipper satellite synchronizing clock time signal B code generating method and apparatus Download PDFInfo
- Publication number
- CN101398666A CN101398666A CNA200710189732XA CN200710189732A CN101398666A CN 101398666 A CN101398666 A CN 101398666A CN A200710189732X A CNA200710189732X A CN A200710189732XA CN 200710189732 A CN200710189732 A CN 200710189732A CN 101398666 A CN101398666 A CN 101398666A
- Authority
- CN
- China
- Prior art keywords
- signal
- big dipper
- time
- sign indicating
- indicating number
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Electric Clocks (AREA)
Abstract
The invention discloses a method for generating a B code of a time signal of a synchronizing clock of Beidou satellite. The method is characterized by comprising the following steps: a. a Beidou satellite signal is received as the time source of a time synchronizing clock; b. the time signal is subject to maintenance processing to generate a DC B code signal; and c. the generated DC B code is utilized to perform amplitude modulation to generate an AC B code signal. The method has the advantages that as IRIG-B receives the Beidou satellite signal and Beidou navigation system is completely controlled by China, devices have high safety; as the Beidou satellite is positioned on a geosynchronous orbit and does not involve inter-satellite switching, the time service system is good and the time service precision is high; as the time processing part of the IRIG-B adopts a time maintenance technology, the IRIG-B can judge the correctness of the time information output by a Beidou receiving module and maintain the time by self when the Beidou satellite signal is unavailable, therefore the correctness of the time information generated by the IRIG-B can be ensured, and the availability of the system is improved.
Description
Technical field
The present invention relates to a kind of method for generation of synchronizing clock time signal, particularly relate to a kind of method for generation of big dipper satellite synchronizing clock time signal IRIG serial codes.
Background technology
Making rapid progress of the develop rapidly of social productive forces and science and technology, people have proposed more and more higher requirement to the accuracy of chronometer time and time, and various time service means continue to bring out.IRIG originates from the time synchronized in army target range, and the time system in the target range is for satellite or spacecraft is launched, conventional weapon is tested, TT﹠C system provides the standard time.IRIG-B is a kind of of IRIG serial codes, carries abundant information, and anti-interference is good, possesses international general-purpose interface.IRIG-B is widely used in fields such as electric power, telecommunications and national defence with the advantage of himself.
Though the technology of IRIG-B has obtained general application in China in recent years, in use also there are some problems.At first, be that timing tracking accuracy is low, the time service precision of present IRIG-B (DC) product also can only reach the us magnitude, can not satisfy growing time service precision demand.Secondly, the plenty of time synchronous device receives gps satellite signal at present, and gps system is controlled by the U.S., has huge potential safety hazard, is not suitable at electric power, and key areas such as telecommunications and national defence are used.
For solve IRIG-B in actual applications run into these problems, need to adopt new technical solution.At first adopt the high-speed figure treatment technology to improve timing tracking accuracy, utilize Big Dipper receiver module to receive Beidou satellite navigation system information, eliminate the potential safety hazard of using GPS to cause.
Summary of the invention
The purpose of this invention is to provide a kind of big-dipper satellite time synchronizing signal B code generating method and device, use Beidou satellite navigation system, eliminated the GPS potential safety hazard as time source.Adopt advanced Design of Digital Circuit scheme, improve B sign indicating number synchronization accuracy.
The present invention seeks to realize like this: the method that a kind of big-dipper satellite time synchronizing signal B sign indicating number takes place, it is characterized in that: described method step comprises:
A, receive the time source of Big Dipper satellite signal as the time synchronized clock;
B, temporal information are safeguarded to handle and are generated the DC B coded signal;
The DC B sign indicating number that c, utilization generate carries out amplitude modulation(PAM), generates the alternating-current B coded signal.
Described step a is: at first the Big Dipper satellite signal that Big Dipper receiving antenna is received amplifies and filtering, carry out the signal down coversion then, signal capture, tracking, demodulation etc. are handled and are obtained the big-dipper satellite text, Big Dipper text is carried out calculation process, output time information and benchmark second pulse signal;
Described step b is: 1. temporal information is judged; State to Big Dipper receiver module detects simultaneously, and when Big Dipper signal was unavailable, according to the temporal information that has received, maintenance time information also produced correct temporal information; 2. the frequency signal that utilizes local clock to shake is counted, and produces DC B the sign indicating number pulse signal and the distinct symbols control signal in required various cycles, inserts the timing code metamessage simultaneously, forms the DC B sign indicating number;
Described step c is: 1. adopt the DDS technology to generate sinusoidal signal, and the frequency signal that utilizes local clock to shake, the frequency that changes is the phase data of 1KHz, utilizes sine lookup table to generate the sinusoidal signal of 1KHz; 2. utilize the DC B coded signal that the signal of the sinusoidal signal of 1KHz is carried out amplitude modulation(PAM), can form the alternating-current B coded signal through behind the amplitude modulation(PAM).
In step b, the DC B coded signal is carried out level transform, export with difference form; In step c, adopt the transformer isolation method.
A kind of for implementing the custom-designed big dipper satellite synchronizing clock time signal B code generating means of this method, comprise receiver module, single-chip microcomputer, programmable logic chip, level transferring chip, D/A converting circuit, transformer and local clock shake, it is characterized in that: receiver module is a Big Dipper receiver module, Big Dipper receiver module receives Big Dipper satellite signal, and single-chip microcomputer is safeguarded temporal information and handled; Temporal information and pps pulse per second signal are input in the programmable logic chip, and in addition, the frequency that local clock shakes also is input in the programmable logic chip, generate the alternating-current B sign indicating number of DC B coded signal and digital form.
In described single-chip microcomputer, temporal information is transformed, form the temporal information of BCD form; And comprise correction module.
In described programmable logic chip, comprise DC B sign indicating number generation module and alternating-current B sign indicating number generation module.
DC B sign indicating number generation module comprises: time memory cell, code element is inserted the unit sum counter.
Alternating-current B sign indicating number generation module comprises: DDS, sine lookup table and amplitude modulation(PAM).
After described DC B sign indicating number generation module, connect level transferring chip, after described alternating-current B sign indicating number generation module, connect D/A converting circuit.
In D/A converting circuit, comprise the LC filtering circuit.
The advantage of invention is:
1, IRIG-B receives Big Dipper satellite signal, and triones navigation system is controlled fully by China, device safe;
2, the bucket satellite is positioned at geostationary orbit, does not relate between star and switching, and the time service system is good, the time service precision height;
3, the time processing part of IRIG-B has adopted the time maintenance technology, not only can judge the correctness of Big Dipper receiver module output time information, can also not receive under the situation of Big Dipper satellite signal, autonomous maintenance time, the correctness of the signal of the IRIG-B that assurance produces in the certain hour section, the availability of raising system;
4, adopt the DDS technology, keep the continuous of phase place, be easy to realize frequency, phase place and amplitude modulation(PAM), have the outstanding advantage of control able to programme;
5, in processing procedure, adopt modular design, each module is worked under the 1PPS of Big Dipper receiver module signal synchronously, and the synchronization accuracy of IRIG-B (DC) is better than 200ns, and the synchronization accuracy of IRIG-B (AC) is better than 10us, satisfies military standard.
Description of drawings
Fig. 1 is the theory diagram of method for designing of the present invention.
Fig. 2 is the schematic block circuit diagram of design apparatus of the present invention.
Fig. 3 is the DC B sign indicating number generation module principle block diagram among the FPGA of the present invention.
Fig. 4 is the alternating-current B sign indicating number generation module principle block diagram among the FPGA of the present invention.
Embodiment
The theory diagram of method for designing of the present invention as shown in Figure 1, its method step comprises:
A, receive the time source of Big Dipper satellite signal as the time synchronized clock;
B, temporal information are safeguarded to handle and are generated the DC B coded signal;
The DC B sign indicating number that c, utilization generate carries out amplitude modulation(PAM), generates the alternating-current B coded signal.
Described step a is: at first the Big Dipper satellite signal that Big Dipper receiving antenna is received amplifies and filtering, carry out the signal down coversion then, signal capture, tracking, demodulation etc. are handled and are obtained the big-dipper satellite text, Big Dipper text is carried out calculation process, output time information and benchmark second pulse signal;
Described step b is: 1. temporal information is judged, guaranteed the accuracy of time signal; State to Big Dipper receiver module 1 detects simultaneously, and when Big Dipper signal was unavailable, according to the temporal information that has received, maintenance time information also produced correct temporal information, strengthens the availability of time signal; 2. utilize shake 7 frequency signal of local clock to count, produce DC B the sign indicating number pulse signal and the distinct symbols control signal in required various cycles, insert the timing code metamessage simultaneously, form the DC B sign indicating number;
Described step c is: 1. adopt the DDS8 technology to generate sinusoidal signal, utilize shake 7 frequency signal of local clock, the frequency that changes is the phase data of 1KHz, utilizes sine lookup table 9 to generate the sinusoidal signal of 1KHz; DDS can carry out frequency modulation and phase modulation easily, produces various frequency signals, realizes simply the frequency accuracy height; 2. utilize the DC B coded signal that the signal of the sinusoidal signal of 1KHz is carried out amplitude modulation(PAM) 10, when the DC B sign indicating number was high level, the sinusoidal signal amplitude remained unchanged, when the DC B sign indicating number is low level, the sinusoidal signal amplitude is dwindled according to the modulation ratio parameter, can form the alternating-current B coded signal through behind the amplitude modulation(PAM) 10.
In step b, for driving force that strengthens the DC B coded signal and the anti-interference that improves signal, the DC B coded signal is carried out level transform, export with difference form; In step c, be the anti-interference of enhancing signal, cut off external signal equipment is disturbed, need isolate and impedance matching the alternating-current B coded signal.The present invention adopts the transformer isolation technology, in Signal Spacing, reaches the purpose of impedance matching.
The schematic block circuit diagram of design apparatus of the present invention as shown in Figure 2, it comprises: comprise receiver module, single-chip microcomputer 2, programmable logic chip 3, level transferring chip 4, D/A converting circuit 5, transformer 6 and local clock shake 7; Receiver module is a Big Dipper receiver module 1, and Big Dipper receiver module 1 receives Big Dipper satellite signal, and 2 pairs of temporal informations of single-chip microcomputer are safeguarded and handled; Temporal information and pps pulse per second signal are input in the programmable logic chip 3, and in addition, shake 7 frequency of local clock also is input in the programmable logic chip 3, generates the alternating-current B sign indicating number of DC B coded signal and digital form.
Big Dipper receiving element comprises Big Dipper antenna and Big Dipper receiver module 1.Big Dipper antenna is mainly finished the reception of satellite-signal and amplification, filtering.1 pair of satellite-signal of Big Dipper receiver module carry out that down coversion, despreading, demodulation, satellite message are handled and the time functions such as frequency marking is synthetic, thereby high precision pulse per second (PPS) time reference and temporal information are provided.
Time maintenance is handled and is finished in single-chip microcomputer 2 in the design.In time maintenance module, detect the duty of Big Dipper receiver module 1, guarantee the correctness of temporal information, and time format is changed.Big Dipper satellite signal just often according to the temporal information that provides, is kept high precision time synchronization according to satellite receiver module 1.When satellite-signal is unusual, in the certain hour section, keep a high precision time information output.Also adopted technology such as split-second precision maintenance in this unit, the serial temporal information that receives is adjudicated and handled, Time Created, maintenance mechanism guaranteed the correctness that output time is believed simultaneously, guaranteed the correctness of IRIG-B signal.Another major function of time maintenance processing unit is to carry out the time format conversion, and an absolute second information format conversion is become date Hour Minute Second time format and SBS days hour formats.
The sinusoidal signal of DC B sign indicating number generation module and alternating-current B sign indicating number takes place and amplitude modulation(PAM) 10 is realized in programmable logic chip 3.With difference form output, the differential signal anti-interference is good, long transmission distance through level transferring chip 4 backs for the DC B sign indicating number.The alternating-current B sign indicating number of the digital form that generates forms simulating signal through D/A converting circuit 5, is isolating back output through transformer 6.
DC B sign indicating number generation module principle block diagram as shown in Figure 3 comprises time memory cell 11, and code element is inserted unit 12 sum counters 13; Time memory cell 11 communicates with single-chip microcomputer 2, thereby obtains needed temporal information; In counter 13, utilize shake 7 frequency of local clock to count, counter 13 is synchronous by pulse per second (PPS), the byte address that produces is input to time memory cell 11, extracts information data sometime, provides 100Hz signal and 10Hz signal to insert unit 12 to code element simultaneously; Code element is inserted unit 12 and is counted generation code element address according to the 100Hz signal, extract the time code element of having carried out and having gone here and there conversion from time memory cell 11, and insert the distinctive mark code element in the position of determining, thereby form the DC B sign indicating number according to 10Hz and pps pulse per second signal.
The major function of DC B sign indicating number generation module is that time of reception is safeguarded the temporal information that processing unit sends, and generates the DC B code data of serial according to certain rule.The DC B sign indicating number comprises three kinds of different controlled flag: 2ms, and 5ms and 8ms come expression time information.The DC B sign indicating number realizes that in programmable logic chip data processing speed is fast, the synchronization accuracy height of DC B sign indicating number.
The DC B coded signal driving force that level conversion is primarily aimed at programmable logic chip FPGA output is not strong, and shortcomings such as anti-interference difference are used level transferring chip 4, and the DC B coded signal is converted to the RS-422 differential level from Transistor-Transistor Logic level.
Alternating-current B sign indicating number generation module principle block diagram as shown in Figure 4, it adopts the DDS8 technology, it is direct digital frequency synthesis technology, it is the phase information of 1ms that the correct frequency word generation cycle is set, through the 1KHz sinusoidal signal of sine lookup table 9 formation digital forms, utilize DC B coded signal offset of sinusoidal signal to carry out the digital form that amplitude modulation(PAM) 10 obtains the alternating-current B coded signal then.
The modulation ratio of alternating-current B sign indicating number and amplitude can be obtained by controlled variable, and modulation ratio can realize the continuous setting of 2:1 to 6:1, and the amplitude setting can be from 0.5V to 10V, and quantizing scale is 0.5V.
D/A converting circuit 5 can realize the B coded signal from the Digital AC conversion of signals to simulating signal.Because in transfer process, there is quantization error, comprise noise signal in the simulating signal, in design, adopt the LC filtering circuit to filter away noise signal.
Adopt transformer 6 buffer circuit isolating exterior signals in the signal isolation circuit, the output of alternating-current B sign indicating number balance.
Claims (10)
1, a kind of big dipper satellite synchronizing clock time signal B code generating method is characterized in that: described method step comprises:
A, receive the time source of Big Dipper satellite signal as the time synchronized clock;
B, temporal information are safeguarded to handle and are generated the DC B coded signal;
The DC B sign indicating number that c, utilization generate carries out amplitude modulation(PAM), generates the alternating-current B coded signal.
2, big dipper satellite synchronizing clock time signal B code generating method according to claim 1 is characterized in that:
Described step a is: at first the Big Dipper satellite signal that Big Dipper receiving antenna is received amplifies and filtering, carry out the signal down coversion then, signal capture, tracking, demodulation etc. are handled and are obtained the big-dipper satellite text, Big Dipper text is carried out calculation process, output time information and benchmark second pulse signal;
Described step b is: 1. temporal information is judged; State to Big Dipper receiver module (1) detects simultaneously, and when Big Dipper signal was unavailable, according to the temporal information that has received, maintenance time information also produced correct temporal information; 2. utilize the shake frequency signal of (7) of local clock to count, produce DC B the sign indicating number pulse signal and the distinct symbols control signal in required various cycles, insert the timing code metamessage simultaneously, form the DC B sign indicating number;
Described step c is: 1. adopt DDS (8) technology to generate sinusoidal signal, utilize the shake frequency signal of (7) of local clock, the frequency that changes is the phase data of 1KHz, utilizes sine lookup table (9) to generate the sinusoidal signal of 1KHz; 2. utilize the DC B coded signal that the signal of the sinusoidal signal of 1KHz is carried out amplitude modulation(PAM) (10), through forming the alternating-current B coded signal behind the amplitude modulation(PAM) (10).
3, big dipper satellite synchronizing clock time signal B code generating method according to claim 2 is characterized in that: in step b, the DC B coded signal is carried out level transform, export with difference form; In step c, adopt the transformer isolation method.
4, a kind of as claimed in claim 1 for implementing the custom-designed big dipper satellite synchronizing clock time signal B code generating means of this method, comprise receiver module, single-chip microcomputer (2), programmable logic chip (3), level transferring chip (4), D/A converting circuit (5), transformer (6) and local clock shake (7), it is characterized in that: receiver module is Big Dipper receiver module (1), Big Dipper receiver module (1) receives Big Dipper satellite signal, and single-chip microcomputer (2) is safeguarded temporal information and handled; Temporal information and pps pulse per second signal are input in the programmable logic chip (3), and in addition, the shake frequency of (7) of local clock also is input in the programmable logic chip (3), generates the alternating-current B sign indicating number of DC B coded signal and digital form.
5, big dipper satellite synchronizing clock time signal B code generating means according to claim 4 is characterized in that: in described single-chip microcomputer (2), temporal information is transformed, form the temporal information of BCD form; And comprise correction module.
6, big dipper satellite synchronizing clock time signal B code generating means according to claim 4 is characterized in that: comprise DC B sign indicating number generation module and alternating-current B sign indicating number generation module in described programmable logic chip (3).
7, big dipper satellite synchronizing clock time signal B code generating means according to claim 6 is characterized in that: described DC B sign indicating number generation module comprises: time memory cell (11), code element is inserted unit (12) sum counter (13).
8, big dipper satellite synchronizing clock time signal B code generating means according to claim 6 is characterized in that: described alternating-current B sign indicating number generation module comprises: DDS (8), sine lookup table (9) and amplitude modulation(PAM) (10).
9, big dipper satellite synchronizing clock time signal B code generating means according to claim 7 is characterized in that: connect level transferring chip (4) after described DC B sign indicating number generation module, connect D/A converting circuit (5) after described alternating-current B sign indicating number generation module.
10, according to claim 4 or 9 described big dipper satellite synchronizing clock time signal B code generating meanss, it is characterized in that: in described D/A converting circuit (5), comprise the LC filtering circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200710189732XA CN101398666A (en) | 2007-09-30 | 2007-09-30 | Big dipper satellite synchronizing clock time signal B code generating method and apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200710189732XA CN101398666A (en) | 2007-09-30 | 2007-09-30 | Big dipper satellite synchronizing clock time signal B code generating method and apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101398666A true CN101398666A (en) | 2009-04-01 |
Family
ID=40517271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA200710189732XA Pending CN101398666A (en) | 2007-09-30 | 2007-09-30 | Big dipper satellite synchronizing clock time signal B code generating method and apparatus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101398666A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102243475A (en) * | 2010-05-13 | 2011-11-16 | 郑州威科姆科技股份有限公司 | Compass-based method for generating Germany long-wave near Frankfurt 77.5 KHz (DCF77) time code |
| CN101871976B (en) * | 2009-04-24 | 2012-06-20 | 郑州威科姆科技股份有限公司 | Power clock detecting device |
| CN102901944A (en) * | 2012-09-27 | 2013-01-30 | 中国电力科学研究院 | B code clock synchronization device for field calibration of electronic mutual inductors |
| CN103684730A (en) * | 2012-09-07 | 2014-03-26 | 北京旋极信息技术股份有限公司 | Time synchronization method |
| CN104270220A (en) * | 2014-10-20 | 2015-01-07 | 上海远景数字信息技术有限公司 | Method for analyzing IRIG-B time code element |
| CN104320237A (en) * | 2014-10-10 | 2015-01-28 | 宁波三星电气股份有限公司 | Second pulse coding timing method |
| CN104460310A (en) * | 2014-11-19 | 2015-03-25 | 广西大学 | Time service device based on Beidou 2nd generation satellite system |
| CN104615101A (en) * | 2014-12-16 | 2015-05-13 | 浙江大丰实业股份有限公司 | Stage multi-dimensional system synchronous control method |
| CN108121678A (en) * | 2017-12-25 | 2018-06-05 | 四川九洲空管科技有限责任公司 | A kind of FPGA data processing method and system based on the optimization of novel C HSI interfaces |
| CN110109157A (en) * | 2019-06-12 | 2019-08-09 | 中国地震局地震预测研究所 | A kind of B code generating unit and device |
| CN111193514A (en) * | 2019-10-25 | 2020-05-22 | 电子科技大学 | High-synchronization-precision IRIG-B encoder |
| CN113341687A (en) * | 2021-06-24 | 2021-09-03 | 中国船舶重工集团公司第七0七研究所 | High-precision self-correcting IRIG-B (AC) code modulation device and method |
| CN113934132A (en) * | 2021-10-12 | 2022-01-14 | 湖南师范大学 | High-precision time synchronization system and synchronization method based on Beidou clock signal |
| CN115453850A (en) * | 2022-08-05 | 2022-12-09 | 福建星云电子股份有限公司 | Time synchronization method, system, equipment and medium for energy storage converter |
-
2007
- 2007-09-30 CN CNA200710189732XA patent/CN101398666A/en active Pending
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101871976B (en) * | 2009-04-24 | 2012-06-20 | 郑州威科姆科技股份有限公司 | Power clock detecting device |
| CN102243475B (en) * | 2010-05-13 | 2012-11-21 | 郑州威科姆科技股份有限公司 | Compass-based method for generating Germany long-wave near Frankfurt 77.5 KHz (DCF77) time code |
| CN102243475A (en) * | 2010-05-13 | 2011-11-16 | 郑州威科姆科技股份有限公司 | Compass-based method for generating Germany long-wave near Frankfurt 77.5 KHz (DCF77) time code |
| CN103684730A (en) * | 2012-09-07 | 2014-03-26 | 北京旋极信息技术股份有限公司 | Time synchronization method |
| CN102901944A (en) * | 2012-09-27 | 2013-01-30 | 中国电力科学研究院 | B code clock synchronization device for field calibration of electronic mutual inductors |
| CN104320237B (en) * | 2014-10-10 | 2017-12-12 | 宁波三星智能电气有限公司 | A kind of pulse per second (PPS) encodes setting means |
| CN104320237A (en) * | 2014-10-10 | 2015-01-28 | 宁波三星电气股份有限公司 | Second pulse coding timing method |
| CN104270220A (en) * | 2014-10-20 | 2015-01-07 | 上海远景数字信息技术有限公司 | Method for analyzing IRIG-B time code element |
| CN104270220B (en) * | 2014-10-20 | 2018-07-20 | 国网宁夏电力公司电力科学研究院 | A method of for analyzing IRIG-B time symbols |
| CN104460310A (en) * | 2014-11-19 | 2015-03-25 | 广西大学 | Time service device based on Beidou 2nd generation satellite system |
| CN104615101A (en) * | 2014-12-16 | 2015-05-13 | 浙江大丰实业股份有限公司 | Stage multi-dimensional system synchronous control method |
| CN104615101B (en) * | 2014-12-16 | 2017-02-22 | 浙江大丰实业股份有限公司 | Stage multi-dimensional system synchronous control method |
| CN108121678A (en) * | 2017-12-25 | 2018-06-05 | 四川九洲空管科技有限责任公司 | A kind of FPGA data processing method and system based on the optimization of novel C HSI interfaces |
| CN108121678B (en) * | 2017-12-25 | 2019-11-12 | 四川九洲空管科技有限责任公司 | A kind of FPGA data processing method and system based on the optimization of novel C HSI interface |
| CN110109157A (en) * | 2019-06-12 | 2019-08-09 | 中国地震局地震预测研究所 | A kind of B code generating unit and device |
| CN111193514A (en) * | 2019-10-25 | 2020-05-22 | 电子科技大学 | High-synchronization-precision IRIG-B encoder |
| CN113341687A (en) * | 2021-06-24 | 2021-09-03 | 中国船舶重工集团公司第七0七研究所 | High-precision self-correcting IRIG-B (AC) code modulation device and method |
| CN113934132A (en) * | 2021-10-12 | 2022-01-14 | 湖南师范大学 | High-precision time synchronization system and synchronization method based on Beidou clock signal |
| CN113934132B (en) * | 2021-10-12 | 2022-05-27 | 湖南师范大学 | High-precision time synchronization system and synchronization method based on Beidou clock signal |
| CN115453850A (en) * | 2022-08-05 | 2022-12-09 | 福建星云电子股份有限公司 | Time synchronization method, system, equipment and medium for energy storage converter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101398666A (en) | Big dipper satellite synchronizing clock time signal B code generating method and apparatus | |
| CN205375018U (en) | Can tame rubidium atomic clock synchronized clock equipment based on satellite time service | |
| CN204964762U (en) | General big dipper positioning orientation time service equipment of radar | |
| CN102243475B (en) | Compass-based method for generating Germany long-wave near Frankfurt 77.5 KHz (DCF77) time code | |
| CN104570021A (en) | GPS simulation method and system based on positioning and time service of Beidou satellite | |
| CN101493674B (en) | B code demodulating and decoding method and apparatus thereof | |
| CN203164620U (en) | High precision time synchronization device | |
| CN108536003A (en) | Accurate time transmission system and method and time service service system | |
| CN101770016B (en) | GPS time service signal generator based on Beidou satellite | |
| CN205017341U (en) | Synchronous timing device of multi -mode | |
| CN210428114U (en) | Multi-system time source redundant timing equipment | |
| CN101834684A (en) | GPS clock synchronization method for distributed acoustic positioning system | |
| CN102830611B (en) | Time source | |
| CN202257089U (en) | Time synchronization device | |
| CN202998116U (en) | Pulse-per-second and IRIG-B direct-current code clock synchronization circuit and equipment | |
| CN107037722A (en) | A kind of time terminal | |
| CN101545965B (en) | GPS synchronous IRIG-B time code generator | |
| CN202217149U (en) | High-precision electric time synchronizer | |
| CN100582970C (en) | B-code demodulation method and demodulator | |
| CN201369712Y (en) | IRIG-B time code generator with GPS synchronization | |
| CN102255682B (en) | Method and device for converting precision time protocol clock into inter-range instrumentation group B (IRIG-B) code | |
| CN102938677A (en) | Shore station time synchronization method for undersea observational network | |
| CN201450508U (en) | Time synchronizer | |
| CN106209090B (en) | A kind of combining unit pulse per second (PPS) synchronism output system and method based on FPGA | |
| CN203708224U (en) | Multipurpose serial time code decoder |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20090401 |