CN101308480A - Method for host serial simultaneously connecting multiple asynchronous serial equipment - Google Patents
Method for host serial simultaneously connecting multiple asynchronous serial equipment Download PDFInfo
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Abstract
The invention discloses a method for a host serial port to simultaneously connect a plurality of asynchronous serial devices, comprising the following steps: the step 1 is that the sending terminal and the receiving terminal of each serial device are accessed to a specific port; the step 2 is that a TX combiner transmits the data sent by each serial device to the receiving terminal of the host serial port; the step 3 is that the receiving terminal of the host serial port sends the analyzed data to each serial processing module of the host computer; the step 4 is that the host serial port sends the awaiting data to a receiving buffer of a programmable RX splitter; the step 5 is that the programmable RX splitter sends the data blocks to a buffer of a target port; the step 6 is that the target port resends the data in the buffer to each serial device, so as to achieve the purpose that a host computer can be simultaneously connected with a plurality of asynchronous serial devices or chips with same or different transmission rate through asynchronous serial ports for data transmission.
Description
Technical field
The present invention relates to the asynchronous communication serial ports of main frame, particularly a kind of serial port of host computer connects the method for a plurality of asynchronous serial port equipment simultaneously.
Background technology
In the actual Application and Development, the asynchronous communication serial ports is widely used in fields such as communication, control as the advantages of simplicity and high efficiency general-purpose interface.Such as, in handheld device, bluetooth, satellite positioning navigation (GlobalPositioning System, abbreviation GPS), Wireless Fidelity (Wireless Fidelity, be called for short WIFI) etc. module Asynchronous Serial Interface (Universal Asynchronous SerialPort all is provided, be called for short UART) with the continuous mode of the serial ports of baseband chip, carry out operations such as Communication Control.The serial ports number that baseband chip provided is normally limited, and everybody wishes the functional module that more has serial interface is integrated in the product.As everyone knows,, must disconnect current serial ports and connect, could connect with new serial equipment when asynchronous serial port and certain serial equipment of a main frame connects.
Summary of the invention
For overcoming the deficiency of above-mentioned prior art, the technical problem to be solved in the present invention provides the method that a kind of serial port of host computer connects a plurality of asynchronous serial port equipment simultaneously.
For solving the problems of the technologies described above, technical scheme of the present invention is:
A kind of serial port of host computer connects the method for a plurality of asynchronous serial port equipment simultaneously, may further comprise the steps:
Step 1: the designated port that the transmitting terminal of each serial equipment is linked into TX combiner able to programme, the receiving end of described each serial equipment is linked into the designated port of RX shunt able to programme, and described designated port is specified by the location register of described TX combiner able to programme and RX shunt;
Step 2: sending data link, the data that TX combiner able to programme is sent each serial equipment, process is also changeed serializer circuit, is combined into circuit-switched data stream, and is synchronized to the assigned timeslot of this combiner clock, sends to the receiving end of serial port of host computer;
Step 3: the serial port of host computer receiving end receives the data that described TX combiner able to programme is sent, and is kept in the reception buffer of serial port of host computer, through data parsing, the byte of separator well is sent to each serial ports processing module of main frame;
Step 4: receiving data link, the serial port of host computer transmitting terminal, earlier the data in the transmission buffer of serial port of host computer are added control byte from beginning to end, belong to which serial equipment, again will these data to be sent send to the reception buffer of RX shunt able to programme to identify these data;
Step 5: RX shunt able to programme according to the control byte of this data block, sends to data block in the impact damper of destination interface after receiving the data block that serial port of host computer sends;
Step 6: described destination interface basis transfer rate separately re-sends to each serial equipment with the data in the impact damper.
The transfer rate of the serial equipment in the step 1 is identical or different.
Serial equipment in the step 1 has several.
The value of the eight bit register of described TX combiner able to programme and RX shunt is by the host chip setting, and the value of this eight bit register is used for representing that described combiner or which port of shunt are enabled.
The transfer rate of serial port of host computer is greater than or equals the serial equipment transfer rate sum that inserts.
When needs increase new serial equipment, the idle port that the transmitting terminal and the receiving end of new serial equipment is linked into TX combiner able to programme, RX shunt respectively.
In the described step 2 and to change serializer circuit be shift register
Compared with prior art, the invention has the beneficial effects as follows:
The present invention is by the matching design of hardware and software, the method that provides a kind of serial port of host computer to connect a plurality of asynchronous serial port equipment simultaneously, thus realized that a main frame connects with the asynchronous serial port equipment of a plurality of similar and different transfer rates or chip simultaneously by asynchronous serial port and transmits data.It is limited to be specially adapted to serial port of host computer, needs the more design proposal of serial equipment that connects.
Description of drawings
Fig. 1 is the hardware frame figure that a serial port of host computer connects four serial equipments simultaneously.
Fig. 2 is that a serial port of host computer connects the extension framework figure more than four serial equipments simultaneously.
Fig. 3 is the byte output of TX combiner able to programme of the serial port of host computer serial equipment that connects four identical traffic speed simultaneously and the corresponding relation figure of clock.
Fig. 4 is the process flow diagram of serial port of host computer serial port of host computer resolution data when connecting the serial equipment of four identical traffic speed simultaneously.
Fig. 5 is the corresponding relation figure of serial port of host computer TX combiner byte output able to programme and clock when connecting the serial equipment of 4 different transmission rates simultaneously.
Fig. 6 is that serial port of host computer is handled the workflow diagram that receives data.
Fig. 7 is the workflow diagram that serial port of host computer sends data.
Embodiment
Specific embodiments of the present invention are further described in detail below in conjunction with drawings and Examples, but should not limit protection scope of the present invention with this.
See also Fig. 1.Fig. 1 is the hardware frame figure that a serial port of host computer connects four serial equipments simultaneously, can realize a main frame asynchronous serial port and maximum four different transmission rates asynchronous serial port equipment or chip connects and transceive data.The transmitting terminal of four serial equipments links to each other with four input ports of TX combiner able to programme respectively, the data of this TX combiner able to programme and the output terminal that changes serializer circuit link to each other with the input end of the reception buffer of serial port of host computer, the output terminal of the transmission buffer of described serial port of host computer links to each other with the input end of the reception buffer of RX shunt able to programme, and four output ports of this RX shunt able to programme link to each other with the receiving end of four serial equipments.
The transfer rate of serial port of host computer is made as a fixed value, and this value is greater than or equals the serial equipment transfer rate sum that inserts.Such as, 4 serial equipment transfer rates of access all are 115200bit/s, then the transfer rate of serial port of host computer is 115200*4bit/s, i.e. 460800bit/s.The clock (hereinafter to be referred as CLOCK) that offers TX combiner able to programme and RX shunt equals the transmission rate value of serial port of host computer, such as, 115200*4Hz, i.e. 460800Hz.The value of 8 location registers of TX combiner able to programme and RX shunt is by the host chip setting, and the value of this eight bit register is used for representing which port is enabled.Such as, 0b1010,0000 expression port 0 and port 2 are enabled, and just, receive port 0 to serial equipment 0, and serial equipment 2 is received port 2.
See also Fig. 3, Fig. 3 is the byte output of TX combiner able to programme of the serial port of host computer serial equipment that connects four identical traffic speed simultaneously and the corresponding relation figure of clock.The transfer rate of supposing TX combiner equipment 0,1,2,3 port connected equipments all is 115200bit/s, the data that equipment 0 port is received are represented with A, the data that equipment 1 port is received represent that with B the data that equipment 2 ports are received represent that with C the data that equipment 3 ports are received are represented with D.Sometime, the data that the TX combiner is received are ABCD, and by also changeing string, the 0th CLOCK of TX combiner exports A, the 1st CLOCK output B, and the 2nd CLOCK exports C, the 3rd CLOCK output D.The byte format that serial port of host computer is whenever received is ABCDABCD successively from a high position to the low level, uses high-order in preceding principle here.The byte of receiving is saved in reception buffer (impact damper is hereinafter to be referred as BUFFER) lining, the byte that per 4 bytes just can component devices 0,1,2,3.
See also Fig. 4, Fig. 4 is a serial port of host computer when connecting the serial equipment of four identical traffic speed simultaneously, the process flow diagram of serial port of host computer resolution data.At first, the reception BUFFER of serial port of host computer must whenever receive 4 bytes, could correctly resolve the byte that serial equipment 0,1,2,3 sends.Suppose that sometime the reception BUFFER of serial port of host computer has received A0B0C0D0A1B1C1D1, A2B2C2D2A3B3C3D3, A4B4C4D4A5B5C5D5, four bytes of A6B6C6D6A7B7C7D7, each byte is from Bit7 to Bit0 here; Then, through data parsing, the 7th and the 3rd with each byte extracts, form the byte A0A1A2A3A4A5A6A7 that serial equipment 0 sends, the 6th and the 2nd with each byte extracts, and forms the byte that serial equipment 1 sends, B0B1B2B3B4B5B6B7, similarly, can extract the byte that serial equipment 2 and serial equipment 3 send; In the 3rd step,, send to each serial equipment handling procedure respectively with the byte that parses.
See also Fig. 5, Fig. 5 is the corresponding relation of serial port of host computer TX combiner byte output able to programme and clock when connecting the serial equipment of 4 different transmission rates simultaneously.Suppose the transfer rate difference of TX combiner equipment 0,1,2,3 port connected equipments, equipment 0 is 115200bit/s, equipment 1 is 115200bit/s/2=57600bit/s, equipment 2 is 115200bit/s, equipment 3 is that the data that 115200bit/s/2=57600bit/s. equipment 0 port is received are represented with A, the data that equipment 1 port is received represent that with B the data that equipment 2 ports are received represent that with C the data that equipment 3 ports are received are represented with D.By also changeing string, the CLOCK of corresponding TX combiner exports, and the byte format that serial port of host computer is whenever received is A0C0ABCD from a high position to the low level.In the reception BUFFER that the byte of receiving is saved in, resolve in per 4 bytes that equipment 0 and each byte of 2 need be received from serial port of host computer, resolve in per 8 bytes that equipment 1 and each byte of 3 need be received from serial port of host computer.
Need to prove that the transfer rate of TX combiner connected equipment should be the 115200bit/s integral multiple, or can be divided exactly by 115200bit/s.Like this, can be easily with the time slot of data allocations to CLOCK.And the software analysis mode of serial port of host computer receiving end will pre-set.
If with more different transmission rates asynchronous serial port equipment or chip connects and transceive data, can be with reference to figure 2.Fig. 2 serial port of host computer connects the extension framework figure more than four serial equipments simultaneously.As Fig. 2, first order RX shunt/TX combiner respectively connects port 0, port one, port 2 and port 3; Second level RX shunt is drawn from the port 0 of first order RX shunt and is connected 4 serial equipments, and second level TX combiner is connected to the port 0 of first order TX combiner.The transfer rate of supposing serial port of host computer is 115200*4bit/s, i.e. 460800bit/s.The transfer rate of distributing to each serial equipment of the first order is 115200bit/s.The transfer rate of distributing to second level serial equipment is 115200/4bit/s, i.e. 26800bit/s.Just equipment 0.0,0.1, and 0.2,0.3 transfer rate is 26800bit/s, equipment 1,2, and 3 transfer rates are 115200bit/s.Suppose equipment 1,2,3 port datas are respectively A, B, and C, equipment 0.0,0.1,0.2,0.3 port data is respectively D, E, F, G.By also changeing string, the CLOCK of corresponding TX combiner exports, and the data layout that serial port of host computer is received is DABC from a high position to the low level, EABC, FABC, GABC, DABC, EABC, FABC, GABC.The byte of receiving is saved in the BUFFER, equipment 1,2,3 bytes that send need be resolved from per 4 bytes that serial port of host computer is received, equipment 0.0,0.1,0.2,0.3 byte that sends need be resolved from per 16 bytes that serial port of host computer is received.
See also Fig. 6 and Fig. 7.Fig. 6 is that serial port of host computer is handled the workflow diagram that receives data.Fig. 7 is the workflow diagram that serial port of host computer sends data.Each serial equipment sends data to same serial port of host computer by TX combiner able to programme, and the process flow diagram that the data after will resolving send to each serial ports processing module is seen Fig. 6.The workflow that serial equipment receives data is, is positioned at the processing module of serial port of host computer transmitting terminal, belong to which serial equipment to the additional from beginning to end special control byte of the data block of issuing serial ports to indicate this data block.The data block that the main frame that RX shunt able to programme receives is sent according to the control byte of this data block, is judged which serial equipment is this data block belong to, and this data content is dealt into port BUFFER.Each port according to transfer rate separately separately the data in the BUFFER send to each serial equipment.Serial port of host computer of the present invention connects the method for a plurality of asynchronous serial port equipment simultaneously, specifically may further comprise the steps:
Step 1: the designated port that the transmitting terminal of each serial equipment is linked into TX combiner able to programme, the receiving end of described each serial equipment is linked into the designated port of RX shunt able to programme, and described designated port is specified by the location register of described TX combiner able to programme and RX shunt;
Step 2: sending data link, the data that TX combiner able to programme is sent each serial equipment, process is also changeed serializer circuit, shift register just, be combined into circuit-switched data stream, and be synchronized to the assigned timeslot of this combiner clock, send to the receiving end of serial port of host computer;
Step 3: the serial port of host computer receiving end receives the data that described TX combiner able to programme is sent, and is kept in the reception buffer of serial port of host computer, through data parsing, the byte of separator well is sent to each serial ports processing module of main frame.The principle of data parsing is that according to each serial equipment speed, corresponding in advance each the serial equipment data of the time slot of host C LOCK according to the byte rule of detachment that has configured, send to the byte of separator well each serial ports processing module of main frame.
Serial port of host computer receiving end data parsing step is as follows,
At first, important affair is known the transfer rate of each serial equipment earlier.With the simplest a kind of situation for example, suppose, 4 serial equipments are arranged, and serial equipment 0,1,2,3 transfer rates are identical, and the data that equipment 0 port is received represent that with A the data that equipment 1 port is received are represented with B, the data that equipment 2 ports are received represent that with C the data that equipment 3 ports are received are represented with D.Serial port of host computer need receive A0B0C0D0A1B1C1D1, and totally four bytes (each byte from Bi t 7 to Bit0) could complete resolution data for A2B2C2D2A3B3C3D3, A4B4C4D4A5B5C5D5, A6B6C6D6A7B7C7D7.
Then, in serial port of host computer Interrupt Process function, each BIT position of each byte that serial port of host computer is received extracts respectively, by shifting function, forms new data byte, that is, and and A, B, C, D.Such as, serial port of host computer receives first byte, and A0B0C0D0A1B1C1D1 extracts the 7th and the 3rd of this byte, and with 3 of the 3rd lts, just obtains BIT7 and the BIT6 of data byte A.Similar operations, serial port of host computer need receive 4 bytes, and through extracting and shifting function, could form data byte A, B, C, D.
At last, with data byte A, B, C, D send to corresponding serial ports processing module.
Step 4: receiving data link, the serial port of host computer transmitting terminal, earlier the data in the transmission buffer of serial port of host computer are added control byte from beginning to end, belong to which serial equipment, again will these data to be sent send to the reception buffer of RX shunt able to programme to identify these data;
Step 5: RX shunt able to programme according to the control byte of this data block, sends to data block in the impact damper of destination interface after receiving the data block that serial port of host computer sends;
Step 6: described destination interface basis transfer rate separately re-sends to each serial equipment with the data in the impact damper.
Serial port of host computer transmitting terminal data processing step is as follows,
At first, need the opening flag of a data block of predefined, which serial equipment sign is this data block belong to, data block contents, data block ending sign.
Then, each serial ports handling procedure becomes data block according to definition with content packaging to be sent, is put in the serial ports transmit queue.
At last, serial ports sends to the data in the formation in the impact damper Buffer of RX shunt, unpacks and be distributed to each serial ports treatment facility by the RX shunt.
(corresponding 16 systems are 0x41, and 0x54 is 0x0d) to serial equipment 0 to suppose will to send character string " AT " by host side serial equipment 0 handling procedure, handle by said procedure, the word string that the RX shunt receives is exactly (0xF9,0xF9,0xF9,0x10,0x41,0x54,0x0d, 0xE9,0xE9,0xE9).The RX shunt just can extract and send to serial equipment 0 with character string " AT " according to opening flag, device number, the ending identifier of data block.
The present invention has realized that by the matching design of hardware and software serial port of host computer connects the method for a plurality of asynchronous serial port equipment simultaneously.When needs increased new serial equipment, the idle port that the transmitting terminal and the receiving end of new serial equipment is linked into TX combiner able to programme, RX shunt respectively got final product.
The above is preferred embodiment of the present invention only, is not to be used for limiting practical range of the present invention.Be that all equivalences of doing according to the content of the present patent application claim change and modification, all should be technology category of the present invention.
Claims (7)
1, a kind of serial port of host computer connects the method for a plurality of asynchronous serial port equipment simultaneously, it is characterized in that this method may further comprise the steps:
Step 1: the designated port that the transmitting terminal of each serial equipment is linked into TX combiner able to programme, the receiving end of described each serial equipment is linked into the designated port of RX shunt able to programme, and described designated port is specified by the location register of described TX combiner able to programme and RX shunt;
Step 2: sending data link, the data that TX combiner able to programme is sent each serial equipment, process is also changeed serializer circuit, is combined into circuit-switched data stream, and is synchronized to the assigned timeslot of this combiner clock, sends to the receiving end of serial port of host computer;
Step 3: the serial port of host computer receiving end receives the data that described TX combiner able to programme is sent, and is kept in the reception buffer of serial port of host computer, through data parsing, the byte of separator well is sent to each serial ports processing module of main frame;
Step 4: receiving data link, the serial port of host computer transmitting terminal, earlier the data in the transmission buffer of serial port of host computer are added control byte from beginning to end, belong to which serial equipment, again will these data to be sent send to the reception buffer of RX shunt able to programme to identify these data;
Step 5: RX shunt able to programme according to the control byte of this data block, sends to data block in the impact damper of destination interface after receiving the data block that serial port of host computer sends;
Step 6: described destination interface basis transfer rate separately re-sends to each serial equipment with the data in the impact damper.
2, serial port of host computer according to claim 1 connects the method for a plurality of asynchronous serial port equipment simultaneously, it is characterized in that the transfer rate of the serial equipment in the step 1 is identical or different.
3, serial port of host computer according to claim 1 and 2 connects the method for a plurality of asynchronous serial port equipment simultaneously, it is characterized in that the serial equipment in the step 1 has several.
4, serial port of host computer according to claim 1 connects the method for a plurality of asynchronous serial port equipment simultaneously, the value of eight bit register that it is characterized in that described TX combiner able to programme and RX shunt is by the host chip setting, and the value of this eight bit register is used for representing that described combiner or which port of shunt are enabled.
5, serial port of host computer according to claim 1 connects the method for a plurality of asynchronous serial port equipment simultaneously, and the transfer rate that it is characterized in that serial port of host computer is greater than or equals the serial equipment transfer rate sum that inserts.
6, serial port of host computer according to claim 1 connects the method for a plurality of asynchronous serial port equipment simultaneously, it is characterized in that when needs increase new serial equipment the idle port that the transmitting terminal and the receiving end of new serial equipment is linked into TX combiner able to programme, RX shunt respectively.
7, serial port of host computer according to claim 1 connects the method for a plurality of asynchronous serial port equipment simultaneously, it is characterized in that in the described step 2 and to change serializer circuit be shift register.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102202165A (en) * | 2010-03-23 | 2011-09-28 | 新奥特（北京）视频技术有限公司 | Method for receiving serial port data of real-time caption broadcasting system and receiving terminal |
| CN103116561A (en) * | 2011-11-17 | 2013-05-22 | 凹凸电子（武汉）有限公司 | Digital signal receiving and sending device, method and electric vehicle system |
| CN103530259A (en) * | 2013-10-21 | 2014-01-22 | 湖南强军科技有限公司 | Method, device and system for serial data clock-domain-crossing exchange of geophysical instrument |
| CN107066412A (en) * | 2017-05-27 | 2017-08-18 | 梦孚（上海）教育科技有限公司 | A kind of telecommunication circuit and its method |
| CN107885691A (en) * | 2017-11-21 | 2018-04-06 | 迈普通信技术股份有限公司 | Serial data transmission method, distributed apparatus and main frame |
| CN108509362A (en) * | 2018-04-11 | 2018-09-07 | 济南浪潮高新科技投资发展有限公司 | A kind of serial port adapter |
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2008
- 2008-06-18 CN CNB2008100391175A patent/CN100570588C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102202165A (en) * | 2010-03-23 | 2011-09-28 | 新奥特（北京）视频技术有限公司 | Method for receiving serial port data of real-time caption broadcasting system and receiving terminal |
| CN103116561A (en) * | 2011-11-17 | 2013-05-22 | 凹凸电子（武汉）有限公司 | Digital signal receiving and sending device, method and electric vehicle system |
| CN103530259A (en) * | 2013-10-21 | 2014-01-22 | 湖南强军科技有限公司 | Method, device and system for serial data clock-domain-crossing exchange of geophysical instrument |
| CN103530259B (en) * | 2013-10-21 | 2016-03-30 | 湖南强军科技有限公司 | The cross clock domain serial data exchange method of geophysical instrument, Apparatus and system |
| CN107066412A (en) * | 2017-05-27 | 2017-08-18 | 梦孚（上海）教育科技有限公司 | A kind of telecommunication circuit and its method |
| CN107066412B (en) * | 2017-05-27 | 2023-05-02 | 梦孚（上海）教育科技有限公司 | Communication circuit and method thereof |
| CN107885691A (en) * | 2017-11-21 | 2018-04-06 | 迈普通信技术股份有限公司 | Serial data transmission method, distributed apparatus and main frame |
| CN108509362A (en) * | 2018-04-11 | 2018-09-07 | 济南浪潮高新科技投资发展有限公司 | A kind of serial port adapter |
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Effective date of registration: 20110221 Address after: 200001 Shanghai City, Huangpu District Beijing East Road No. 668 building C room 715 Patentee after: SHANGHAI MICROELECTRONIC DESIGN Co.,Ltd. Address before: 314006, No. 777, Middle South Road, Nanhu District, Zhejiang, Jiaxing (Jiaxing science and technology city) Patentee before: WINGTECH Group Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091216 Termination date: 20120618 |