CN101192165B - Master-slave mode multiprocessor system and software version loading method - Google Patents
Master-slave mode multiprocessor system and software version loading method Download PDFInfo
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Abstract
The present invention discloses a software version loading method and comprises the following procedures that: the first step: a main processor carries out a bootstrap program of a bootstrap memory to initialize the main processor and the relevant peripheral circuit interface; the second procedure: relevant contents are downloaded from a network management version server by the main processor and stored in a program memory of the main processor; the third procedure: the main processor sends reset control signals to one or a plurality of slave processors and a relevant program version needed by each processor is read to a corresponding bootstrap program memory through a bus-mastering switch; the fourth procedure: the main processor and the slave processors respectively start respective function and task; the fifth procedure: the main procedure and the slave procedures establish a master-slave communication relation in order that the main processor monitors and manages the operating condition of the slave processors. In addition, the present invention also provides a software version loading system, reduces the complexity of the circuit and is convenient to load, upgrade, maintain and manage the software version.
Description
Technical field
The present invention relates to the embedded system field of master-slave mode multiprocessor, and especially, relate to a kind of master-slave mode multiprocessor system and software version loading method.
Background technology
In large-scale communication apparatus of modern times, equipment even embedded system on a veneer in equipment often need to be designed to master-slave mode multiprocessor system, jointly to complete large-scale calculations or to control in real time.Master and slave processor can be comprised of processor of the same type or difference in functionality type, and the communication between master and slave processor can be undertaken by universal asynchronous receiver/transmitter (UART), Ethernet, peripheral controller interface (PCI) bus or other bus mode.
As shown in Figure 1, in the prior art, main processor system and often all need separately a set of independently peripheral storage from processor system, these storeies comprise following part: the bootstrap memory starting for bootstrap processor, for storing the program storage of kernel and application program and for carrying out the SDRAM storer of this kernel and application program.The software version loading method of master and slave processor is: (1) first, is respectively master and slave processor bootstrap memory sintering boot separately by instruments such as burning sheet device; (2) by bootstrap memory, guide respectively and start after master and slave processor, by master and slave processor UART interface or Ethernet interface separately, kernel and application program are loaded in program storage separately; (3) follow master and slave processor and carry out respectively again kernel and the application program in program storage separately, start respectively master and slave processor function and task separately; (4) primary processor and from setting up master-slave communication relation by UART interface, Ethernet interface, pci bus interface or other bus interface between processor simultaneously.As can be seen here, primary processor and only just have a kind of principal and subordinate's correspondence from processor program is separately moved, is independently in the start-up course of master and slave processor completely.And in software release upgrade, primary processor and from bootstrap memory separately of processor and the software version program storage also needs to upgrade respectively.
The shortcoming of the design of correlation technique is: not only circuit is complicated, device is many, cost is high for whole principal and subordinate's multicomputer system, and the upgrading of program version and maintenance also much complicated, the time spending and cost are also high, efficiency is low.
Summary of the invention
Consider the problems referred to above and make the present invention, for this reason, fundamental purpose of the present invention is to provide a kind of master-slave mode multiprocessor system and software version loading method.
To achieve these goals, according to the first embodiment of the present invention, provide a kind of master-slave mode multiprocessor system.
This system comprises: primary processor, by its external bus with bootstrap memory, program storage, SDRAM storer; One or more from processor, one or more each from processor by its external bus with guiding and program storage, SDRAM storer; And bus-controlled switching, for the external bus of primary processor being connected to each guiding from processor and program storage; Wherein, primary processor and one or morely connect by communication interface circuit between processor.
In this system, primary processor can send reseting controling signal from processor to one or more.In addition, communication interface circuit comprises UART interface, Ethernet interface, pci bus interface and other bus interface.
To achieve these goals, according to a second embodiment of the present invention, provide a kind of software version loading method, the method has adopted the master-slave mode multiprocessor system of first embodiment of the invention.
The method comprises the following steps: first step, and primary processor is carried out the boot of its bootstrap memory, with initialization primary processor and related peripheral circuit interface; Second step, primary processor is downloaded related content from webmaster version server, and is kept in the program storage of primary processor; Third step, primary processor, by sending reseting controling signal to one or more from processor, writes corresponding guiding and program storage by bus-controlled switching by the required relative program version of each processor; The 4th step, primary processor and start respectively various functions and task separately from processor; And the 5th step, primary processor and set up master-slave communication relation from processor, so that main processor monitors and management are from the running status of processor.
Wherein, in second step, the related content that primary processor is downloaded comprises: the kernel that primary processor is used and application version, the boot version, kernel and the application version that from processor, use.
In addition, third step comprises the following steps: steps A, primary processor sends reseting controling signal to one or more from processor so that one or more from processor in reset mode; Step B, primary processor is opened bus-controlled switching, with the guiding to from processor and program storage, reads and writes control; Step C, primary processor writes corresponding guiding and program storage by each from processor required boot version, kernel and application version; Step D, primary processor stops, to the reset from processor, closing bus-controlled switching, to close primary processor, the read-write of the guiding from processor and program storage is controlled.
The 4th step comprises the following steps: steps A: primary processor operation kernel and application version, start its various functions and task; And step B: carry out respectively the boot bootstrap memory separately from processor, and move kernel and application version, start function and task separately.
In addition, in second step, primary processor is downloaded related content by related peripheral interface, and wherein, related peripheral interface comprises UART interface and Ethernet interface.
In the 5th step, primary processor and from setting up master-slave communication relation by UART interface, Ethernet interface, pci bus interface or other bus interface between processor.
By technique scheme, the present invention has reduced the complexity of circuit, and has facilitated loading, upgrading and the maintenance management of software version.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the system chart of principal and subordinate processor in prior art;
Fig. 2 is according to the system chart of the principal and subordinate processor of first embodiment of the invention;
Fig. 3 is according to the block diagram of the particular instance of the system of the principal and subordinate processor of first embodiment of the invention;
Fig. 4 is according to the process flow diagram of the software version loading method of second embodiment of the invention; And
Fig. 5 is the detailed processing flow chart according to the software version loading method of second embodiment of the invention.
Embodiment
Describe below with reference to the accompanying drawings the present invention in detail.
The first embodiment
First with reference to Fig. 2 and Fig. 3, the first embodiment of the present invention is described.Fig. 2 is according to the block diagram of the master-slave mode multiprocessor system of first embodiment of the invention, and Fig. 3 is the block diagram of master-slave mode multiprocessor system that adopts the network processing unit APP320E of PowerPC MPC875 microprocessor and Agere company
As shown in Figure 2, according to the master-slave mode multiprocessor system of first embodiment of the invention, comprise: primary processor 202, by its external bus with bootstrap memory (BOOT storer) 204, program storage (PROGRAM storer) 206, SDRAM storer 208; One or more from processor 210, one or more each from processor 210 by its external bus with guiding and program storage (, BOOT & PROGRAM storer, guiding and the two-in-one storer of program) 212, SDRAM storer 214; And bus-controlled switching 216, for the external bus of primary processor 202 being connected to guiding and program storage 212; Wherein, primary processor 202 and one or morely connect by communication interface circuit between processor 210.
In this system, primary processor 202 sends reseting controling signal to one or more from processor 210.In addition, communication interface circuit comprises UART interface, Ethernet interface, pci bus interface and other bus interface.
It is example that the primary processor of take adopts the system of the PowerPC MPC875 microprocessor of Freescale company.As shown in Figure 3, primary processor 301 connects the Program Flash storer 305 of the Boot Flash storer 303 of a 512K byte, the SDRAM storer 304 of 16M byte and 4M byte by its external bus 302; From the built-in ARM microprocessor of the network processing unit APP320E of processor 306Wei Agere company, it connects the Boot & Program Flash storer 308 of a 16M byte and the DDR2 SDRAM storer 309 of 32M byte by its external bus 307; Primary processor 301 is connected to from the Boot & Program Flash storer 308 of processor 306 by a set of bus switch 310, can be for downloading from processor 306 or upgrading refresh routine version; In addition, primary processor 301 is controlled from the reset mode of processor 306 by reseting controling signal 311, primary processor 301 and from communicating by Ethernet interface 312 between processor 306.
The second embodiment
Below with reference to Fig. 4 and Fig. 5, the second embodiment of the present invention is described.Fig. 4 is according to the process flow diagram of the software version loading method of second embodiment of the invention, and Fig. 5 is according to the process flow diagram of the detailed processing of the software version loading method of second embodiment of the invention.
As shown in Figure 4, according to the software version loading method of second embodiment of the invention, comprise the following steps: step S402, primary processor is carried out the boot of its bootstrap memory, with initialization primary processor and related peripheral circuit interface; Step S404, primary processor is downloaded related content from webmaster version server, and is kept in the program storage of primary processor; Step S406, primary processor, by sending reseting controling signal to one or more from processor, writes corresponding guiding and program storage by bus-controlled switching by the required relative program version of each processor; Step S408, primary processor and start respectively various functions and task separately from processor; And step S410, primary processor and set up master-slave communication relation from processor, so that main processor monitors and management are from the running status of processor.
Wherein, in step S404, the related content that primary processor is downloaded comprises: the kernel that primary processor is used and application version, the boot version, kernel and the application version that from processor, use.
In addition, step S406 comprises the following steps: steps A, primary processor sends reseting controling signal to one or more from processor so that one or more from processor in reset mode; Step B, primary processor is opened bus-controlled switching, with the guiding to from processor and program storage, reads and writes control; Step C, primary processor writes corresponding guiding and program storage by each from processor required boot version, kernel and application version; Step D, primary processor stops, to the reset from processor, closing bus-controlled switching, to close primary processor, the read-write of the guiding from processor and program storage is controlled.
In addition, step S408 comprises the following steps: steps A: primary processor operation kernel and application version, start its various functions and task; And step B: carry out respectively the boot bootstrap memory separately from processor, and move kernel and application version, start function and task separately.
In addition, in step S404, primary processor is downloaded related content by related peripheral interface, and wherein, related peripheral interface comprises UART interface and Ethernet interface.
In step S410, primary processor and from setting up master-slave communication relation by UART interface, Ethernet interface, pci bus interface or other bus interface between processor.
The more specifically step of said method as shown in Figure 5, specifically describes as follows:
Step 501, flow process starts.
Step 502, primary processor electrifying startup, carries out the boot of its Boot storer, and initialization primary processor itself and related peripheral interface, as UART interface and Ethernet interface.
Step 503, need to do you judge that master and slave processor load or updating software release is no? Boot program version and kernel when if master and slave processor starts separately and application version has all existed and the renewal of need not upgrading, skip to execution step 508, master and slave processor is Bootstrap Commissioning Program and kernel and application program separately, start function and task separately, and set up the correspondence between master and slave processor; If master and slave processor needs updating software release, perform step 504.
Step 504, primary processor is by its UART interface and Ethernet interface, from webmaster version server download primary processor kernel used and application version, from processor Boot boot version used and kernel and application version, be all saved in the Program storer of primary processor.
Step 505, primary processor is by reseting controling signal, allow each from processor in reset mode.
Step 506, primary processor is opened bus-controlled switching simultaneously, makes primary processor can read and write Boot and the two-in-one storer of Program of controlling from processor; Primary processor writes each corresponding Boot and the two-in-one storer of Program from the required Boot boot version of processor and kernel and application version.
Step 507, primary processor stops, to the reset from processor, closing bus-controlled switching simultaneously, closes primary processor the read-write of the Boot from processor and the two-in-one storer of Program is controlled.
Step 508, primary processor operation kernel and application version, start its various functions and task.
Step 509, each carries out the Boot boot Boot storer separately from processor, then moves kernel and application version, starts function and task separately.
Step 510, primary processor and from setting up master-slave communication relation by UART interface, Ethernet interface, pci bus interface or other bus interface between processor, the running status from processor can be monitored and manage to primary processor constantly.
Comprehensive the first and second embodiment, the software version load step of the embedded system of master-slave mode multiprocessor wherein can be to carry out when master and slave processor starts first, can be also to carry out when the normal upgrading update software version in service of master and slave processor.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. a master-slave mode multiprocessor system, is characterized in that, comprising:
Primary processor, by its external bus with bootstrap memory, program storage, SDRAM storer;
One or more from processor, described one or more each from processor by its external bus with guiding and program storage, SDRAM storer; And
Bus-controlled switching, at described primary processor, describedly one or morely from processor, need to load or updating software release in the situation that, the external bus of described primary processor is connected directly to described guiding and program storage;
Wherein, described primary processor and described one or morely connect by communication interface circuit between processor.
2. master-slave mode multiprocessor system according to claim 1, is characterized in that, described primary processor can be to described one or more from processor transmission reseting controling signal.
3. master-slave mode multiprocessor system according to claim 1, is characterized in that, described communication interface circuit comprises UART interface, Ethernet interface, pci bus interface and other bus interface.
4. a software version loading method, is used according to the master-slave mode multiprocessor system described in any one in claims 1 to 3, it is characterized in that, comprises the following steps:
First step, primary processor is carried out the boot of its bootstrap memory, with initialization primary processor and related peripheral circuit interface;
Second step, described primary processor is downloaded related content from webmaster version server, and is kept in the program storage of described primary processor;
Third step, described primary processor is by sending reseting controling signal to one or more from processor, the external bus by the described primary processor of direct connection and describedly from the guiding of processor and the bus-controlled switching of program storage, the required relative program version of each processor is write to corresponding guiding and program storage;
The 4th step, described primary processor and describedly start respectively various functions and task separately from processor; And
The 5th step, described primary processor and describedly set up master-slave communication relation from processor, so that the described running status from processor of described main processor monitors and management.
5. software version loading method according to claim 4, it is characterized in that, in described second step, the described related content that described primary processor is downloaded comprises: the kernel that described primary processor is used and application version, described boot version, kernel and the application version using from processor.
6. software version loading method according to claim 5, is characterized in that, described third step comprises the following steps:
Steps A, described primary processor sends reseting controling signal to one or more from processor so that described one or more from processor in reset mode;
Step B, described primary processor is opened bus-controlled switching, so that the described guiding from processor and program storage are read and write to control;
Step C, described primary processor writes corresponding guiding and program storage by each from processor required boot version, kernel and application version;
Step D, described primary processor stops, to the described reset from processor, closing described bus-controlled switching, to close described primary processor, to described, from the described guiding of processor and the read-write of program storage, controls.
7. software version loading method according to claim 5, is characterized in that, described the 4th step comprises the following steps:
Steps A: described primary processor operation kernel and application version, start its various functions and task; And
Step B: describedly carry out respectively the boot bootstrap memory separately from processor, and move kernel and application version, start function and task separately.
8. software version loading method according to claim 4, is characterized in that, in institute
State in second step, described in described primary processor is downloaded by described related peripheral interface
Related content, wherein, described related peripheral interface comprises UART interface and ether
Network interface.
9. software version loading method according to claim 4, it is characterized in that, in described the 5th step, described primary processor and described from setting up master-slave communication relation by UART interface, Ethernet interface, pci bus interface or other bus interface between processor.
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| CN101222374B (en) * | 2008-01-30 | 2010-09-22 | 华为技术有限公司 | System, device and method for implementing service upgrade |
| US8136108B2 (en) * | 2008-09-03 | 2012-03-13 | Computime, Ltd | Updating firmware with multiple processors |
| CN101697128A (en) * | 2009-10-10 | 2010-04-21 | 中兴通讯股份有限公司 | Version upgrading method and device |
| CN102053849B (en) * | 2009-10-30 | 2013-06-26 | 杭州华三通信技术有限公司 | Distributed system, main system and slave systems thereof and a code loading method |
| US8938609B2 (en) | 2009-11-13 | 2015-01-20 | Qualcomm Incorporated | Methods and apparatus for priority initialization of a second processor |
| CN102110072B (en) * | 2009-12-29 | 2013-06-05 | 中兴通讯股份有限公司 | Complete mutual access method and system for multiple processors |
| CN102253844B (en) * | 2010-05-18 | 2014-05-07 | 大唐移动通信设备有限公司 | Method and device for starting processor |
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| WO2015014013A1 (en) * | 2013-07-30 | 2015-02-05 | 宇龙计算机通信科技(深圳)有限公司 | Terminal, display control method and display control system for user interface |
| CN103440437B (en) * | 2013-07-30 | 2017-02-15 | 东莞宇龙通信科技有限公司 | Terminal and display control method of user interface |
| CN104199702A (en) * | 2014-09-08 | 2014-12-10 | 吴健辉 | Software version loading method |
| CN106020898A (en) * | 2016-05-30 | 2016-10-12 | 华讯方舟科技有限公司 | Software upgrading method and system of multi-processor device |
| CN106095454A (en) * | 2016-06-16 | 2016-11-09 | 北京经纬恒润科技有限公司 | The Oftware updating method of a kind of coprocessor, system and primary processor |
| CN107544815A (en) * | 2016-06-28 | 2018-01-05 | 中兴通讯股份有限公司 | A kind of startup method and device of multicomputer system |
| CN107463377A (en) * | 2017-07-27 | 2017-12-12 | 重庆秦嵩科技有限公司 | A kind of quick loading methods of more Powerpc based on PCIE |
| CN108845969B (en) * | 2018-03-28 | 2021-09-10 | 核工业理化工程研究院 | Operation control method and operation system suitable for incompletely symmetrical multi-processing microcontroller |
| CN113169907B (en) * | 2018-06-08 | 2022-06-07 | 住友电装株式会社 | Communication apparatus and control method |
| CN110377358A (en) * | 2019-06-28 | 2019-10-25 | 深圳市汇川技术股份有限公司 | Coprocessor firmware dynamic loading method, system, equipment and storage medium |
| CN110569053A (en) * | 2019-09-03 | 2019-12-13 | 深圳市东微智能科技股份有限公司 | method for upgrading application chip in electronic equipment and electronic equipment |
| CN111209059B (en) * | 2020-01-14 | 2023-03-03 | 中国北方车辆研究所 | Embedded software multi-version control system and method |
| CN111475191B (en) * | 2020-04-04 | 2023-06-06 | 东风越野车有限公司 | Automobile controller software upgrading system and method based on multi-core technology |
| CN111666104B (en) * | 2020-06-11 | 2023-12-19 | 江苏华创微系统有限公司 | DSP processor design method supporting from rapidI/O start |
| CN112799743A (en) * | 2021-04-13 | 2021-05-14 | 浙江华创视讯科技有限公司 | Method and device for loading system file of slave processor unit and electronic equipment |
| CN113778538A (en) * | 2021-09-13 | 2021-12-10 | 讯牧信息科技(上海)有限公司 | Multiprocessor system and starting method thereof |
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