CN102520961A - Off-chip online programmable SOC (system on a chip) and control method for same - Google Patents
Off-chip online programmable SOC (system on a chip) and control method for same Download PDFInfo
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- CN102520961A CN102520961A CN2011104330685A CN201110433068A CN102520961A CN 102520961 A CN102520961 A CN 102520961A CN 2011104330685 A CN2011104330685 A CN 2011104330685A CN 201110433068 A CN201110433068 A CN 201110433068A CN 102520961 A CN102520961 A CN 102520961A
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Abstract
The invention relates to the technical field of design of an SOC (system on a chip), in particular to an off-chip online programmable SOC (system on a chip) and a control method for the same. The system comprises an SOC, an off-chip Nflash/Norflash storage and an off-chip switch, the SOC comprises a minimum SOC, a serial port controller, an Nflash/Norflash controller and a reset control CCU (central control unit) module, and the minimum SOC comprises a CPU (central processing unit), an internal storage and an on-chip bus. The control method for the system includes: compiling software on a computer, switching the SOC into a programming mode by means of selection control of the off-chip switch, downloading compiled executable file data into the off-chip Nflash/Norflash storage, and then switching the SOC into a normal operating mode to realize system operation. The system and the control method for the system are not only beneficial to development of a software system, but also easy to debug, and the chip is not easy to damage during debugging.
Description
Technical field
The present invention relates to the SOC design field, particularly a kind of outer online programmable SOC system and control method thereof.
Background technology
The SOC chip has been widely used in the every field at present; And the carrier of the software of SOC chip storage has dual mode, and a kind of is the interior Flash of SOC chip; A kind of is the outer Nflash/Norflash of sheet, and this dual mode is different for the downloading mode of software data.
The software data downloaded stored mode of Flash in the sheet is as shown in Figure 1, after the PC end generates software executable, downloads data to the serial ports of SOC chip through serial ports, through the flash controller of chip internal, writes data among the Flash then.The advantage of this mode is that software can be directly downloaded to the routine data that generates among the Flash; System debug is very convenient; Shortcoming is that the Flash memory span can be very not big because flash in the SOC chip, receives the restriction of chip technology and cost; For the software systems of complicacy, just limited its application like this.
The software data downloaded stored mode of the Nflash/Norflash that sheet is outer is as shown in Figure 2; The PC end is after software generates; Through the Nflash/Norflash programming instrument of specialty, the software program data programming in Nflash/Norflash, and then is welded on pcb board.The advantage of this mode is that the outer Nflash/Norflash of sheet is enough big; Software systems for complicacy can support that shortcoming is that debugging bothers very much for software systems, each update routine; Need earlier the Nflash/Norflash chip to be welded; Fever writes through specialty in Nflash/Norflash, and then is welded to the software programming on the pcb board, brings the risk of damage having increased chip virtually because of welding like this.
Summary of the invention
The objective of the invention is to overcome the deficiency of prior art, a kind of outer online programmable SOC system and control method thereof are provided, this system and control method thereof not only help the exploitation of software systems, and are easy to debugging, and the debug process chip is not fragile.
For realizing above-mentioned purpose; Technical scheme of the present invention is: a kind of outer online programmable SOC system; Comprise SOC chip, the outer Nflash of sheet or Norflash storer and the outer switch of sheet; Said SOC chip is made up of SOC minimum system, serial ports controller, Nflash or the Norflash controller corresponding with said outer Nflash or Norflash storer and the control CCU module that resets, and said SOC minimum system comprises CPU, internal storage and bus on chip;
Said serial ports controller; Being used for the UART protocol conversion is the bus on chip agreement; Said serial ports controller is provided with two UART interfaces and two EBIs; UART0 interface in two UART interfaces is used under programming mode, linking to each other with serial ports of computers; The UART1 interface is the functional interface of SOC system under normal mode of operation, and the MBUS interface in two EBIs is that said serial ports controller is operated in the EBI under the Master pattern, Nflash or Norflash controller outside being used under programming mode, initiatively giving said with data transmission; Another SBUS interface is that said serial ports controller is operated in the EBI under the Slave pattern, is used under normal mode of operation bus on chip to the control interface of serial ports;
Said Nflash or Norflash controller; Be used for the bus on chip protocol conversion is the control timing of outer Nflash of sheet or Norflash storer; Said Nflash or Norflash controller have only a Slave EBI, and controlling said Slave EBI through model selection is to connect MBUS interface or SBUS interface;
The said control CCU module that resets is used for the reset signal of SOC system is controlled the management and the switching of completion all reset signals of SOC system under programming mode and under the normal mode of operation;
Said outer switch is used for the mode of operation of SOC system is selected control.
The present invention also provides the outer online programmable SOC of sheet the control method of system, may further comprise the steps:
(1) the outer switch of sheet being set makes the SOC system switch to programming mode;
(2) control the control that resets of CCU module through resetting; SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller are changed to reset mode, then MBUS interface, UART0 interface and Nflash or Norflash controller are changed to the disarm state that resets;
(3) through computing machine start-up code and function code are compiled as the executable file data, said executable file data are write the serial ports controller of SOC chip through the UART0 interface;
(4) serial ports controller through MUX, is passed to Nflash or Norflash controller with said executable file data through the MBUS interface;
(5) Nflash or the Norflash controller said executable file data that will receive transfer the external memory control timing to, are written in outer Nflash of sheet or the Norflash storer;
(6) the outer switch of sheet being set makes the SOC system switch to normal mode of operation;
(7) control the control that resets of CCU module through resetting; MBUS interface, UART0 interface and Nflash or Norflash controller are changed to reset mode, then SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller are changed to the disarm state that resets;
(8) CPU starts working, sense order Nflash or the Norflash storer outside sheet, configuration peripheral hardware, operation function corresponding program.
The invention has the beneficial effects as follows:
(1) the software function design no longer of SOC system receives the restriction of internal storage capacity, makes the PHP pay attention to the efficient and the performance of software more, improves the Time To Market of product.
(2) avoid fully in the software debugging stage, use special storer programming instrument that the Nflash/Norflash device is carried out repeatedly programming and welds the chip risk of damage that is brought, and software debugging is very flexible, has significantly reduced debug time.
Below in conjunction with accompanying drawing and specific embodiment the present invention is done further detailed description.
Description of drawings
Fig. 1 is the software data downloaded stored mode synoptic diagram of the Flash in the sheet in the prior art.
Fig. 2 is the software data downloaded stored mode synoptic diagram of the Nflash/Norflash outside the sheet in the prior art.
Fig. 3 is the system architecture synoptic diagram of the embodiment of the invention.
Fig. 4 is the present invention switches to normal mode of operation from programming mode the control timing figure that resets.
Fig. 5 is the present invention switches to programming mode from normal mode of operation the control timing figure that resets.
Embodiment
Of the present invention outer online programmable SOC system; As shown in Figure 3; Comprise SOC chip, the outer Nflash of sheet or Norflash storer and the outer switch of sheet; Said SOC chip is made up of SOC minimum system, serial ports controller, Nflash or the Norflash controller corresponding with said outer Nflash or Norflash storer and the control CCU module that resets, and said SOC minimum system comprises CPU, internal storage and bus on chip; Need to prove; Outer Nflash of sheet or Norflash storer are meant that chip external memory can adopt Nflash or Norflash wherein a kind of; If sheet adopts the Nflash storer outward; Then corresponding employing is the NFlash controller, if sheet adopts the Norflash storer outward, then corresponding employing is the Norflash controller.
Said serial ports controller; Being used for the UART protocol conversion is the bus on chip agreement; Said serial ports controller is provided with two UART interfaces and two EBIs; UART0 interface in two UART interfaces is used under programming mode, linking to each other with serial ports of computers; The UART1 interface is the functional interface of SOC system under normal mode of operation, and the MBUS interface in two EBIs is that said serial ports controller is operated in the EBI under the Master pattern, Nflash or Norflash controller outside being used under programming mode, initiatively giving said with data transmission; Another SBUS interface is that said serial ports controller is operated in the EBI under the Slave pattern, is used under normal mode of operation bus on chip to the control interface of serial ports;
Said Nflash or Norflash controller; Be used for the bus on chip protocol conversion is the control timing of outer Nflash of sheet or Norflash storer; Said Nflash or Norflash controller have only a Slave EBI, and controlling said Slave EBI through model selection is to connect MBUS interface or SBUS interface;
The said control CCU module that resets is used for the reset signal of SOC system is controlled the management and the switching of completion all reset signals of SOC system under programming mode and under the normal mode of operation;
Said outer switch is used for the mode of operation of SOC system is selected control; When the switch signal was high level outside the sheet, the expression system was in online programming state, and when switch signal outside sheet when being low level, the expression system is in normal operating conditions.
Above-mentioned SOC minimum system also comprises peripheral hardware, and CPU, internal storage, bus on chip are the requisite assemblies of SOC system, and peripheral hardware is selected different functional according to SOC system different demands.
The control method of of the present invention outer online programmable SOC system may further comprise the steps:
(1) the outer switch of sheet is set to high level, and the SOC system is under the programming mode;
(2) under programming mode; The control that resets through the control CCU module that resets; SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller are changed to reset mode, then MBUS interface, UART0 interface and Nflash or Norflash controller are changed to the disarm state that resets;
(3) through computing machine start-up code and function code are compiled as the executable file data, said executable file data are write the serial ports controller of SOC chip through the UART0 interface;
(4) serial ports controller through MUX, is passed to Nflash or Norflash controller with said executable file data through the MBUS interface;
(5) Nflash or the Norflash controller said executable file data that will receive transfer the external memory control timing to, are written in outer Nflash of sheet or the Norflash storer;
The said executable file data that (6) will write are read through Nflash or Norflash controller; Pass to computing machine again through the UART0 interface then; In computing machine with write before data compare; Guarantee that the data of writing into do not have mistake,, then write the executable file data again if make a mistake;
(7) after confirming that the executable file data successfully are written to sheet outside Nflash or Norflash storer, sheet switch outward is set to low level, makes the SOC system switch to normal mode of operation from programming mode;
(8) switch under the normal mode of operation and after operation a period of time in the SOC system; The control that resets through the control CCU module that resets; MBUS interface, UART0 interface and Nflash or Norflash controller are changed to reset mode, then SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller are changed to the disarm state that resets;
(9) CPU starts working, sense order Nflash or the Norflash storer outside sheet, configuration peripheral hardware, operation function corresponding.
(10) if not meeting the demands or need, function revises; Then revise software and recompility on computers; Selection control through the outer switch of sheet switches to programming mode with the SOC system, and the executable file data that newly compile are downloaded in outer Nflash of sheet or the Norflash storer; And then switch to normal mode of operation, carry out system debug and checking.
As shown in Figure 3, in the use of product, switch or wire jumper need be set on pcb board outside the sheet control as mode switch.With after computer by serial links to each other, software design is accomplished, after the compiling at the SOC chip; Mode selector switch is set to height; Be the online programmable pattern, software data downloaded in the external memory storage through serial ports, guarantee that data download is correct after; To normal mode of operation, the SOC system starts anew to carry out function program with mode switch.
In the present invention, the control that resets of CCU module has played crucial effects to switching in programming mode and normal mode of operation of total system.
Fig. 4 is for switching to the sequential chart of normal mode of operation from programming mode; The control that resets of the control CCU module that resets; At first the reset signal of online programmable logical gate drags down earlier and is in reset mode, and the reset signal of operate as normal logic is drawn high then, is in the disarm state that resets.Wherein, The reset signal of online programmable logical gate refers to the reset signal of MBUS interface, UART0 interface and Nflash or Norflash controller, and the reset signal of operate as normal logical gate refers to the reset signal of SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller.
Fig. 5 is for switching to the sequential chart of programming mode from normal mode of operation; The control that resets of the CCU module that resets; At first the reset signal of operate as normal logical gate drags down earlier and is in reset mode, and the reset signal of online programmable logic is drawn high then, is in the disarm state that resets.
Normal mode of operation and programming mode all will be used the Nflash/Norflash controller; This part logic need reset in mode switch; Like Fig. 4 and shown in Figure 5; The control that resets of reset control and the online programmable logic of operate as normal logic all be low during, be the reset time of Nflash/Norflash controller.
More than be preferred embodiment of the present invention, all changes of doing according to technical scheme of the present invention when the function that is produced does not exceed the scope of technical scheme of the present invention, all belong to protection scope of the present invention.
Claims (5)
1. the outer online programmable SOC of sheet system; It is characterized in that: comprise SOC chip, the outer Nflash of sheet or Norflash storer and the outer switch of sheet; Said SOC chip is made up of SOC minimum system, serial ports controller, Nflash or the Norflash controller corresponding with said outer Nflash or Norflash storer and the control CCU module that resets, and said SOC minimum system comprises CPU, internal storage and bus on chip;
Said serial ports controller; Being used for the UART protocol conversion is the bus on chip agreement; Said serial ports controller is provided with two UART interfaces and two EBIs; UART0 interface in two UART interfaces is used under programming mode, linking to each other with serial ports of computers; The UART1 interface is the functional interface of SOC system under normal mode of operation, and the MBUS interface in two EBIs is that said serial ports controller is operated in the EBI under the Master pattern, Nflash or Norflash controller outside being used under programming mode, initiatively giving said with data transmission; Another SBUS interface is that said serial ports controller is operated in the EBI under the Slave pattern, is used under normal mode of operation bus on chip to the control interface of serial ports;
Said Nflash or Norflash controller; Be used for the bus on chip protocol conversion is the control timing of outer Nflash of sheet or Norflash storer; Said Nflash or Norflash controller have only a Slave EBI, and controlling said Slave EBI through model selection is to connect MBUS interface or SBUS interface;
The said control CCU module that resets is used for the reset signal of SOC system is controlled the management and the switching of completion all reset signals of SOC system under programming mode and under the normal mode of operation;
Said outer switch is used for the mode of operation of SOC system is selected control.
2. according to claim 1 outer online programmable SOC system, it is characterized in that: said SOC minimum system also comprises peripheral hardware.
3. the control method of according to claim 1 and 2 outer online programmable SOC system is characterized in that: may further comprise the steps:
(1) the outer switch of sheet being set makes the SOC system switch to programming mode;
(2) control the control that resets of CCU module through resetting; SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller are changed to reset mode, then MBUS interface, UART0 interface and Nflash or Norflash controller are changed to the disarm state that resets;
(3) through computing machine start-up code and function code are compiled as the executable file data, said executable file data are write the serial ports controller of SOC chip through the UART0 interface;
(4) serial ports controller through MUX, is passed to Nflash or Norflash controller with said executable file data through the MBUS interface;
(5) Nflash or the Norflash controller said executable file data that will receive transfer the external memory control timing to, are written in outer Nflash of sheet or the Norflash storer;
(6) the outer switch of sheet being set makes the SOC system switch to normal mode of operation;
(7) control the control that resets of CCU module through resetting; MBUS interface, UART0 interface and Nflash or Norflash controller are changed to reset mode, then SBUS interface, UART1 interface, SOC minimum system and Nflash or Norflash controller are changed to the disarm state that resets;
(8) CPU starts working, sense order Nflash or the Norflash storer outside sheet, configuration peripheral hardware, operation function corresponding program.
4. the control method of according to claim 3 outer online programmable SOC system; It is characterized in that: between step (5) and step (6), also further may further comprise the steps: the said executable file data that will write are read through Nflash or Norflash controller; Pass to computing machine again through the UART0 interface then; In computing machine with write before data compare; Guarantee that the data of writing into do not have mistake,, then write the executable file data again if make a mistake; After confirming that the executable file data successfully are written to sheet outside Nflash or Norflash storer, be provided with again sheet outward switch make the SOC system switch to normal mode of operation.
5. the control method of according to claim 3 outer online programmable SOC system; It is characterized in that: also further may further comprise the steps afterwards: revise if function does not meet the demands or needs in step (8); Then revise software and recompility on computers; Selection control through the outer switch of sheet switches to programming mode with the SOC system, and the executable file data that newly compile are downloaded in outer Nflash of sheet or the Norflash storer; And then switch to normal mode of operation, carry out system debug and checking.
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| CN103246623A (en) * | 2013-05-20 | 2013-08-14 | 杭州士兰控股有限公司 | Computing device extension system for system on chip (SOC) |
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| CN105487906A (en) * | 2015-12-07 | 2016-04-13 | 浪潮集团有限公司 | Method and system for updating MCU core code by plug-in FLASH |
| CN106682535A (en) * | 2017-03-16 | 2017-05-17 | 周清睿 | System on chip (SoC) |
| CN106873916A (en) * | 2017-02-23 | 2017-06-20 | 郑州云海信息技术有限公司 | A kind of Debugging message access method and device based on the debugging of ultra-large chip |
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| CN111459744A (en) * | 2020-03-20 | 2020-07-28 | 江苏集萃智能集成电路设计技术研究所有限公司 | Firmware burning method and firmware debugging method of video processing chip |
| CN112291256A (en) * | 2020-11-06 | 2021-01-29 | 北京中航通用科技有限公司 | UART gateway data transmission method |
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Cited By (11)
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| CN103246623A (en) * | 2013-05-20 | 2013-08-14 | 杭州士兰控股有限公司 | Computing device extension system for system on chip (SOC) |
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| CN106873916A (en) * | 2017-02-23 | 2017-06-20 | 郑州云海信息技术有限公司 | A kind of Debugging message access method and device based on the debugging of ultra-large chip |
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| WO2020029254A1 (en) * | 2018-08-10 | 2020-02-13 | 深圳市汇顶科技股份有限公司 | Soc chip and bus access control method |
| US11048648B2 (en) | 2018-08-10 | 2021-06-29 | Shenzhen GOODIX Technology Co., Ltd. | SoC chip and method for controlling bus access |
| CN111459744A (en) * | 2020-03-20 | 2020-07-28 | 江苏集萃智能集成电路设计技术研究所有限公司 | Firmware burning method and firmware debugging method of video processing chip |
| CN112291256A (en) * | 2020-11-06 | 2021-01-29 | 北京中航通用科技有限公司 | UART gateway data transmission method |
| CN112291256B (en) * | 2020-11-06 | 2023-12-01 | 北京中航通用科技有限公司 | UART gateway data transmission method |
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