CN101174202B - Fast access device of video recording transcoder with multi-instruction flow and its control method - Google Patents

Fast access device of video recording transcoder with multi-instruction flow and its control method Download PDF

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Publication number
CN101174202B
CN101174202B CN2006101366044A CN200610136604A CN101174202B CN 101174202 B CN101174202 B CN 101174202B CN 2006101366044 A CN2006101366044 A CN 2006101366044A CN 200610136604 A CN200610136604 A CN 200610136604A CN 101174202 B CN101174202 B CN 101174202B
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order
instruction queue
instruction
steering
video recording
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CN101174202A (en
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成世明
蔡忠宪
易四军
王津福
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Ali Corp
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Ali Corp
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Abstract

The invention relates to a quick caching device for the video recording decoder, comprising a plurality of instruction queues. The quick caching device is coupled with a video recording decoder and a dynamic random access memory for providing the decoder with the data in the dynamic random access memory or the data in the quick caching device depending on the external control instructions. The invention enables to send multiple instructions to the quick caching buffer, internal buffer and dynamic random access memory.

Description

The video recording code translator fast access device and the control method thereof of tool multiple instruction flow
Technical field
The present invention relates to a kind of video recording code translator fast access device, particularly a kind of video recording code translator fast access device of tool multiple instruction flow.
Background technology
Please refer to Fig. 1.Fig. 1 is the synoptic diagram of the H.264 video recording code translator fast access device (H.264 videodecoder cache) 100 of prior art.As shown in the figure, video recording code translator fast access device 100 comprises a fast instruction fetch device 110 and and gets buffer zone 120 soon.Fast instruction fetch device 110 comprises an instruction queue 111 and an order-sorter 112.Instruction queue 111 is coupled to outside in order to the steering order that receives and storage is sent by the outside.Order-sorter 112 is coupled to instruction queue 111, gets a buffer zone 120 and a DRAM (Dynamic Random Access Memory) (dynamic random access memory soon, DRAM) 130, in order to steering order classification that will be received, and send to respectively and get buffer zone 120 and DRAM (Dynamic Random Access Memory) 130 soon.Get buffer zone 120 soon and be coupled to order-sorter 112, DRAM (Dynamic Random Access Memory) 130 and video recording code translator (video decoder) 140, be used for the instruction that sends according to order-sorter 112, the data storage that DRAM (Dynamic Random Access Memory) 130 is sent, perhaps, be sent to video recording code translator 140 with the data of being stored.
The external control instruction comprises the instruction of reading the instruction of getting buffer zone 120 soon and reading DRAM (Dynamic Random Access Memory) 130.If order-sorter 112 receives one and reads the instruction of getting buffer zone 120 soon, then order-sorter 112 can be sent to this instruction and get buffer zone 120 soon, gets buffer zone 120 soon and according to this instruction the data of being stored is sent to video recording code translator 140 again.If order-sorter 112 receives an instruction of reading DRAM (Dynamic Random Access Memory) 130, then order-sorter 112 can be sent to DRAM (Dynamic Random Access Memory) 130 with this instruction, DRAM (Dynamic Random Access Memory) 130 is again according to this instruction, data are sent to get buffer zone 120 soon, get buffer zone 120 then soon and will be sent to video recording code translator 140 again from the data of DRAM (Dynamic Random Access Memory).
Order-sorter 112 receives the steering order of instruction queue 111 and classifies to after getting buffer zone 120 or DRAM (Dynamic Random Access Memory) 130 soon, can stop to receive again instruction wait for get the release that buffer zone 120 or DRAM (Dynamic Random Access Memory) 130 will carry out according to steering order soon after, receive next steering order again.And, therefore, after the instruction of DRAM (Dynamic Random Access Memory) 130 is read in order-sorter 112 transmission one, just need wait for one period considerable time because the reading speed of DRAM (Dynamic Random Access Memory) 130 is quite slow.Even and order-sorter 112 next ones instruction that will receive at this moment is to read the instruction of getting buffer zone 120 soon, order-sorter 112 can be waited for still that DRAM (Dynamic Random Access Memory) 130 executes and read after the action, just receive and nextly reads the instruction of getting buffer zone 120 soon, and send to and get buffer zone 120 soon.And during this section wait, getting buffer zone 120 soon is to be in idle state.Therefore, the video recording code translator fast access device of prior art provides data can not effectively improve to the speed of video recording code translator, causes temporal waste.
Summary of the invention
The invention provides a kind of video recording code translator fast access device of tool multiple instruction flow.This video recording code translator comprises a fast instruction fetch device, comprises a main instruction queue, in order to store the steering order that is sent by the outside; One order-sorter is coupled to this main instruction queue, in order to the steering order that is stored in this main instruction queue is classified; One command generator is coupled to first output terminal of this order-sorter, in order to the steering order that sends according to this order-sorter, produces a plurality of steering orders; One first instruction queue is coupled between first output terminal and an external memory of this order-sorter, in order to store the steering order that is sent by this order-sorter; One second instruction queue is coupled to first output terminal of this command generator, the steering order that is sent by this command generator in order to storage; One the 3rd instruction queue is coupled to second output terminal of this command generator, the steering order that is sent by this command generator in order to storage; One the 4th instruction queue is coupled to the 3rd output terminal of this command generator, the steering order that is sent by this command generator in order to storage; One the five fingers make formation, are coupled to second output terminal of this order-sorter, in order to store the steering order that is sent by this order-sorter; One gets buffer zone soon, be coupled to the 4th instruction queue and this five fingers make formation, in order to the steering order of exporting according to this second instruction queue and the 3rd instruction queue, data that storage is received or read and be stored in this data to one of getting buffer zone soon video recording code translator; An and internal buffer, be coupled to this second instruction queue and the 3rd instruction queue, in order to the steering order of exporting according to this second instruction queue and the 3rd instruction queue, store data that an external memory transmits and maybe the data of this internal buffer are reached this and get buffer zone soon.
The present invention provides a kind of method of controlling video recording code translator fast access device in addition.This method comprises a plurality of steering orders of reception; Store these a plurality of steering orders in one first instruction queue; These a plurality of steering orders are classified; These a plurality of steering orders of classification transmission according to these a plurality of steering orders are organized second instruction queue at the most; Reaching one according to steering orders storage of first group of second instruction queues output of these many group second instruction queues gets the data of buffer zone soon or reads and be stored in this data to one of getting buffer zone soon video recording code translator; And the data storage that one external memory is transmitted according to the steering order of second group of second instruction queues output that should many group second instruction queues maybe reaches this with the data of this internal buffer in an internal buffer and gets buffer zone soon.
Description of drawings
Fig. 1 is the synoptic diagram of the video recording code translator fast access device of prior art.
Fig. 2 is the synoptic diagram of video recording code translator fast access device of the present invention.
Fig. 3 is that main instruction queue of the present invention receives the synoptic diagram when instructing.
Fig. 4 is the synoptic diagram that instruction queue of the present invention receives instruction.
The reference numeral explanation
100 200 video recording code translator fast access devices
110 210 fast instruction fetch devices
120 220 get buffer zone soon
111 instruction queues
112 212 order-sorters
130 230 DRAM (Dynamic Random Access Memory)
140 240 video recording code translators
221 internal buffers
211 main instruction queues
217 command generators
2131 read and get the buffer zone instruction queue soon
2132 write caching buffer zone instruction queues
2141 read the internal buffer instruction queue
2142 write the internal buffer instruction queue
215 read the DRAM (Dynamic Random Access Memory) instruction queue
Embodiment
Please refer to Fig. 2.Fig. 2 is the synoptic diagram of video recording code translator fast access device 200 of the present invention.Video recording code translator fast access device 200 comprises a fast instruction fetch device 210, and gets a buffer zone 220 and an internal buffer 221 soon.Comprise fast instruction fetch device 210 a main instruction queue 211, an order-sorter 212, a command generator 217, read gets buffer zone instruction queue 2131, a write caching buffer zone instruction queue 2132, soon and reads internal buffer instruction queue 2141, and write internal buffer instruction queue 2142 and and read DRAM (Dynamic Random Access Memory) instruction queue 215.
Main instruction queue 211 is coupled to outside in order to receive steering order.Order-sorter 212 is coupled to main instruction queue 211.Read and get first output terminal that buffer zone instruction queue 2131 is coupled to order-sorter 212 soon.Command generator 217 is coupled to second output terminal of order-sorter 212.Write caching buffer zone instruction queue 2132, read internal buffer instruction queue 2141, write internal buffer instruction queue 2142, DRAM (Dynamic Random Access Memory) instruction queue 215 is respectively coupled to command generator 217.Getting buffer zone 220 soon is coupled to read and gets buffer zone instruction queue 2132 and write caching buffer zone instruction queue 2132 soon.Internal buffer 221 is coupled to and reads internal buffer instruction queue 2141, writes internal buffer instruction queue 2142 and gets buffer zone 220 soon.DRAM (Dynamic Random Access Memory) 230 is coupled to and reads DRAM (Dynamic Random Access Memory) instruction queue 215 and internal buffer 221.Video recording code translator 240 is coupled to gets buffer zone 220 soon.
Main instruction queue 211 is in order to the steering order that receives and storage is sent by the outside.The steering order that the outside sends comprises the steering order that reads the steering order of getting buffer zone 220 soon and read DRAM (Dynamic Random Access Memory) 230.Order-sorter 212 is in order to the steering order that receives main instruction queue 211 and sent and with the steering order classification that is received, and steering order is divided into reads the steering order of getting buffer zone 220 soon and in first output terminal output of order-sorter 212 and the steering order that reads DRAM (Dynamic Random Access Memory) and in second output terminal output of order-sorter 212.For example if order-sorter 212 judges that the steering order that is received is to read the steering order of getting buffer zone 220 soon, then order-sorter 212 can be sent to this steering order to read and get buffer zone instruction queue 2131 soon, be resent to and get buffer zone soon, get buffer zone 220 soon and according to this steering order the data of being stored are sent to video recording code translator 240 again.If order-sorter 212 judges that the steering order that is received is to read the steering order of DRAM (Dynamic Random Access Memory), then order-sorter 212 can be sent to command generator 217 with steering order.Command generator 217 can produce a steering order that writes internal buffer 221 in addition accordingly according to the received steering order that reads DRAM (Dynamic Random Access Memory), one reads the steering order of internal buffer 221, the steering order of one write caching buffer zone 220, one reads the steering order of getting buffer zone 220 soon, and respectively above-mentioned steering order is sent into DRAM (Dynamic Random Access Memory) instruction queue 215, write internal buffer instruction queue 2142, read internal buffer instruction queue 2141, write caching buffer zone instruction queue 2132, read and get buffer zone instruction queue 2131 soon, and DRAM (Dynamic Random Access Memory) 230 is again via reading that DRAM (Dynamic Random Access Memory) instruction queue 215 receives these steering orders and according to this steering order, data are sent to internal buffer 221, and internal buffer 221 is also via reading internal buffer instruction queue 2141 and writing that internal buffer instruction queue 2142 receives steering orders and according to this steering order, the data storage that will be received from DRAM (Dynamic Random Access Memory) 230 also is sent to and gets buffer zone 220 soon, get soon then buffer zone 220 more internally the data storage of buffer zone 221 getting buffer zone 220 soon or be sent to video recording code translator 240.
Please refer to Fig. 3.Fig. 3 is the synoptic diagram that main instruction queue 211 of the present invention receives when instructing.As shown in the figure, suppose that main instruction queue 211 its degree of depth are 32, also can store 32 steering orders.Suppose to have received 32 external control instructions, preceding 28 is to read the steering order of getting buffer zone 220 soon, and 4 of back are the steering orders that reads DRAM (Dynamic Random Access Memory) 230.And hypothesis reads and gets buffer zone 220 soon and need 1 period of time T, and reading DRAM (Dynamic Random Access Memory) 230 needs 10 period of time T, and meaning promptly takes 10T, and data are sent to from DRAM (Dynamic Random Access Memory) 230 and get buffer zone 220 soon and take 1T.If use the video recording code translator fast access device 100 of prior art, in a time cycle, only transmit a steering order when last one steering order that reads DRAM (Dynamic Random Access Memory) is handled, take 1T+28T+10T+4T+1T=44T altogether.If use video recording code translator fast access device 200 of the present invention, please refer to Fig. 4.Fig. 4 is the synoptic diagram that instruction queue of the present invention receives instruction.Order-sorter 212 just can be sent to the steering order in the main instruction queue 211 at once to read and get buffer zone instruction queue 2131, write caching buffer zone instruction queue 2132 soon, reads internal buffer instruction queue 2141, writes internal buffer instruction queue 2142, reads DRAM (Dynamic Random Access Memory) instruction queue 215, as shown in Figure 4.By in the steering order that has 4 to read DRAM (Dynamic Random Access Memory) instruction queue 215, so order-sorter 212 can produce 4 steering orders that write the steering order of internal buffer, 4 steering orders that read the internal buffer and 4 write caching buffer zones again.And five instruction queues in Fig. 4 all can be carried out transfer control instruction simultaneously, therefore, shown in figure, be coupled to read and get getting buffer zone 220 soon and can finishing in the moment of (28+1) T and read of buffer zone instruction queue 2131 soon, can finish in the moment of (4+10) T and read and be coupled to the DRAM (Dynamic Random Access Memory) 230 that reads DRAM (Dynamic Random Access Memory) instruction queue 215.In addition, internal buffer 221 of the present invention can be carried out the action of reading and writing simultaneously, and therefore, data are sent to via internal buffer 221 from DRAM (Dynamic Random Access Memory) 230 and get buffer zone 220 soon and also take T equally.So finish when reading getting buffer zone 220 soon when the moment of 29T, because the data of DRAM (Dynamic Random Access Memory) 230 have been finished when (4+10) T and have been read, get buffer zone 220 soon and just can receive the data that DRAM (Dynamic Random Access Memory) 230 sends at once, and when 29+1+4=34T, finish and read.Hence one can see that, with video recording code translator fast access device of the present invention, the delay of reading DRAM (Dynamic Random Access Memory) can be hidden in and read among the running time of getting buffer zone soon, and then reach and improve the efficient that video recording is got soon.
To sum up state, video recording code translator fast access device of the present invention can send many steering orders simultaneously, so that higher access efficiency to be provided, need wait for when solving prior art and reading external memory and the problem of losing time.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.

Claims (12)

1. the video recording code translator fast access device of a tool multiple instruction flow comprises:
One fast instruction fetch device comprises:
One main instruction queue is in order to store the steering order that is sent by the outside;
One order-sorter is coupled to this main instruction queue, in order to the steering order that is stored in this main instruction queue is classified;
One command generator is coupled to first output terminal of this order-sorter, in order to the steering order that sends according to this order-sorter, produces a plurality of steering orders;
One first instruction queue is coupled between first output terminal and an external memory of this order-sorter, in order to store the steering order that is sent by this order-sorter;
One second instruction queue is coupled to first output terminal of this command generator, the steering order that is sent by this command generator in order to storage;
One the 3rd instruction queue is coupled to second output terminal of this command generator, the steering order that is sent by this command generator in order to storage;
One the 4th instruction queue is coupled to the 3rd output terminal of this command generator, the steering order that is sent by this command generator in order to storage; And
One the five fingers make formation, are coupled to second output terminal of this order-sorter, in order to store the steering order that is sent by this order-sorter;
One gets buffer zone soon, be coupled to the 4th instruction queue and this five fingers make formation, in order to the steering order of exporting according to this second instruction queue and the 3rd instruction queue, data that storage is received or read and be stored in this data to one of getting buffer zone soon video recording code translator; And
One internal buffer, be coupled to this second instruction queue and the 3rd instruction queue, in order to the steering order of exporting according to this second instruction queue and the 3rd instruction queue, store data that an external memory transmits and maybe the data of this internal buffer are reached this and get buffer zone soon.
2. video recording code translator fast access device as claimed in claim 1, wherein, this external memory is a DRAM (Dynamic Random Access Memory).
3. video recording code translator fast access device as claimed in claim 1, wherein, this fast instruction fetch device comprises an input end in addition, in order to receive a plurality of reading command.
4. video recording code translator fast access device as claimed in claim 1, wherein, this first, second, third, fourth, the five fingers make formation can export the steering order of being stored simultaneously.
5. video recording code translator fast access device as claimed in claim 1, wherein, this first instruction queue comprises an instruction queue reads this external memory in order to storage steering order.
6. video recording code translator fast access device as claimed in claim 1, wherein, these the five fingers make formation comprise an instruction queue and read the steering order that this gets buffer zone soon in order to storage.
7. video recording code translator fast access device as claimed in claim 1, wherein, the 4th instruction queue comprises an instruction queue and writes the steering order that this gets buffer zone soon in order to storage.
8. video recording code translator fast access device as claimed in claim 1, wherein, this second instruction queue comprises an instruction queue reads this internal buffer in order to storage steering order.
9. video recording code translator fast access device as claimed in claim 1, wherein, the 3rd instruction queue comprises an instruction queue writes this internal buffer in order to storage steering order.
10. method of controlling video recording code translator fast access device comprises:
Receive a plurality of steering orders;
Store these a plurality of steering orders in one first instruction queue;
These a plurality of steering orders are classified;
These a plurality of steering orders of classification transmission according to these a plurality of steering orders are organized second instruction queue at the most;
Reaching one according to steering orders storage of first group of second instruction queues output of these many group second instruction queues gets the data of buffer zone soon or reads and be stored in this data to one of getting buffer zone soon video recording code translator; And
The data storage that one external memory is transmitted according to the steering order of second group of second instruction queues output of these many group second instruction queues maybe reaches this with the data of this internal buffer in an internal buffer and gets buffer zone soon.
11. method as claimed in claim 10, wherein, the data storage that this external memory is transmitted according to the steering order of second group of second instruction queues output of these many group second instruction queues maybe reaches the data of this internal buffer this and gets buffer zone soon and comprise the data storage that one DRAM (Dynamic Random Access Memory) transmitted according to the steering order of second group of second instruction queues output that should many group second instruction queues and maybe the data of this internal buffer are reached this in this internal buffer and get buffer zone soon in this internal buffer.
12. method as claimed in claim 10, other comprises a plurality of reading command of reception to produce these a plurality of steering orders.
CN2006101366044A 2006-10-31 2006-10-31 Fast access device of video recording transcoder with multi-instruction flow and its control method Active CN101174202B (en)

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CN102540973B (en) * 2010-12-09 2013-06-26 中国科学院沈阳计算技术研究所有限公司 Implementation method for command multi-transmitting mechanism of numerical control system

Citations (4)

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CN1675626A (en) * 2002-08-12 2005-09-28 皇家飞利浦电子股份有限公司 Instruction cache way prediction for jump targets
CN1690952A (en) * 2004-04-22 2005-11-02 国际商业机器公司 Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache
WO2006031511A2 (en) * 2004-09-10 2006-03-23 Cavium Networks Store instruction ordering for multi-core processor
US20060095680A1 (en) * 2004-11-02 2006-05-04 Gi-Ho Park Processor with cache way prediction and method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1675626A (en) * 2002-08-12 2005-09-28 皇家飞利浦电子股份有限公司 Instruction cache way prediction for jump targets
CN1690952A (en) * 2004-04-22 2005-11-02 国际商业机器公司 Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache
WO2006031511A2 (en) * 2004-09-10 2006-03-23 Cavium Networks Store instruction ordering for multi-core processor
US20060095680A1 (en) * 2004-11-02 2006-05-04 Gi-Ho Park Processor with cache way prediction and method thereof

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Assignee: Ali Corporation

Assignor: Yangzhi Science & Technology Co., Ltd.

Contract record no.: 2012990000112

Denomination of invention: Fast access device of video recording transcoder with multi-instruction flow and its control method

Granted publication date: 20100915

License type: Exclusive License

Open date: 20080507

Record date: 20120316