CN101132245A - Digital synchronization series simple instrument implementing device - Google Patents
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- CN101132245A CN101132245A CNA2006101099024A CN200610109902A CN101132245A CN 101132245 A CN101132245 A CN 101132245A CN A2006101099024 A CNA2006101099024 A CN A2006101099024A CN 200610109902 A CN200610109902 A CN 200610109902A CN 101132245 A CN101132245 A CN 101132245A
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Abstract
This invention discloses a device for realizing simplified digital synchronous sequence instrument, which applies a current technological platform to realize cost to SDH equipment and test of error codes, at the sending direction, a data sequence generating unit generates data load to form a synchronous transfer mode signal of the synchronous digital sequence STM-N after channel process and segment process to be sent to a being tested unit, at the receiving direction, it receives being tested digital synchronous optical signals from the being tested unit to carry out photoelectric conversion to change it to electric signal to separate data sequence from it by segment and channel process and then a data sequence check unit compares the sequence with the pre-set data generated by the generating unit and presents a system bit error code and carry out error code instruction and report.
Description
Technical field
The present invention relates to a kind of testing apparatus of digital synchronous system in the communication technical field, relate in particular to a kind of digital synchronization series simple instrument implement device that expense and error code are detected.
Background technology
At present, the main flow of communication apparatus still is digital synchronization series (SDH, Synchronous DigitalHierarchy) equipment, and ATM (asynchronous transmission mould), GE business such as (gigabit Ethernets) can be assembled to and transmit on the SDH business, can improve the efficient of transmission, reduce the cost of unit bandwidth.Along with the increase and the development of technology of demand, the transfer rate of SDH is more and more higher, has reached present STM-256 from initial STM-1.Adopt the data multiplexing technology the professional synthetic SDH business at a high speed of the SDH of low speed, improved the usefulness that transmits, saved fiber resource, reduce the cost.
In order to improve the efficient of transmission, released dwdm system, each a professional certain wavelengths, transmittability raising hundreds of times of adopting.In order to improve transmitting range, go back standard OTN (optical transfer network) technology at present.
These systems become increasingly complex, and people are also more and more higher to the requirement of system simultaneously, need be to the complete test of carrying out of system.For the quality of the product that improves, improve production efficiency of products, in the process of producing, also need to provide detection means.But the test instrumentation of SDH is very expensive, in order to reduce the instrument cost of use of product, can develop the SDH detecting instrument that is used to the simplification of producing and debugging, satisfies the demand of producing.
SDH is a kind of advanced person's of the present extensive application that grows up in the nineties in 20th century a transmission system, it adopts the Time Division Multiplexing technology, stipulated serial speed, has unified bit rate, adopt unified light, electrical interface standard, a large amount of expenses is provided, and network management capabilities is strengthened greatly.Proposed the new ideas of self-healing network, formed the looped network form that has the self-healed protection ability, can when the transmission medium main signal is cut off, recover proper communication by self-healing network automatically with SDH equipment.Therefore the SDH business has very high QoS, satisfies the requirement of people to communication quality.
The STM-64 of SDH system (10Gb/s) system is commercial at present, is developing STM-256 (40Gb/s) commercial system at present.The speed of SDH regulation differs 4 times successively, is respectively STM-1/STM-4/STM-16/STM-64, at present converging for the SDH business, the general SDH framing chip that adopts, the SDH signal gathering of 4 road or 16 road low speed on SDH speed at a high speed, the block diagram of SDH service convergence as shown in Figure 1, wherein:
XA is rate adapted and the overhead processing functional block of SDH, finish the Clock Extraction of SDH data, with string and conversion, reduce the processing speed of data, finish the Performance Detection of receive path simultaneously, the expense of the SDH that receives is preserved, to be inserted in the expense on SDH group road later on, do transparent transmission, simultaneously, at sending direction the expense that the group road receives is assigned to each branch road, finishes the transparent transmission of expense.
XB is the pointer processing unit, is used to finish the processing of AU layer, comprises the detection of pointer, the Performance Detection of VC, and the regeneration of AU pointer is finished in the parsing of VC business in the other direction.SDH is by between the adaptive different passages of pointer, and the clock difference on receive path and group road guarantees the synchronous of clock.
1C is that AU selects and the distribution function piece, can provide short grained intersection to select, and can finish the reconciliation of converging of data and converge, and also can realize the loopback of passage.
1D is a group road adaptation overhead detection module, finish Clock Extraction and string and conversion, the Performance Detection on group road, the processing of expense, on sending direction, the branch road overhead transmission that receives is inserted into untapped position, group road, inserts the expense on group road, on receive direction, the overhead extraction that receives is come out, isolate the expense of the insertion of branch road, be sent to the xA functional block, realize the transparent transmission of expense.
In the present invention, we will adopt the multiple connection technology platform of ready-made SDH, through it is transformed, system is not re-used as transmission multiple connection product and uses, signal no longer receives data from the low rate port, does converging of data, and then sends from the high-speed data port.But, through the SDH coding, generate the SDH data again by the inner automatically generating certificate of detecting instrument device, according to the data that receive, provide the indication of receptivity at receiving terminal.The low speed data port is separate with the high-speed data port, and each port all produces the data of oneself, receives receiving terminal again and makes input.Each port can use simultaneously like this, can improve the volume of instrument.
Summary of the invention
Technical problem to be solved by this invention is, a kind of digital synchronization series simple instrument implement device is provided, and adopts expense and the Error detection of existing technology platform realization to SDH equipment.
The invention provides a kind of digital synchronization series simple instrument implement device, be used for aborning the unit under test of digital synchronization series is carried out error performance and straight-through performance detection, comprise program bootstrapping module and at least one transmitting-receiving detection module, wherein:
Program bootstrapping module, be used for the automatic operation of the synchronous series simple instrument of control figure, the automatic configuration service type in the back that powers on, the light Transmit-Receive Unit switch of control transmitting-receiving detection module reports and indicates receive path error code and alarm, and is used to be provided with the service rate of port;
The transmitting-receiving detection module, be used to generate and send the digital synchronization series light signal to unit under test, or receive digital synchronization series light signal to be measured and it is detected, or directly receive the digital synchronization series light signal of output and it is detected to the unit under test generating and sending the digital synchronization series light signal from unit under test from unit under test;
Wherein, described transmitting-receiving detection module comprises:
The data sequence generation unit is used to produce and send the data load with fixed sequence program, for follow-up cell processing;
The administrative unit data generating unit is used for receiving data load from the data sequence generation unit, and increases bit interleaved parity, the insertion Administrative Unit Pointer of path overhead, calculating passage in described data load, forms the administrative unit data;
Digital synchronization series signal generation unit, be used for receiving described administrative unit data from the administrative unit data generating unit, and to described administrative unit data add digital synchronization series frame signal, compute segment bit interleaved parity, insert section overhead, signal is carried out scrambler, form the synchronous transfer mode signal STM-N of synchronous digital hierarchy;
The light transmitting element is used to receive described STM-N signal, and after it was carried out electric light conversion, light signal to the unit under test that sends digital synchronization series was tested;
Light receiving unit is used for receiving the synchronous serial light signal of measured number from unit under test, and should carries out becoming the low speed signal of telecommunication after the light-to-current inversion by tested light signal, for follow-up cell processing;
Digital synchronization series signal resolution unit, be used for the digital synchronization series signal from light receiving unit is carried out frame detection, frame check, locking digital synchronization series frame, carry out STM-N signal descrambling code, extract the digital synchronization series expense and isolate the administrative unit data, the error code bit interleaved parity of the section of carrying out, the error code indication and the error code that provide the receiving port epimere report;
Administrative unit data parsing unit, be used to receive administrative unit data, handle split tunnel expense and data sequence through pointer from digital synchronization series signal resolution unit, carry out the bit interleaved parity of passage error code, calculate the error code indication and the alarm that provide passage;
The data sequence verification unit is used for the data sequence of receiving management cell data resolution unit, and the preset data that this data sequence and data sequence generation unit are produced is compared, and provides the systematic bits error code.
Further, the data load that produced of described data sequence generation unit is pseudo-random binary sequence PRBS data or complete " 1 " data or complete " 0 " data.
Further, the speed of the STM-N signal that produced of described digital synchronization series signal generation unit is STM-1 or STM-4 or the STM-16 or the STM-64 of synchronous digital hierarchy defined.
Further, when described unit under test connect the light transmitting element, whether the receive path that described device is used to detect unit under test was normal, comprised that service rate, frame detect, bit interleaved parity.
Further, when described unit under test connect light receiving unit, whether scrambler, frame structure, expense insertion function that described device is used to detect unit under test be correct.
Further, described unit under test cross-over connection is between described smooth transmitting element and described light receiving unit the time, and described device is used to detect the straight-through ability of speed, frame structure, bit interleaved parity error code and signal of unit under test.
Further, described data sequence generation unit, administrative unit data generating unit, digital synchronization series signal generation unit, digital synchronization series signal resolution unit, administrative unit data parsing unit, data sequence verification unit realize on digital synchronous pattern framing chip or on-site programmable gate array FPGA.When adopting FPGA, described device further comprises the error code counting module, and the error code that is used to add up counting provides performance to report and inquires about required error code counting.
Further, when described synchronous series of signals was STM-16 or STM-64, serial/separating the serial chip carried out low speed/high speed or high speed/low speed electrical signal conversion for described digital synchronization series signal generation unit and the employing of described digital synchronization series signal resolution unit.
Further, when described device directly links to each other with light receiving unit at described smooth transmitting element, be used to detect the signal quality of reception, whether the mistake of frame and the function that error code is verified transceiver channel arranged according to received signal.
Device integrated level height of the present invention can hold the transmission and the reception of multichannel simultaneously, is equivalent to a plurality of Error Detectors, and this device is again the simplification of Error Detector simultaneously, only supports the function that error code function and expense detect.Speed is supported STM-1/STM-4/STM-16/STM-64, is fit to produce use.Adopt device of the present invention, the SDH simple instrument of a large amount of cheapness can be provided for production, the business in the time of can realizing producing detects, and has improved the veneer detection range, improves the production First Pass Yield of veneer.Characteristics such as this device has small size, and port is many, and supporting business is many, and cost is low, and power consumption is little.
Description of drawings
Fig. 1 is the block diagram of digital synchronization series service convergence in the prior art;
Fig. 2 adopts existing multiple connection structure to make up the principle schematic of SDH testing apparatus in the embodiment of the invention;
Fig. 3 is a kind of composition frame chart of SDH simple instrument in the embodiment of the invention;
Fig. 4 is to be the simple and easy Error Detector of SDH of three kinds of speed STM-1/STM-4/STM-16 of fundamental construction with the STM-16 multiplexing chip in the embodiment of the invention;
Fig. 5 is to be the simple and easy Error Detector of SDH of two kinds of speed STM-16/STM-64 of fundamental construction with the STM-64 multiplexing chip in the embodiment of the invention;
Fig. 6 is to be the simple and easy Error Detector of SDH of three kinds of speed STM-1/STM-4/STM-16 of fundamental construction with the FPGA high-speed chip in the embodiment of the invention;
Fig. 7 is to be that the veneer of the professional measuring ability automatically of having of fundamental construction is used block diagram with the STM-16 multiplexing chip in the embodiment of the invention.
Embodiment
Below in conjunction with specific embodiment and accompanying drawing technical solutions according to the invention are elaborated.Below, enumerated several typical way that embody the present invention's design, be the specific implementation that realizes SDH simple instrument implement device, do not use other embodiment that embodies design of the present invention but do not get rid of.
As shown in Figure 2, in the present invention, we adopt the multiple connection technology platform of ready-made SDH, through it is transformed, system is not using as transmission multiple connection product, and signal no longer receives data from the low rate port, do converging of data, and then send from the high-speed data port.But, through the SDH coding, generate the SDH data again by the inner automatically generating certificate of detecting instrument device, according to receiving data, provide the indication of receptivity at receiving terminal.The low speed data port is separate with the high-speed data port, and each port all produces the data of oneself, receives receiving terminal again and makes input.Among Fig. 2, existing multiple connection structure has been divided into three parts, and each port can use simultaneously, can improve the volume of instrument.
The present invention only provides the detection of expense and the detection of BIP error code.Do the checking of professional straight-through property and the detection of error performance in the time of can only be as link between aborning and debugging.Can only be as the detection means of SDH business, can not be as the performance instrument of complete SDH.The SDH performance test of dispatching from the factory need be adopted special-purpose SDH instrument.
As shown in Figure 3, provide the implement device of a typical port of SDH simple instrument, can on a veneer, realize the transmission of SDH of many speed, multiport and the detection of SDH business, can be used as the SDH Error detection.This programme has multichannel, many speed, low cost, small size, characteristics such as low-power consumption.
At current SDH multiple connection and delivery unit, original data-transmission channel is interrupted.Do not realize that signal transforms to the conversion of another port from a port.The business of low-speed port does not have association with high-speed port, and each port all is separate.At the transmitting terminal of each port, the inner signal data that produces through framer, produces the signal of SDH form; At receiving terminal, receive the SDH signal, make error performance detection and other overhead processing, recover internal data and compare with default data.
Use as instrument like this, can send the SDH signal, for the receptivity of unit under test (DNT) Receipt Validation SDH by instrument.Also can be placed on unit under test and do professional straight-through property experiment between transmitting terminal and the receiving terminal.
As shown in Figure 3, system comprises the data sequence generation unit, path overhead processing unit, section overhead processing unit, parts such as optical transceiver module.For instrument allows automatically, also comprise bootstrap routine, the back configuration service type automatically that powers on, the switch of control optical module reports and indicates receive path error code and alarm.
For convenient test, professional speed that each port is given when needing is opened laser, does professional the detection, and the laser of cutting out the corresponding port when not required is to prolong the useful life of instrument.This device is a multiport, the system of many speed, for each port wherein, wherein:
Whether the light that unit under test connects the SDH simple instrument sends, can check the receive path of unit under test normal, comprises service rate, and frame detects, functions such as BIP verification.The light-receiving that unit under test connects the SDH simple instrument can be checked the scrambler of unit under test, frame structure, and whether functions such as expense insertion are correct.Unit under test jump to the SDH simple instrument light send and light-receiving between, can check the speed of unit under test, frame structure, BIP error code, and the straight-through ability of signal.
Above-mentioned data sequence generation unit, administrative unit data generating unit, digital synchronization series signal generation unit, light transmitting element, receiving element, digital synchronization series signal resolution unit, administrative unit data parsing unit, data sequence verification unit, can be considered as a transmitting-receiving detection module on the whole, remove the light Transmit-Receive Unit, other parts can be realized by framer or FPGA.
If mixing power supply, unit and display unit are set, just can be used as semi-professional Error Detector.Also can adopt the pattern of veneer, directly use as simple and easy Error Detector.
As shown in Figure 4, be the realization block diagram of present embodiment 1.In the present embodiment 1,, made up the simple and easy Error Detector of the SDH with three kinds of speed STM-1/STM-4/STM-16 based on the multiplexing chip of STM-16.
The multiplexing chip of STM-16 generally can be finished 16 STM-1 or 4 STM-4 or their multiple connection that is combined to STM-16 and conciliate multiple connection, can finish in theory and have a STM-16 speed, SDH simple instrument with 16 STM-1 speed or 4 STM-4 speed ports or their combination, simple in order to realize, here the simple instrument that define comprises 1 STM-16,2 road STM-4, the SDH error code testing function of three kinds of speed of 2 road STM-1.
Three kinds of speed block diagrams are the same with structure, are the port difference of chip, the service rate difference of support.Length for the purpose of simplifying the description, we are that example comes it is elaborated with STM-4, because the principle of STM-1/STM-16 is the same with STM-4, only do relevant explanation simultaneously.
With reference to Fig. 4, wherein, the block diagram of STM-1 comprises 31～38, and the block diagram of STM-4 comprises 21～28, and the block diagram of STM-16 comprises 11～18.
For convenient test, integrated PRBS generator in chip can be used as the generation source of data, and therefore, data are produced by the PRBS module in module 21.Correspondingly, be module 31 at STM-1, be module 11 at STM-16.
The data load that is produced is delivered to module 22 by module 21, calculates the BIP verification of passage in this module 22, increases path overhead in the load that receives, and inserts the AU pointer then, forms the AU data.General data can be set to AU4-4c at STM-4; Can be set to AU4 at STM-1; Can be set to AU4-4c or AU4-16c at STM-16.
The STM-4 signal that optical module 24 sends 23 modules is done the electric light conversion, provides the light signal of SDH to use for test cell.In order to improve the life-span of Error Detector, laser can turn-off by order when not using.At module 34 output STM-1 light signals.At module 14 output STM-16 light signals.
For STM-1 and STM-4 signal, signal receives data from module 35, module 25, inserts in the chip, but for STM-16, because speed is higher, signal receives data from module 15, needs through SERDES just to receive in the chip after (serial, separate the serial chip) becomes low speed signal.
In module 26, module 16, module 36, after signal inserts chip, check, lock the SDH frame through frame detection, frame, to STM-N signal descrambling code, extract the SDH expense and isolate the AU data; Simultaneously, the BIP error checking of the section of carrying out, section error code indication and the error code that provide receiving port report, and are B1/B2 as what produce use care generally, if demand is arranged, also can increase the detection to other expense.
In module 27, the AU data of receiver module 26 are handled through pointer, split tunnel expense and data, and passage error code BIP calculates error code indication and the alarm that provides passage.Data are delivered to data verification units 28.Correspondingly, module 17 and module 37 finishes STM-16 and STM-1 handles accordingly.
In module 28, the data of reception and the PRBS data of module 21 are compared, can provide the BIT error code of receiving port.Module 18 and module 38 also can finish STM-16 and STM-1 handles accordingly.
Whether when unit under test connects the light transmission of SDH simple instrument, can check the receive path of unit under test normal, comprise service rate, frame detects, functions such as BIP verification.When unit under test connects the light-receiving of SDH simple instrument, can check the scrambler of unit under test, frame structure, whether functions such as expense insertion are correct.The light that unit under test jumps to the SDH simple instrument simultaneously send and light-receiving between the time, can check the straight-through ability of speed, frame structure, BIP error code and signal of unit under test.
The BIT error code here is different with the BIP error code, the Error detection during BIP on the SDH layer, and the bit-errors of PRBS or other data detects during BIT, they are different, and general requirement is not strict, can be indifferent to the BIT error code, the BIP Error detection is that we are concerned about very much, is B1/B2 in SDH.
Here, this testing apparatus can have three kinds of test modes:
1) as signal source, whether main consideration is to detect the receiving port that is equipped with measurement equipment to meet the demands, and can detect the signal rate of measurement equipment fully, Clock Extraction, frame detects, functions such as BIP Error detection, and SDH is the structure of standard, stipulated frame structure, speed, expense etc.The BIT error code can not considered, because data format can not be predicted.
2) as Authentication devices, main consideration is to detect the transmit port that is equipped with measurement equipment whether to meet the SDH standard-required, can detect the transmission signal rate of measurement equipment fully, functions such as expense insertion.SDH is the structure of standard, has stipulated frame structure, speed, expense etc.
3) signal sends to unit under test from light, through being input to light-receiving after the unit under test output.
Further, if present embodiment 1 described device is mixed power supply again, unit and display unit are set, just can be used as semi-professional Error Detector.Can on original veneer, not make other yet and revise, do not revise the profile supply power mode of original veneer, only change the function of veneer, directly use as simple and easy Error Detector.
As shown in Figure 5, present embodiment 2 makes up the simple and easy Error Detector of SDH with two kinds of speed STM-16/STM-64 based on the STM-64 multiplexing chip.The STM-64 multiplexing chip generally can be finished 4 STM-16 and conciliate multiple connection to the multiple connection of STM-64, utilizes built-in PRBS module to produce data-signal internally now, can realize the SDH error code testing function of 4 road STM-16 and 1 road STM-64.
In Fig. 5, the block diagram of two kinds of speed STM-16 and STM-64 is the same with structure, the port difference of chip just, the service rate difference of support.Length for the purpose of simplifying the description only is that example describes with STM-64, and the principle of STM-16 is the same with STM-64, does relevant explanation simultaneously.The block diagram of STM-16 comprises module 121～128, and the block diagram of STM-64 comprises module 111～118.
In module 111, module 121, utilize the PRBS generator of built-in chip type, produce data load, and data load is delivered to corresponding thereafter module 112 and module 122.
In module 112 and module 122, in received load, add path overhead, calculate the BIP verification of passage, insert the AU pointer then, form the AU data.
In module 113 and module 123, in receiving the AU data of coming, add the SDH frame signal, section overhead is inserted in the BIP verification of compute segment, again signal is carried out scrambler, thereby form the signal of SDH, promptly the STM-N signal is sent into each self-corresponding module 114 and module 124.
The STM-64 that optical transmission module 114,124 is sent 113,123 modules here, STM-16 signal are done the electric light conversion, and the light signal of SDH is provided to unit under test.Because chip port can not be supported the speed that STM-16 and STM-64 are high like this, the outside needs to increase SERDES (serial, separate the serial chip), for the independent SERDES chip of the general employing of STM-16, to the STM-64 signal, because speed is higher, SERDES integrates with optical transmission module, and this part is not an emphasis, does not indicate on block diagram.When providing the SDH light signal to use for test cell, in order to improve the life-span of Error Detector, laser can turn-off by order when not using.
Module 115, module 125 are Optical Receivers, can receiving optical signals, and light signal become the signal of telecommunication is delivered to corresponding module 116, module 126 is handled.Wherein, because the service rate height, need through SERDES again the signal of telecommunication to be delivered to module 116, module 126 after (serial, separate the serial chip) becomes low speed signal.
The low speed signal of telecommunication that module 116,126 pairs of modules receive is checked, is locked the SDH frame through frame detection, frame after inserting chip, to STM-N signal descrambling code, extracts the SDH expense and also isolates the AU data; The BIP error checking of the section of carrying out, section error code indication and the error code that provide receiving port report, and are B1/B2 as what produce use care generally, if demand is arranged, can increase the detection to other expense.
In module 117, module 127, receive the AU data of sending from module 116, module 126.Handle through pointer, split tunnel expense and data, the error code that utilizes passage error code BIP calculating to provide passage is indicated and alarm, and the data of separating are delivered to data verification units module 118, module 128.
In module 118, module 128, the PRBS data of the data that receive and module 111, module 121 are compared, can provide the BIT error code of receiving port.
Whether the light that unit under test connects the SDH simple instrument sends, can check the receive path of unit under test normal, comprises service rate, and frame detects, functions such as BIP verification.Unit under test connect the SDH simple instrument light-receiving can check the scrambler of unit under test, frame structure, whether functions such as expense insertion correct.Unit under test jump to simultaneously the SDH simple instrument light send and light-receiving between, can check the speed of unit under test, frame structure, BIP error code, and the straight-through ability of signal.
Module 119, be program bootstrapping module, it is expressed as software section, and the automatic operation of SDH simple instrument, the demonstration and the reporting functions of error code are provided, as instrument the time, the detection that can the while come respectively different unit under tests to be carried out the BIP error code as the independent instrument of 2 kinds of speed of 5.
Further, if mix power supply again, unit and display unit are set, just can be used as semi-professional Error Detector.Certainly, can be not yet top in addition, and directly use as simple and easy Error Detector, it is provided with environment merchandiser plate is the same.
As shown in Figure 6, be the realization block diagram of embodiment 3 correspondences, this embodiment 3 makes up the simple and easy Error Detector of the SDH with three kinds of speed STM-1/STM-4/STM-16 based on FPGA.This embodiment 3 is identical with the scheme of described embodiment 1, and difference is: have only the means difference of realization, adopt framer (FRAMER) to make up among the embodiment 1,2, and adopt FPGA to make up among the embodiment 3.In present embodiment 3, the speed that FPGA can the flexible configuration port, each port can be made as STM-1/STM-4/STM-16, and port number can increase as required, subtract.Simple in order to realize, the simple instrument among the definition embodiment 3 comprises the SDH error code testing function of 1 STM-16,2 road STM-4, three kinds of speed of 2 road STM-1.
Three kinds of speed block diagrams shown in Fig. 6 are the same with structure, are the port difference of chip, the service rate difference of support.Length for the purpose of simplifying the description no longer describes in detail here, and the function of its each module is referring to embodiment 1.
In this embodiment 3, module 229 shown in Figure 6 is listed separately, is because when adopting framer FRAMER in embodiment 1, the counting of error code is finished by framing chip, and when adopting FPGA, the error code that then needs to add up counting is so that the confession performance reports and inquires about.
In present embodiment 3, the data of 211,221,231 modules generate more flexible, can be set to the PRBS sequence, also can adopt fixing sequence to generate, such as the data sequence that adopts complete " 1 " or complete " 0 ".And in 218,228,238 modules as the data check unit, compare by the predetermined data sequence that is produced with 211,221,231 modules, provide the twin check result.
As shown in Figure 7, present embodiment 4 is an example with STM-16, has made up to have a professional application example of measuring ability automatically, and this example is equivalent to the self-checking function of the simple and easy Error Detector of SDH.After carrying out professional self check, veneer is talked about normally, then can guarantee the single board service operate as normal.
By the instrument function test of veneer, just can verify the correctness of the business unit of veneer.Guarantee after each business unit of veneer normal, switch to the normal situation about using of veneer by software again, data are multiplexed into high-speed port from low-speed port, can improve the coverage rate of test, the veneer of promptly being not only assembling detects, can also utilize this simple instrument that each business unit of veneer is detected in advance, thereby improve the First Pass Yield of production, improve the production capacity of product.This also calculates the contribution of Error Detector to single-board testing.Simple and easy Error Detector not only can also can be used to produce the professional self check of veneer for other veneers provide the Error detection function, the initial failure detectability of veneer.
Adopt device of the present invention, can realize simultaneously that many speed of multichannel SDH signal produces and detects, with low cost, the processing and the detection of expense can be provided, can conveniently realize the function expansion.
Device of the present invention adopts present existing technology platform, realizes producing cheaply the SDH operational trials instrument of debugging usefulness, can reduce the production cost of entire product, improves the quality of product.
Device of the present invention just designs as producing the cheap SDH instrument of using; mainly need to detect BIP (bit interleaved parity; Bit Interleaved Parity) error code; detection with LOS/LOF; not complete SDH test instrumentation, for complete SDH functional test, such as alarm; protection is switched, and shake waits the special test instrumentation of performance need.
Each embodiment described in the present invention only is several typical way that embody the present invention's design, does not get rid of other embodiment that use and embody design of the present invention.
Claims (10)
1. digital synchronization series simple instrument implement device is used for aborning the unit under test of digital synchronization series is carried out error performance and straight-through performance detection, it is characterized in that, comprises program bootstrapping module and at least one transmitting-receiving detection module, wherein:
Program bootstrapping module, be used for the automatic operation of the synchronous series simple instrument of control figure, the automatic configuration service type in the back that powers on, the light Transmit-Receive Unit switch of control transmitting-receiving detection module reports and indicates receive path error code and alarm, and is used to be provided with the service rate of port;
The transmitting-receiving detection module, be used to generate and send the digital synchronization series light signal to unit under test, or receive digital synchronization series light signal to be measured and it is detected, or directly receive the digital synchronization series light signal of output and it is detected to the unit under test generating and sending the digital synchronization series light signal from unit under test from unit under test;
Wherein, described transmitting-receiving detection module comprises:
The data sequence generation unit is used to produce and send the data load with fixed sequence program, for follow-up cell processing;
The administrative unit data generating unit is used for receiving data load from the data sequence generation unit, and increases bit interleaved parity, the insertion Administrative Unit Pointer of path overhead, calculating passage in described data load, forms the administrative unit data;
Digital synchronization series signal generation unit, be used for receiving described administrative unit data from the administrative unit data generating unit, and to described administrative unit data add digital synchronization series frame signal, compute segment bit interleaved parity, insert section overhead, signal is carried out scrambler, form the synchronous transfer mode signal STM-N of synchronous digital hierarchy;
The light transmitting element is used to receive described STM-N signal, and after it was carried out electric light conversion, light signal to the unit under test that sends digital synchronization series was tested;
Light receiving unit is used for receiving the synchronous serial light signal of measured number from unit under test, and should carries out becoming the low speed signal of telecommunication after the light-to-current inversion by tested light signal, for follow-up cell processing;
Digital synchronization series signal resolution unit, be used for the digital synchronization series signal from light receiving unit is carried out frame detection, frame check, locking digital synchronization series frame, carry out STM-N signal descrambling code, extract the digital synchronization series expense and isolate the administrative unit data, the error code bit interleaved parity of the section of carrying out, the error code indication and the error code that provide the receiving port epimere report;
Administrative unit data parsing unit, be used to receive administrative unit data, handle split tunnel expense and data sequence through pointer from digital synchronization series signal resolution unit, carry out the bit interleaved parity of passage error code, calculate the error code indication and the alarm that provide passage;
The data sequence verification unit is used for the data sequence of receiving management cell data resolution unit, and the preset data that this data sequence and data sequence generation unit are produced is compared, and provides the systematic bits error code.
2. device as claimed in claim 1 is characterized in that, the data load that described data sequence generation unit is produced is pseudo-random binary sequence PRBS data or complete " 1 " data or complete " 0 " data.
3. device as claimed in claim 1 is characterized in that, the speed of the STM-N signal that described digital synchronization series signal generation unit is produced is STM-1 or STM-4 or the STM-16 or the STM-64 of synchronous digital hierarchy defined.
4. device as claimed in claim 1 is characterized in that, when described unit under test connect the light transmitting element, whether the receive path that described device is used to detect unit under test was normal, comprises that service rate, frame detect, bit interleaved parity.
5. device as claimed in claim 1 is characterized in that, when described unit under test connect light receiving unit, whether scrambler, frame structure, expense insertion function that described device is used to detect unit under test be correct.
6. device as claimed in claim 1, it is characterized in that, described unit under test cross-over connection is between described smooth transmitting element and described light receiving unit the time, and described device is used to detect the straight-through ability of speed, frame structure, bit interleaved parity error code and signal of unit under test.
7. device as claimed in claim 1, it is characterized in that described data sequence generation unit, administrative unit data generating unit, digital synchronization series signal generation unit, digital synchronization series signal resolution unit, administrative unit data parsing unit, data sequence verification unit realize on digital synchronous pattern framing chip or on-site programmable gate array FPGA.
8. as claim 1 or 7 described devices, it is characterized in that when adopting FPGA, described device further comprises the error code counting module, the error code that is used to add up counting provides performance to report and inquires about required error code counting.
9. as claim 1 or 3 described devices, it is characterized in that, when described synchronous series of signals was STM-16 or STM-64, serial/separating the serial chip carried out low speed/high speed or high speed/low speed electrical signal conversion for described digital synchronization series signal generation unit and the employing of described digital synchronization series signal resolution unit.
10. device as claimed in claim 1, it is characterized in that, when described device directly links to each other with light receiving unit at described smooth transmitting element, be used to detect the signal quality of reception, whether the mistake of frame and the function that error code is verified transceiver channel arranged according to received signal.
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