CN101116129A - Method and system for programming, calibrating and driving a light emitting device display - Google Patents

Method and system for programming, calibrating and driving a light emitting device display Download PDF

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Publication number
CN101116129A
CN101116129A CNA2005800480205A CN200580048020A CN101116129A CN 101116129 A CN101116129 A CN 101116129A CN A2005800480205 A CNA2005800480205 A CN A2005800480205A CN 200580048020 A CN200580048020 A CN 200580048020A CN 101116129 A CN101116129 A CN 101116129A
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voltage
pixel circuit
current
programming
calibration
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CNA2005800480205A
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CN101116129B (en
Inventor
A·内森
G·R·查吉
P·塞尔瓦蒂
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Ignis Innovation Inc
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Ignis Innovation Inc
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Priority claimed from CA 2503237 external-priority patent/CA2503237A1/en
Priority claimed from CA002509201A external-priority patent/CA2509201A1/en
Priority claimed from CA002521986A external-priority patent/CA2521986A1/en
Application filed by Ignis Innovation Inc filed Critical Ignis Innovation Inc
Priority claimed from PCT/CA2005/001897 external-priority patent/WO2006063448A1/en
Publication of CN101116129A publication Critical patent/CN101116129A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0285—Improving the quality of display appearance using tables for spatial correction of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

This invention presents a scheduling method and algorithm for calibration of pixels in active-matrix organic light-emitting diode (AMOLED) displays. The pixels are calibrated based on their aging and usage during the normal operation of active matrix display. The display data is used to determine the pixels with high brightness for calibration, which guarantees high speed and accurate calibration. This method can be used with any current programmed pixels, in particular, current mirror based designs.

Description

Method and system for programming, calibrating and driving a light emitting device display
Technical Field
The present invention relates to display technology, and more particularly, to a method and system for programming, calibrating and driving a light emitting device display.
Background
Recently, active Matrix Organic Light Emitting Diode (AMOLED) displays with amorphous silicon (a-Si), polysilicon, organic or other driving backplanes have become more attractive due to their advantages over active matrix liquid crystal displays. These advantages include, for example, the use of a-Si, which has advantages of low production cost, high resolution, and wide viewing angle, in addition to its low temperature fabrication allowing a wide variety of substrates to be used and flexible display to be achieved.
An AMOLED display includes an array of rows and columns of pixels in which are disposed Organic Light Emitting Diodes (OLEDs) and backplane electronics. Since the OLED is a current driving device, the pixel circuit of the AMOLED should be able to provide an accurate and constant driving current.
U.S. Pat. No. 6,594,606 discloses a method and system for calibrating passive pixels. U.S. Pat. No. 6,594,606 measures data line voltage and uses the measurement of precharge. However, this technique does not provide the accuracy required for an active matrix since the active matrix calibration should be effective for both backplane aging and OLED aging. Furthermore, after the pre-charging, current programming must be performed. Current programming of current driven pixels is slow due to parasitic line capacitance and suffers from non-uniformity of large displays. Speed can become an issue when programming with small currents.
Other compensation techniques have been proposed. However, there is still a need to provide a method and system that can provide constant brightness, achieve high accuracy, and reduce the effects of pixel circuit aging.
Disclosure of Invention
It is an object of the present invention to provide a method and system that eliminates or mitigates at least one disadvantage of existing systems.
According to one aspect of the present invention, there is provided a method of real-time calibration of a display array having a plurality of pixel circuits arranged in rows and columns, the method comprising the steps of: generating a priority list of pixels for prioritizing pixels for calibration based on display and previous calibration data, using the priority list to select one or more (n) pixels, programming the selected pixels with a current higher than a threshold current for calibration; selecting n pixels in a selected column of the display array from the chain table; programming pixels in the selected column, comprising: monitoring pixel currents of the n pixels and obtaining calibration data; updating the compensation memory according to the calibration data for calibration; the next programmed priority list is sorted.
According to another aspect of the present invention, there is provided a system for real-time calibration of a display array having a plurality of pixel circuits arranged in rows and columns, each pixel circuit having a light emitting device and a drive transistor, the system comprising: a calibration scheduler for controlling programming and calibration of a display array, comprising: listing a priority list of one or more pixels for calibration based on the display data; a module that initiates a calibration mode for one or more pixels in a selected column selected from the priority list during a programming cycle and a normal operating mode for the remaining pixels in the selected column during the programming cycle; a monitor for monitoring a pixel current of a pixel in a calibration mode on a selected column; a generator for generating calibration data based on the monitoring result; a memory for storing calibration data; and an adjuster that adjusts the programming data applied to the display array according to the calibration data when programming the pixels in the normal operation mode.
According to another aspect of the invention, there is provided a system for a display array with pixel circuits programmed via data lines, the system comprising: a data source for providing programming data into the pixel circuit; a current controlled voltage source associated with the voltage source for converting the current on the data line to a voltage associated with the current to extract a time varying parameter of the pixel circuit.
According to another aspect of the present invention, there is provided a system for a display array comprising a plurality of pixel circuits, each pixel circuit comprising a drive transistor, at least one switching transistor, a storage capacitor and a light emitting device, the system comprising: a monitor for monitoring a current or a voltage of the pixel circuit; a data processing unit for controlling the operation of the display array, the data processing unit extracting information about the aging of the pixel circuit according to the monitored current or voltage and determining the state of the pixel circuit; a driver controlled by the data processing unit and adapted to provide the pixel circuit with programming and calibration data in dependence of the state of the pixel circuit.
According to another aspect of the present invention, there is provided a method of driving a display array including a plurality of pixel circuits each including a driving transistor, at least one switching transistor, a storage capacitor, and a light emitting device, the method including the steps of: applying a current or voltage to the pixel circuit; monitoring a current or voltage flowing through the pixel circuit; extracting information about the aging of the pixel circuit from the monitored current or voltage and determining the state of the pixel circuit; the operating voltages are provided to the pixel circuit, including determining programming and calibration data for the pixel circuit based on the state of the pixel circuit.
According to another aspect of the present invention, there is provided a method of driving a display array including a plurality of pixel circuits each including a driving transistor, at least one switching transistor, a storage capacitor, and a light emitting device, the method including the steps of: applying a current or voltage to the light emitting device; monitoring a current or voltage flowing through the light emitting device; predicting a voltage shift of the light emitting device based on the monitored current or voltage; and providing a bias to the light emitting device associated with a voltage shift of the light emitting device.
According to another aspect of the present invention, there is provided a system for driving a display array comprising a plurality of pixel circuits, each pixel circuit comprising a drive transistor, at least one switching transistor, a storage capacitor and a light emitting device, the system comprising: a monitor for monitoring a current or a voltage of the pixel circuit; a data processing unit for predicting a voltage deviation of the light emitting device according to the monitored current or voltage and determining a state of the pixel circuit; and a circuit for providing a bias to the light emitting device associated with a voltage offset of the light emitting device.
According to another aspect of the present invention, there is provided a system for a display array comprising a plurality of pixel circuits, each pixel circuit comprising a drive transistor, at least one switching transistor, a storage capacitor and a light emitting device in a programming path for programming the pixel circuits, the system comprising: a controller for controlling operation of the display array; a driver for supplying an operating voltage to the pixel circuit according to control of the controller; and a driver for supplying an operating voltage to the pixel circuit during a programming period to remove the light emitting device from the programming path.
This summary of the invention does not necessarily describe all features of the invention.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following detailed description of the preferred embodiments in conjunction with the accompanying figures.
Drawings
These and other features of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings wherein:
FIG. 1 is a flow diagram illustrating a correction scheduling process according to one embodiment of the invention;
FIG. 2 is a diagram showing one example of a system structure for performing the corrective scheduling of FIG. 1;
FIG. 3 is a diagram illustrating a system architecture for voltage extraction, programming and driving, according to one embodiment of the present invention;
FIG. 4 is a diagram showing one example of the extraction, programming and driving system and pixel circuit of FIG. 3;
FIG. 5 is a diagram showing another example of the extraction, programming and driving system and pixel circuit of FIG. 3;
FIG. 6 is a diagram showing another example of the extraction, programming and driving system of FIG. 3 and a pixel circuit;
FIG. 7 is a diagram showing another example of the extraction, programming and driving system of FIG. 3 and a pixel circuit;
fig. 8 is a diagram showing a pixel circuit to which a step calibration driving according to an embodiment of the present invention is applied;
FIG. 9 is a diagram showing one example of a driver and extraction module and the drive transistor of FIG. 8;
FIG. 10 is a diagram illustrating one example of an extraction algorithm performed by the DPU module of FIG. 9;
FIG. 11 is a diagram illustrating another example of an extraction algorithm performed by the DPU module of FIG. 9;
fig. 12 is a timing chart showing one example of waveforms for step calibration driving;
fig. 13 is a timing chart showing another example of waveforms for step calibration driving;
fig. 14 is a diagram showing a pixel circuit to which step calibration driving can be applied;
fig. 15 is a graph showing a simulation result for the step calibration driving;
FIG. 16 is a diagram illustrating one embodiment of a system architecture for step calibration driving with a display array;
FIG. 17 is a timing diagram showing one example of waveforms applied to the system architecture of FIG. 16;
FIG. 18 is a timing diagram showing one example of waveforms for voltage/current extraction;
FIG. 19 is a timing diagram showing another example of waveforms for voltage/current extraction;
FIG. 20 is a diagram of a pixel circuit to which the voltage/current extraction of FIG. 19 can be applied;
FIG. 21 is a timing diagram showing another example of waveforms for voltage/current extraction;
fig. 22 is a diagram showing a pixel circuit to which the voltage/current extraction of fig. 21 can be applied;
FIG. 23 is a diagram illustrating a mirror-based pixel circuit to which OLED removal according to one embodiment of the present invention is applied;
FIG. 24 is a diagram showing the programming path of FIG. 23 when OLED removal is applied;
FIG. 25 is a diagram showing one example of a system configuration for OLED removal;
fig. 26 is a graph showing simulation results for voltages on IDATA lines with different threshold voltages.
Detailed Description
Embodiments of the present invention will now be described using a pixel including a light emitting device and a plurality of transistors. The light emitting device may be an Organic Light Emitting Diode (OLED). It should be noted that "pixel" and "pixel circuit" may be used interchangeably.
The real-time calibration schedule for a display array having a plurality of pixels is described in detail below. FIG. 1 illustrates a calibration scheduling process according to one embodiment of the present invention. According to this technique, the pixels are calibrated according to pixel aging and/or usage in normal operation of the display array.
In step S2 a linked list of pixels is generated. The linked list contains the identification of pixels with high brightness for calibration. A linked list is used to schedule the priorities for the calibrations.
In step S4, "n" is selected according to the display size and the desired instability over time (e.g., shift of the characteristic curves of the transistors and the light emitting devices). "n" represents the number of pixels calibrated in each programming cycle. "n" may be greater than or equal to 1.
Then, in step S6, a programming cycle begins. Step S6 includes steps S8-S16. Steps S8-S16 are performed for the selected column of the display array.
In step S8, "n" pixels in the selected column, hereinafter referred to as "selected pixels", are selected from the beginning of the linked list.
In step S10, a "calibration mode" is initiated for the selected pixel and a "normal operating mode" is initiated for the remaining pixels in the selected column of the display array.
In step S12, all pixels in the selected column are programmed by a voltage source driver (e.g., 28 of fig. 2) connected to the data lines of the pixels.
The current through the data line is monitored during the programming cycle for the selected pixel. For pixels in the selected column other than the selected pixel, the data stored in a memory (e.g., 34 of FIG. 2), hereinafter referred to as "Δ V compensation memory," is used to raise the corresponding programming voltage.
In step S14, the monitored current is compared with a desired current that must flow through the data line. Then, a calibration data curve for the selected pixel is generated. And updating the delta V compensation memory according to the calibration data curve.
The calibration data curve of a pixel stored in the av compensation memory will be used to raise the programming voltage of the pixel in the next programming cycle when the pixel is in the normal operating mode.
In step S16, the identity of the selected pixel is sent to the end of the linked list. The selected pixel has the lowest alignment priority in the linked list.
During display operations (S6-S16), the linked list will provide a ranked priority list of pixels that must be calibrated. It should be noted that in the description, the use of the term "linked list" and the term "priority list" are interchangeable.
The operation returns (S18) to S8. The next programming cycle begins. A new column in the display array is activated (selected) and a new "n" number of pixels in the newly activated column is selected from the top of the linked list. The av compensation memory is updated with the calibration data obtained for the newly selected pixel.
The number "n" of selected pixels is now described in detail. As described above, the number "n" is determined based on the display size and the expected instability of the characteristic curve of the device over time. Assume that the total number of pixels N is N =3 × m 1 ×m 2 Wherein m is 1 And m 2 Respectively the number of rows and columns in the display array.
The maximum rate of change of the characteristic curve shift is K (= Δ I/Δ t.i). Each programming cycle was taken to be t =1/f.m 2 . After calibration of the entire display, the maximum desired offset of the characteristic curve is Δ I/I = k.t.n/n < e, where e is the tolerance error. After this, calibration can be resumed and the error eliminated. It can be seen that n > K.t.N/e, or n > 3.K.m 1 E.f.e. For example, if K =1%/hr, m 1 =1024,f =60hz, and e =0.1%, then n > 0.14, which means that 5 programming cycles are required for one calibration. This can be achieved by a calibration unit that is run only once in 5 programming cycles. Each calibration unit is capable of performing a calibration of one pixel in one programming cycle. Suppose e =0.01%And n is more than 1.4. This means that two calibration units are needed to calibrate two pixels in each programming cycle. This means that the speed can be very lowThe calibration system is cost effective to implement.
Since the shift in the characteristic will slow over time, the frequency of calibration can be automatically reduced as the display ages. In addition, the pixels selected for calibration may be programmed with different currents depending on the display data. The only condition is that its programming current is greater than the reference current. Thus, one pixel can be calibrated at multiple brightness levels to achieve higher accuracy.
The linked list is described in detail below. In the linked list, pixels with high brightness are listed for calibration. The display data is used to determine pixels with high brightness for calibration. When the current is weak, the calibration is slow and often inaccurate. In addition, the maximum shift amount of the characteristic curve occurs at the pixel having a strong current. Thus, to improve the accuracy and speed of the calibration, the selection must use a specific threshold current I TH The stronger current is to program the pixels and store them in a linked list.
I TH Is variable and may be "0". For I TH =0, all pixels are listed in a linked list, and calibration is performed for all pixels regardless of the programming current.
The calibration scheduling techniques described above may be applied to any current programmed pixel, such as, but not limited to, a current mirror based pixel.
Fig. 2 shows an example of a system architecture for performing the calibration schedule of fig. 1. The system 30 of fig. 2 is provided for implementing a calibration scheduling algorithm for a display array 10 having a plurality of pixel circuits 12. The pixel circuit 12 is a current programmed pixel circuit such as, but not limited to, a current mirror based pixel. The pixel circuits 12 are arranged in rows and columns.
The pixel circuit 12 may include an OLED and a plurality of transistors (e.g., TFTs). The transistors may be fabricated using amorphous silicon, nanocrystalline/microcrystalline silicon, polycrystalline silicon, an organic semiconductor process (e.g., organic TFT), an NMOS/PMOS process, or a CMOS process (e.g., MOSFET). The display array 10 may be an AMOLED display array.
The pixel circuit 12 is operated by the gate lines 14 connected to the gate driver 20, the data lines 16 connected to the voltage data driver 28, and the power supply lines connected to the power supply 24. In fig. 2, two data lines, two gate lines, and two power supply lines are shown as an example. Obviously, more than two data lines, more than two gate lines and more than two power lines may be provided in the display array 10.
The system 30 includes a calibration scheduler, and a programming and calibration memory block 32 for controlling the display array 10, and a Δ V compensation memory 34 for storing Δ V compensation voltages (values). In each programming cycle, a column in the display array 10 is selected. Calibration scheduler and memory block 32 initiates a normal operating mode or calibration mode for the selected column (i.e., data line) in the programming cycle.
The system 30 also includes a monitoring system for monitoring and measuring the pixel current. The monitoring system includes switches 36 and 38, and a voltage sensor 40 with a precision resistor 42. In fig. 2, for example, switches 36 and 38 are provided for each data line.
The system 30 also includes a generator that generates a av compensation voltage based on the monitoring results. The generator includes an analog/digital converter (a/D) 44, a comparator 46, and a transformer 48. The a/D44 converts the analog output of the voltage sensor 40 to a digital output. The comparator 46 compares the digital output with the output of the inverter 48. The transformer 48 implements the function f (V) on the digital data input 52. The converter 48 converts the current data input 52 to a voltage data input via f (V). The comparison result of the comparator 46 is stored in the Δ V compensation memory 34.
The system 30 also includes an adder 50 for adding the digital data input 52 and the av compensation voltage stored in the av compensation memory 34. The voltage data driver 28 drives the data lines based on the output of the adder 50. The programmed data of the data line is adjusted by adding the av compensation voltage.
Switch 36 is activated when the calibration scheduler and memory block 32 initiates the normal operating mode for the selected data line. The voltage output of the voltage data driver 28 is applied directly to the pixels on that data line.
When the calibration scheduler and memory block 32 initiates the calibration mode for that data line, the switch 38 is activated. A voltage is applied to the pixels on the data line through precision resistors 42. At the final stage of the programming time (i.e., when the initial transient ends), the voltage drop across resistor 42 is measured by voltage sensor 40. The a/D44 converts the voltage drop monitored by the voltage sensor 40 into digital data. If the pixel is a current programmed pixel circuit, the resulting voltage drop has a value proportional to the current flowing through the pixel. The comparator 46 compares this value with the desired value obtained by the converter 48.
The difference between the expected value and the measured value is stored in the av compensation memory 34 and will be used for the subsequent programming cycle. The difference will be used to adjust the data voltage used to program the pixel in the future.
The calibration scheduler and memory block 32 may comprise the linked list described above. Initially, a linked list is automatically generated. The linked list may be simply a list of pixels. However, modifications may be made during operation.
The calibration of the pixel circuit with high brightness can ensure high-speed and accurate calibration required in a large or small-area display.
Since the display array 10 is driven using voltage programming techniques, it can be fast and can be used for high resolution and large area displays.
Due to speed, accuracy and ease of implementation, the calibration scheduling techniques have applications ranging from electroluminescent devices for cell phones, personal organizers, monitors, televisions, to large area display panels.
The system 30 monitors and measures the voltage drop depending on the time-varying parameters of the pixels and generates the required programming data. However, the time-varying parameters of the pixels may be extracted by any other mechanism than the mechanism in fig. 2.
Another technique for programming, extracting time-varying parameters of, and driving pixels is described in detail with reference to fig. 3-7. The technique includes voltage extraction for calibration. The programming data is calibrated using the extracted information to produce a pixel current that is stable over time. Using this technique, the aging of the pixel is extracted.
FIG. 3 illustrates a system architecture for performing voltage extraction, programming and driving according to one embodiment of the invention. The system of fig. 3 performs voltage extraction and programming for the current mode pixel circuit 60. The pixel circuit 60 includes a light emitting device and a plurality of transistors with driving transistors (not shown). The transistor may be a TFT.
The pixel circuit 60 is selected by a selection line SEL and driven by DATA on a DATA line 61. A voltage source 62 is provided to apply a programming voltage V P Written into the pixel circuit 60. A current-controlled voltage source (CCVS) 63 having a positive node and a negative node is provided to convert the current on the data line 61 to a voltage Vext. A display controller and scheduler 64 operates the pixel circuits 60. The display controller and scheduler 64 monitors the extraction voltage Vext output from CCVS63 and then controls the voltage source 62.
The resistance of CCVS63 is negligible. The current on data line 61 can thus be written as:
I Line ＝I piexl ＝β(V P -V T ) 2 ...(1)
in which I Line Representing the current, I, on the data line 61 piexl Representing pixel current, V T Represents the threshold voltage of the driving transistor included in the pixel circuit 60, and β represents the gain parameter of the TFT characteristic.
As the threshold voltage of the drive TFT increases with time, the current on the data line 61 decreases. By monitoring the extraction voltage Vext, the display controller and scheduler 64 determines the offset of the threshold voltage.
The threshold voltage V of the drive transistor can be calculated as follows T ：
V T ＝V P -(I Line /β) 0.5 ...(2)
Modifying a programming voltage V using extracted information P . The extraction procedure may be performed for one or a few pixels in each frame time.
Fig. 4 shows one example of the system for voltage extraction, programming and driving of fig. 3, which employs a pixel circuit 70 of a top-emitting current cell. The pixel circuit 70 includes an OLED 71, a storage capacitor 72, a driving transistor 73, and switching transistors 74 and 75.
The transistors 73, 74, and 75 may be n-type TFTs. However, these transistors 73, 74, and 75 may also be p-type transistors. The voltage extraction and programming techniques applied to the pixel circuit 70 are equally applicable to pixel circuits with p-type transistors.
The driving transistor 73 is connected to the data line 76 through a switching transistor 75, to the OLED 71, and to the storage capacitor 72 through a switching transistor 74. The gate terminal of the driving transistor 73 is connected to the storage capacitor 72. The gate terminals of the switching transistors 74 and 75 are connected to a selection line SEL. The OLED 71 is connected to a voltage supply electrode or a VDD line. The pixel circuit 70 is selected by a select line SEL and driven by DATA on a DATA line 76.
A Current Conveyor (CC) 77 has X, Y and Z terminals and is used to draw current on the data line 76 without increasing its load. A voltage source 78 applies a program voltage to the Y terminal of CC 77. In CC 77, the X terminal is made to have the same voltage as the Y terminal by feedback. At the same time, the current on the X terminal of CC 77 is copied to the Z terminal. The Current Controlled Voltage Source (CCVS) 79 has a positive node and a negative node. CCVS 79 converts the current on the Z terminal of CC 77 to a voltage Vext.
Vext is provided to the display controller and scheduler 64 of fig. 3, where the threshold voltage of the drive transistor 73 is extracted. The display controller and scheduler 64 controls the voltage source 78 based on the extracted threshold voltage.
Fig. 5 illustrates another embodiment of the system for voltage extraction, programming and driving of fig. 3, employing a pixel circuit 80 of a bottom emitting current cell. The pixel circuit 80 includes an OLED 81, a storage capacitor 82, a driving transistor 83, and switching transistors 84 and 85. The transistors 83, 84, and 85 may be n-type TFTs. However, these transistors 83, 84, and 85 may also be p-type transistors.
The driving transistor 83 is connected to the data line 86 through the switching transistor 85, to the OLED 81, and to the storage capacitor 82. The gate terminal of the driving transistor 83 is connected to the voltage supply line VDD through the switching transistor 84. The gates of the switching transistors 84 and 85 are connected to a selection line SEL. The pixel circuit 80 is selected by a select line SEL and driven by DATA on a DATA line 86.
A Current Conveyor (CC) 87 has X, Y and Z terminals for extracting the current on the data line 86 without increasing its load. The voltage source 88 applies a negative programming voltage to the Y terminal of the CC 87. In CC 87, the X terminal is made to have the same voltage as the Y terminal by feedback. At the same time, the current on the X terminal of CC 87 is copied to the Z terminal. The Current Controlled Voltage Source (CCVS) 89 has a positive node and a negative node. CCVS 89 converts the current on the Z terminal of CC 87 to a voltage Vext.
Vext is provided to the display controller and scheduler 64 of fig. 3, where the threshold voltage of the drive transistor 83 is extracted. The display controller and scheduler 64 controls the voltage source 88 based on the extracted threshold voltage.
Fig. 6 illustrates another embodiment of the system for voltage extraction, programming and driving of fig. 3, employing a top-emitting current mirror pixel circuit 90. The pixel circuit 90 includes an OLED 91, a storage capacitor 92, mirror transistors 93 and 94, and switching transistors 95 and 96. The transistors 93, 94, 95, and 96 may be n-type TFTs. However, these transistors 93, 94, 95, and 96 may also be p-type transistors.
The mirror transistor 93 is connected to the data line 97 through a switching transistor 95 and to the storage capacitor 92 through a switching transistor 96. The mirror transistors 93 and 94 have gate terminals connected to the storage capacitor 92 and the switching transistor 96. The mirror transistor 94 is connected to the voltage supply electrode or VDD line through the OLED 91. The gates of the switching transistors 85 and 86 are connected to a select SEL line. The pixel circuit 90 is selected by a selection line SEL and driven by DATA on a DATA line 97.
A Current Conveyor (CC) 98 has X, Y and Z terminals and is used to extract the current of the data line 97 without increasing its load. Voltage source 99 applies a positive programming voltage to the Y terminal of CC 98. In CC 98, the X terminal is made to have the same voltage as the Y terminal by feedback. At the same time, the current on the X terminal of CC 98 is copied to the Z terminal. A current-controlled voltage source (CCVS) 100 has a positive node and a negative node. CCVS 100 converts the current on the Z terminal of CC 98 to a voltage Vext.
Vext is provided to the display controller and scheduler 64 of fig. 3, where the threshold voltage of the drive transistor 93 is extracted. The display controller and scheduler 64 controls the voltage source 99 based on the extracted threshold voltage.
Fig. 7 illustrates another embodiment of the system for voltage extraction, programming and driving of fig. 3 employing a bottom emission current mirror pixel circuit 110. The pixel circuit 110 includes an OLED 111, a storage capacitor 112, mirror transistors 113 and 116, and switching transistors 114 and 115. The transistors 113, 114, 115, and 116 may be n-type TFTs. However, these transistors 113, 114, 115, and 116 may also be p-type transistors.
The mirror transistor 113 is connected to the data line 117 via the switching transistor 114 and to the storage capacitor 112 via the switching transistor 115. The gate terminals of the mirror transistors 113 and 116 are connected to the storage capacitor 112 and the switching transistor 115. The mirror transistor 116 is connected to the voltage supply line VDD. Mirror transistors 113, 116 and a storage capacitor 112 are connected to the OLED 111. The gate terminals of the switching transistors 114 and 115 are connected to a selection line SEL. The pixel circuit 110 is selected by a selection line SEL and driven by DATA on the DATA line 117.
A Current Conveyor (CC) 118 has X, Y and Z terminals and is used to draw current on the data line 117 without increasing its load. Voltage source 119 applies a positive programming voltage to the Y terminal of CC 118. In the CC 118, the X terminal of the CC 118 has the same voltage as the Y terminal by feedback. At the same time, the current on the X terminal of CC 118 is copied to the Z terminal. The current-controlled voltage source (CCVS) 120 has a positive node and a negative node. CCVS 120 converts the current on the Z terminal of CC 118 to a voltage Vext.
Vext is provided to the display controller and scheduler 64 of fig. 3, where the threshold voltage of the drive transistor 113 is extracted. The display controller and scheduler 64 controls the voltage source 119 based on the extracted threshold voltage.
Referring to fig. 3-7, a voltage extraction technique may be utilized to extract a time-varying parameter (e.g., threshold offset) of a pixel. Thus, the extracted information can be used to calibrate the programming voltage, resulting in a pixel current that is stable over time. Since the voltage of the OLED (e.g., 71 of fig. 4, 81 of fig. 5, 91 of fig. 6, 111 of fig. 7) directly affects the current, the voltage extraction driving technique described above can also be used to extract OLED aging and threshold shift.
The voltage extraction techniques described above may be used for any current mode pixel circuit, including current mirror and current cell pixel circuit configurations, and may be applied to the display array 10 of FIG. 2. With the extracted information, a stable current which is not related to the aging of the pixel under a long-time display operation can be provided. Thus, the life of the display operation can be effectively improved.
It should be noted that the transistors in the pixel circuits of fig. 3-7 may be fabricated using amorphous silicon, nanocrystalline/microcrystalline silicon, polycrystalline silicon, an organic semiconductor process (e.g., organic TFT), an NMOS/PMOS process, or a CMOS process (e.g., MOSFET). The pixel circuits of fig. 3-7 may constitute an AMOLED display array.
Another technique for programming, extracting time-varying parameters of, and driving pixels is described in detail with reference to fig. 8-17. This technique includes a step calibration drive technique. In this step calibration driving technique, information about pixel aging (e.g., threshold offset) is extracted. The extracted information will be used to generate a stable pixel current/brightness. The resolution of the extracted aging case is defined by the display driver, despite the use of the one-bit extraction technique. Also, since the pixels are extracted under the operating condition, the dynamic effect can be compensated, which is similar to the driving period.
Fig. 8 shows a pixel circuit 160 to which a step calibration drive according to an embodiment of the invention is applied. The pixel circuit 160 includes an OLED 161, a storage capacitor 162, and a driving transistor 163, and switching transistors 164 and 165. The pixel circuit 160 is a current programmed 3-TFT pixel circuit. The plurality of pixel circuits 160 may constitute an AMOLED display.
Transistors 163, 164, and 165 are n-type TFTs. However, transistors 163, 164, and 165 may also be p-type transistors. The step calibration driving technique applied to the pixel circuit 160 is also applicable to a pixel circuit with p-type transistors. Transistors 163, 164, and 165 may be fabricated using amorphous silicon, nanocrystalline/microcrystalline silicon, polycrystalline silicon, an organic semiconductor process (e.g., organic TFT), an NMOS/PMOS process, or a CMOS process (e.g., MOSFET).
The gate terminal of the driving transistor 163 is connected to the signal line VDATA through the switching transistor 164 and is also connected to the storage capacitor 162. The source terminal of the drive transistor 163 is connected to a common ground. The drain terminal of the driving transistor 163 is connected to the MONITOR line MONITOR through the switching transistor 165, and also connected to the cathode electrode of the OLED 161.
The gate terminal of the switching transistor 164 is connected to the select line SEL1. The source terminal of the switching transistor 164 is connected to the gate terminal of the driving transistor 163 and to the storage capacitor 162. The drain terminal of switch transistor 164 is connected to VDATA.
The gate terminal of switch transistor 165 is connected to select line SEL2. The source terminal of the switching transistor 165 is connected to MONITOR. The drain terminal of the switching transistor 165 is connected to the drain terminal of the driving transistor 163 and the cathode electrode of the OLED 161. The anode electrode of the OLED 161 is connected to a voltage supply electrode or a VDD line.
Transistors 163 and 164 and storage capacitor 162 are connected at node A3. Transistors 163 and 165 and OLED 161 are connected at node B3.
Fig. 9 shows one example of a driver and extraction module 170 and the driving transistor 163 of fig. 8. In fig. 9, rs171a and Rs171b represent the ON resistance of the switching transistors (e.g., 164, 165 of fig. 8), respectively. Cs represents a storage capacitor of the pixel, C OLED Representing the OLED capacitance, CP represents the line parasitic capacitance. In fig. 9, the OLED is represented as a capacitor.
The threshold voltage of the driving transistor is extracted in an extraction period using the module 173. The module 173 may be a current Sense Amplifier (SA) or a current comparator. In the description, the module 173 is referred to as an "SA module 173".
If the current on the MONITOR line is higher than the reference current (IREF), the output of the SA module 173 (i.e., the flip-flop in fig. 10, 11) becomes 1. If the current on the MONITOR line is less than the reference current (IREF), the output of the SA module 173 goes to 0.
It should be noted that the SA blocks 173 may be shared between several columns, thereby reducing overhead. Furthermore, the calibration of the pixel currents can also be performed one at a time, so the extraction circuit can be shared between all columns.
A Data Processing Unit (DPU) module 172 is provided to control the programming cycle, contrast and brightness, to perform the calibration procedure and to control the drive cycle. The DPU module 172 executes an extraction algorithm to extract (estimate) the threshold voltage of the driving transistor based on the output value of the SA module 173 and controls the driver 174 connected to the driving transistor 163.
Fig. 10 shows an example of an extraction algorithm performed by the DPU module 172 of fig. 9. The algorithm of fig. 10 is part of the DPU module 172. In FIG. 10, V T (i, j) represents the threshold voltage extracted for the pixel (i, j) in the previous extraction cycle, V S Representing the resolution of the driver 174, "i" represents a row of the pixel array and "j" represents a column of the pixel array. The flip-flop transfers the comparison result of the SA module 173 of fig. 9. Less than state 180 determines the actual V of the pixel T Less than predicted V T (V TM ) Equal to the case where state 181 determines the prediction V of the pixel T (V TM ) And the actual V T Equal, greater than state 182 determines the actual V of the pixel T Greater than predicted V T (V TM ) The case (1).
DPU module 172 of FIG. 9 determines an intermediate threshold voltage V TM The following:
(A1) When s (i, j) = less than state (180), the actual threshold voltage is less than V T (i, j), mixing V TM Is set as (V) T (i，j)-V S )。
(A2) When s (i, j) = equals to state (181), the actual threshold voltage equals to V T (i, j) byV TM Is set to V T (i，j)。
(A3) When s (i, j) = greater than state (182), the actual threshold voltage is greater than V T (i, j), mixing V TM Is set to (V) T (i，j)+V S )。
Where s (i, j) represents the previous state of pixel (i, j) stored in the calibration memory (e.g., 208 of FIG. 16).
Fig. 11 illustrates another embodiment of an extraction algorithm performed by the DPU module 172 of fig. 9. The algorithm of fig. 11 is part of the DPU module 172 of fig. 9. In FIG. 11V T (i, j) represents the threshold voltage, V, of the pixel (i, j) extracted in the previous extraction cycle S Representing the resolution of the driver 174, "i" represents a row of the pixel array and "j" represents a column of the pixel array. Flip-flop passing ratio of SA module 173And (6) comparing the results.
In fig. 11, vres represents an actual V for obtaining a pixel T Will predict V T (V TM ) The step size is added/subtracted, a represents the gain of decrease of the predicted step size, and K represents the gain of increase of the predicted step size.
The operation of fig. 11 is the same as that of fig. 10, except that it has additional states L2 and G2 added for rapid extraction of mutations. In the gain state, the step size is increased to keep up with the change more quickly. L1 and G1 are the definitions V T Whether it is a mutated or a normally altered state of transformation.
Fig. 12 shows an example of a waveform applied to the pixel 160 of fig. 8. In FIG. 12, V Call ＝V B +V TM ，V DR ＝V P +V T (i，j)+V REF In which V is B Representing the bias voltage, V, in the extraction cycle TM Is defined based on the algorithm shown in FIG. 10 or 11, V P Representing the programming voltage, V T (i, j) represents the threshold voltage extracted in the previous extraction cycle, V REF Representing the source voltage of the drive transistor in the programming cycle.
Referring to fig. 8-12, the operation of the pixel circuit 160 includes operation periods X51, X52, X53, and X54. In fig. 12, the fetch cycle is separated from the program cycle. The fetch cycle includes X51 and 52X, and the program cycle includes X53. X54 is the drive period. At the end of the programming cycle, node A3 is charged to (V) P +V T ) In which V is P Is the programming voltage, V T Is the threshold voltage of the driving transistor 163.
In the first operation period X51: SEL1 and SEL2 are at high level. Charging node A3 to V cal Charging node B3 to V REF 。V cal Is a V B +V TM In which V is B For bias, V TM Is predicted V T And V is REF Should be greater than V DD -V OLED0 In which V is OLED0 Is the ON voltage of the OLED 161.
In the second operation period X52: SEL1 becomes zero. The gate-source voltage of the driving transistor 163 is given by:
VGS＝V B +V TM +ΔV B +ΔV TM -ΔV T2 -ΔV H
where VGS represents the gate-source voltage of the drive transistor 163, Δ V B 、ΔV TM 、ΔV T2 And Δ V H Are each dependent on V B 、V TM 、V T2 And V H The dynamic effect of (2). V T2 Representing the threshold voltage, V, of the switching transistor 164 H Representing the change in voltage of SEL1 at the beginning of the second operating period when X52 becomes zero.
The SA module 173 is tuned to detect a value greater than β (V) B ) 2 So that the gate-source voltage of the driving transistor 163 is greater than (V) B +V T ) Where β is the gain parameter in the I-V characteristic of the drive transistor 163.
Thus, after several iterations, V TM And an extraction threshold voltage V of the pixel (i, j) T (i, j) converge to:
V TM ＝V T -γ-(V B +V T +V T2 -V H )
Figure A20058004802000241
wherein C g2 Representing the gate capacitance of the switching transistor 164.
In the third operation period X53: SEL1 is at a high level. VDATA to V DR . Node A3 is charged to [ V ] P +V T (i，j)-γ(V P -V B )]。
In the fourth operation period X54: SEL1 and SEL2 become zero. In view of dynamic effects, the gate-source voltage of the driving transistor 163 can be written as:
VGS＝V P +V T
thus, the pixel current becomes independent of the static and dynamic effects of the threshold voltage shift.
In fig. 12, the fetch cycle and the program cycle are shown as separate cycles. However, the fetch cycle and the program cycle may also be combined, as shown in fig. 13. Fig. 13 shows another example of waveforms applied to the pixel circuit 160 of fig. 8.
Referring to fig. 8 to 11 and 13, the operation of the pixel circuit 160 includes operation periods X61, X62, and X63. The programming and extraction cycles are merged into operation cycles X61 and X62. The operation period X63 is a driving period.
In the programming cycle, the pixel current is compared to the required current and the algorithm of fig. 10 or 11 is used to extract the threshold voltage of the drive transistor. By V in the operating cycle X61 DR ＝ V P +V T (i，j)+V REF The pixel circuit 160 is programmed. The pixel current is then monitored by the MONITOR line and compared to the required current. Based on the comparison result, useThe extraction algorithm of fig. 10 or 11 to update the threshold voltage V T (i，j)。
Two select lines SEL1 and SEL2 are shown in fig. 8. However, the switching transistors 164 and 165 may be operated using a signal selection line (e.g., SEL 1) as a common selection line. When the common selection line is used, SEL1 in fig. 12 is kept at the high level in the second operation period X52, and VGS is kept at (V) B +V TM ). Thus, no dynamic effects are detected.
The step alignment driving technique described above can be applied to the pixel circuit 190 of fig. 14. The pixel circuit 190 includes an OLED 191, a storage capacitor 192 and a driving transistor 193, and switching transistors 194 and 195. Pixel circuit 190 is a current programmed 3-TFT pixel circuit. The plurality of pixel circuits 190 may constitute an AMOLED display.
Transistors 193, 194, and 195 are n-type TFTs. However, the transistors 193, 194, and 195 may also be p-type transistors. The step calibration driving technique applied to the pixel circuit 190 may also be applied to a pixel circuit with p-type transistors. Transistors 193, 194, and 195 can be fabricated using amorphous silicon, nanocrystalline/microcrystalline silicon, polycrystalline silicon, an organic semiconductor process (e.g., organic TFT), an NMOS/PMOS process, or a CMOS process (e.g., MOSFET).
The gate terminal of the driving transistor 193 is connected to the signal line VDATA through the switching transistor 194 and also connected to the storage capacitor 192. The source terminal of the driving transistor 193 is connected to the anode electrode of the OLED 191, and is connected to the MONITOR line MONITOR through the switching transistor 195. The drain terminal of the drive transistor 193 is connected to the voltage supply line VDD. The gate segments of transistors 194 and 195 are connected to select lines SEL1 and SEL2, respectively.
Transistors 193 and 194 and storage capacitor 192 are connected at node A4. The transistor 195, the OLED 191 and the storage capacitor 192 are connected at node B4.
The structure of the pixel circuit 190 is similar to that shown in fig. 8 except that the OLED 191 is located at the source terminal of the driving transistor 193. The operation of the pixel circuit 190 is the same as that shown in fig. 12 or 13.
Since the source terminal of the driving TFT193 is made VREF in the extraction period (X51 and X52 or X62), the extracted data is not related to ground bounce. Further, in the programming cycle (X53 or X61), the source terminal of the driving TFT is made V REF The gate-source voltage of the driving TFT becomes independent of the ground bounce. Because of these conditions, the pixel current is independent of ground bounce.
Fig. 15 shows the simulation results of the step calibration driving technique. In fig. 15, "case I" represents an operation in the case where SEL1 in fig. 8 becomes zero in the second operation period (X52 in fig. 12); "case II" represents an operation in the case where SEL1 in fig. 8 is held at the high level in the second operation period.
In FIG. 15,. DELTA.V TR Is the minimum detectable shift, Δ V, in the threshold voltage of the drive transistor (e.g., 163 of FIG. 8) T2R Is the minimum shift detectable in the threshold voltage of the switching transistor (e.g., 164 of FIG. 8)And I is PL Is the pixel current of the pixel during the drive period.
Due to the dynamic effect of threshold voltage shift, the pixel current of case II is less than the pixel current of case I for a given programming voltage. Further, the pixel current of case II increases (a) when the threshold voltage of the driving transistor increases, and decreases (b) when the threshold voltage of the switching transistor decreases. However, the pixel current of case I is stable. The maximum error induced in the pixel current is less than 0.5% of any shift in the threshold voltage of the drive and switching TFTs. Apparently because of V on the pixel current T The influence of the offset is dominant, so Δ V T2R Greater than Δ V TR . These two parameters are determined by the resolution (V) of the driver (e.g., 174 of FIG. 9) s ) And SNR control of the SA module (e.g., 193 of fig. 9). Since less than Δ V cannot be detected TR And the time constant of the threshold shift is large, it is possible to perform the extraction period (e.g., X51 and X52 of fig. 12) after a long time interval consisting of several frames, which results in lower power consumption. Meanwhile, the main operation period becomes the other program period (e.g., X53 of fig. 12) and the driving period (e.g., X54 of fig. 12). Therefore, the programming time can be significantly reduced, providing a high resolution, high speed programming prerequisite large area AMOLED display.
Fig. 16 shows an example of a system configuration for step calibration driving of the display array 200. The display array 200 includes a plurality of pixel circuits (e.g., 160 in fig. 8 or 190 in fig. 14).
The display array 200 is provided with a gate driver 202 for selecting pixel circuits, a driver/SA module 204, and a data processing and calibration unit module 206. The driver/SA module 204 includes the driver 174 and the SA module 173 in fig. 9. The data processing and calibration unit module 206 includes the DPU module 172 of fig. 9. The "calibration" in fig. 16 includes calibration data from the calibration memory 208 and may include certain user-defined constants for setting the calibration data processing. The user uses the contrast and brightness inputs to adjust the contrast and brightness of the panel. In addition, gamma correction data is defined based on the OLED characteristic curve and the human eye. The gamma correction input is used to adjust the pixel brightness for the human eye.
The calibration memory 208 stores the extraction threshold voltage V of each pixel T (i, j) and state s (i,j) In that respect The memory 210 stores other required data for normal operation of the display, including gamma correction, resolution, contrast, etc. The DPU module performs the normal tasks assigned to the controller and the scheduler in the display. In addition, the algorithm of fig. 10 or 11 is added to perform calibration.
Fig. 17 shows an example of waveforms applied to the system configuration of fig. 16. In FIG. 17, ROW [1], ROW [2], ROW [3] each represent a ROW in the display array 200, "E" represents a fetch operation, "P" represents a program operation, and "D" represents a drive operation. It should be noted that the extraction period (E) is not required for all frame periods. Therefore, the extraction of the pixels is repeated after a long time interval (extraction interval).
As shown in fig. 17, the extraction process occurs only once in a frame time. Further, VT extraction of pixel circuits on the same row is performed simultaneously.
Thus, the maximum time required to update a frame is:
τ F ＝nτ P +τ E
wherein tau is F Represents the frame time, τ P Represents the time, τ, required to write the pixel data into the storage capacitor (e.g., 162 of FIG. 8) E Representing the extraction time, and n represents the number of rows in the display array (e.g., 200 of fig. 16).
Let τ be E ＝m·τ P Frame time τ F Can be written as:
τ F ＝(n+m)·τ P
where m represents the time (τ) in the programming cycle F ) The time required for the extraction cycle in the scale.
For example, for a Quarter Video Graphics Array (QVGA) display (240 × 320) with a frame rate of 60Hz, if m =10, the programming time per line is 66 μ s and the extraction time is 0.66ms.
Note that the step-by-step calibration driving technique described above can be applied to any current-programmed pixel circuit other than those shown in fig. 8 and 14.
With the step calibration drive technique, time-varying parameters of the pixels, such as threshold offset, are extracted. The extracted information is then used to calibrate the programming voltage, resulting in a pixel current that is stable over time. Also, a stable current which is not related to pixel aging under a long-time display operation can be supplied to the pixel circuit, which effectively improves the life of the display operation.
Techniques for programming, extracting time-varying parameters of, and driving pixels according to another embodiment of the invention are described in detail below. The technique involves extracting information about the aging of the pixel (e.g., OLED brightness) by monitoring the OLED voltage or OLED current and generating the brightness. The extracted information is used to calibrate the programming voltage, resulting in a luminance that is stable over time.
Since the OLED voltage/current is known to be related to luminance degradation of the OLED (e.g., 161 of fig. 8, 191 of fig. 14), the programming voltage can be varied by the OLED voltage/current to provide a constant luminance.
For example, in the driving period, when SEL2 is at a high level, the voltage/current of the OLED (161 of fig. 8, 191 of fig. 14) is extracted. Since the OLED voltage or current is known to be related to the luminance degradation of the OLED, the programming voltage can be modified by the OLED voltage to provide a constant luminance.
Fig. 18 shows an example of a waveform for voltage/current extraction. The waveforms of fig. 18 may be applied to the pixel circuit 160 of fig. 8 and the pixel circuit 190 of fig. 14 to extract the OLED voltage/current. The operation of fig. 18 includes operation cycles X71, X72, and X73. The operation periods X71 and X72 are OLED extraction periods. The operation period X73 is one of the operation periods shown in fig. 12 and 13.
In the first operation period X71, SEL1 and SEL2 are at a high level, VDATA is zero. The gate-source voltage of the driving transistor (e.g., 163 of fig. 8) becomes zero. A current or voltage is applied to the OLED through the MONITOR line (161 of fig. 8).
In the second operation period X72, SEL2 is at a high level, and SEL1 is at a low level. The OLED voltage or current is extracted through the MONITOR line using the algorithm shown in fig. 10 or 11. This waveform may be combined with any other drive waveform.
In the above description, the algorithm in fig. 10 and 11 is used to predict the aging data, i.e., V, based on the comparison result (current to current or voltage to voltage) T And (4) offsetting. However, by using V OLED To replace V T And the comparison of the OLED current/voltage with the reference current/voltage, the algorithms of FIGS. 10 and 11 can be applied to predict the OLED voltage V OLED Of (3) is detected. In the above description, the system configuration shown in fig. 9 is used to compensate for the threshold shift. However, it should be understood that when the structure shown in fig. 9, i.e., the DPU172, the module 173, the driver 174, etc., is used, OLED data is also extracted. This data can be used to compensate for OLED shift.
The operation period X73 may be any operation period including a program period. Depending on the panel state after OLED extraction. If it is in the process of operation, X73 is the programming cycle of the waveforms in FIGS. 12 and 13. The OLED voltage can be extracted in the drive periods X55/X63 of FIGS. 12/13. In the driving period X55/X63, SEL2 in fig. 8 or 14 becomes a high voltage, and thus the voltage of the OLED of a specific pixel current can be read back by MONITOR.
Fig. 19 shows another example of waveforms for voltage/current extraction. Fig. 20 shows a pixel circuit 220 that applies the voltage/current extraction of fig. 19.
Referring to fig. 20, the pixel circuit 220 includes an OLED 221, a storage capacitor 222, and a driving transistor 223 and switching transistors 224 and 225. The plurality of pixel circuits 220 may constitute an AMOLED display.
The transistors 223, 224, 225 are n-type TFTs, however the transistors 223, 224, 225 may also be p-type TFTs. The voltage/current extraction techniques applied to the pixel circuit 220 may also be applied to pixel circuits having p-type transistors. The transistors 223, 224, 225 may be fabricated using amorphous silicon, nanocrystalline/microcrystalline silicon, polycrystalline silicon, an organic semiconductor process (e.g., organic TFT), an NMOS/PMOS process, or a CMOS process (e.g., MOSFET).
The gate terminal of the driving transistor 223 is connected to the source terminal of the switching transistor 224 and also to the storage capacitor 222. One terminal of the driving transistor 223 is connected to the common ground. The other end of the driving transistor 223 is connected to a MONITOR and DATA line MONITOR/DATA through a switching transistor 235 and also connected to a cathode electrode of the OLED 221.
The gate terminal of the switching transistor 224 is connected to the select line SEL1. One terminal of the switching transistor 224 is connected to the gate terminal of the driving transistor 223 and to the storage capacitor 222. The other end of the switching transistor 224 is connected to a cathode electrode of the OLED 221.
The gate terminal of the switching transistor 225 is connected to the selection line SEL2. One terminal of the switching transistor 225 is connected to MONITOR/DATA. The other end of the switching transistor 225 is connected to the driving transistor 223 and the cathode electrode of the OLED 221. The anode electrode of the OLED 221 is connected to a voltage supply electrode or a VDD line.
Transistors 223, 224 and storage capacitor 222 are connected at node A5. The transistors 223, 225 and the OLED 221 are connected at node B5.
The pixel circuit 220 is similar to the pixel circuit 160 of fig. 8. However, in the pixel circuit 220, the MONITOR/DATA line is used for monitoring and programming.
Referring to fig. 19 to 20, the operation of the pixel circuit 220 includes operation periods X81, X82, and X83.
In the first operation period X81, SEL1 and SEL2 are at a high level, MONITOR/DATA is zero. The gate-source voltage of the driving transistor (223 in fig. 2) becomes zero.
In the second operation period X82, a current or voltage is applied to the OLED through the MONITOR/DATA line, and the voltage or current thereof is extracted. As described above, the offset of the OLED voltage is extracted based on the monitored voltage or current using the algorithm shown in fig. 10 or 11. This waveform can be combined with any drive waveform.
The operation cycle X83 may be any operation cycle including a program cycle. Depending on the panel state after OLED extraction.
The OLED voltage/current may be extracted in the drive period of the pixel circuit 220 of fig. 20 after the pixel circuit is programmed to a constant current using any drive technique. In the drive period, SEL2 goes high, so the voltage of the OLED can be read back through the mono or/DATA line for a particular pixel current.
Fig. 21 shows another example of waveforms of the voltage/current extraction technique. Fig. 22 shows a pixel circuit 230 to which the voltage/current extraction of fig. 21 can be applied. The waveforms of fig. 21 are equally applicable to the pixel circuit 160 of fig. 8 to extract the OLED voltage/current.
Referring to fig. 22, the pixel circuit 230 includes an OLED 231, a storage capacitor 232, and a driving transistor 233, and switching transistors 234 and 235. The plurality of pixel circuits 230 may constitute an AMOLED display.
The transistors 233, 234, 235 are n-type TFTs, however the transistors 233, 234, 235 may also be p-type TFTs. The voltage/current extraction techniques applied to the pixel circuit 230 may also be applied to pixel circuits having p-type transistors. Transistors 233, 234, 235 may be fabricated using amorphous silicon, nanocrystalline/microcrystalline silicon, polycrystalline silicon, an organic semiconductor process (e.g., organic TFT), an NMOS/PMOS process, or a CMOS process (e.g., MOSFET).
The gate terminal of the driving transistor 233 is connected to the source terminal of the switching transistor 234 and also to the storage capacitor 232. One terminal of the driving transistor 233 is connected to the voltage supply line VDD. The other end of the driving transistor 233 is connected to a MONITOR and DATA line MONITOR/DATA through a switching transistor 235 and also connected to an anode electrode of the OLED 231.
The gate terminal of the switching transistor 234 is connected to the select line SEL1. One terminal of the switching transistor 234 is connected to the gate terminal of the driving transistor 233 and to the storage capacitor 232. The other terminal of the switching transistor 234 is connected to VDD.
The gate terminal of the switching transistor 225 is connected to the selection line SEL2. The other terminal of the switching transistor 235 is connected to MONITOR/DATA. The other end of the switching transistor 235 is connected to the driving transistor 233 and the anode electrode of the OLED 231. The anode electrode of the OLED 231 is connected to VDD.
Transistors 233, 234 and storage capacitor 232 are connected at node A6. The transistors 233, 235 and the OLED 231 are connected at node B5.
The pixel circuit 230 is similar to the pixel circuit 190 of fig. 14. However, in the pixel circuit 230, the MONITOR/DATA line is used for monitoring and programming.
Referring to fig. 21-22, the operation of fig. 22 includes operation cycles X91, X92, and X93.
In the first operation period X91, SEL1 and SEL2 are at the high level, and VDD becomes zero. The gate-source voltage of the driving transistor (e.g., 233 of fig. 21) becomes zero.
In the second operation period X92, a current (voltage) is applied to the OLED (e.g., 231 of fig. 21) through the MONITOR/DATA line, and the voltage (current) thereof is extracted. As described above, the offset of the OLED voltage is extracted based on the monitored voltage or current using the algorithm shown in fig. 10 or 11. This waveform can be combined with any drive waveform.
The operation period X93 may be any operation period including a program period. Depending on the panel state after OLED extraction.
The OLED voltage may be extracted in a drive period of the pixel circuit 230 of fig. 21 after the pixel circuit is programmed to a constant current using any drive technique. In the drive cycle, SEL2 goes high, so the voltage of the OLED can be read back over the mono or/DATA line for a particular pixel current.
It is known that the OLED characteristic curve improves under negative bias stress. Thus, a negative bias, extracted from the OLED voltage/current, relating to the stress change history of the pixel may be applied to the OLED during times when the display is not in operation. Any of the pixel circuits presented herein can use this approach.
Using the OLED voltage/current extraction technique, the pixel circuit can provide stable luminance regardless of pixel aging under long-time display operation to effectively improve the life span of the display operation.
A technique for reducing unnecessary light emission in a display array having light emitting devices according to one embodiment of the present invention is described in detail below. The technique includes removing the OLED from the programming path during a programming cycle. This technique can be employed in a hybrid drive technique to extract information about the exact aging of the pixel, e.g. the actual threshold voltage shift/mismatch of the drive transistors. The light emitting device is turned off during the programming/calibration period to prevent unnecessary light emission and to prevent pixel aging related effects of the light emitting device. The technique is applicable to any current mirror pixel circuit fabricated using any process including polysilicon, amorphous silicon, crystalline silicon, and organic materials.
Fig. 23 shows a mirror-based pixel circuit 250 that applies the technique of removing OLEDs from the programming path during a programming cycle. The pixel circuit 250 includes an OLED 251, a storage capacitor 252, and a programming transistor 253, a driving transistor 254, and switching transistors 255 and 256. Gate terminals of the transistors 253 and 254 are connected to IDATA through the switching transistors 255 and 256.
The transistors 253, 254, 255, and 256 are n-type TFTs. However, the transistors 253, 254, 255, and 256 may be p-type TFTs. The OLED removal technique applied to the pixel circuit 250 can also be applied to pixel circuits having p-type transistors. Transistors 253, 254, 255, and 256 can be fabricated using amorphous silicon, nanocrystalline/microcrystalline silicon, polycrystalline silicon, an organic semiconductor process (e.g., organic TFT), an NMOS/PMOS process, or a CMOS process (e.g., MOSFET).
The transistors 253, 254, 256 and the storage capacitor 252 are connected at node a 10. The transistors 253, 254, the OLED 251 and the storage capacitor 252 are connected at node B10.
In conventional current programming, SEL goes high and a programming current (IP) is applied to IDATA. Considering that the width of the mirroring transistor 253 is "m" times larger than the width of the mirroring transistor 254, the current flowing through the OLED 251 in the programming cycle is (m + 1) IP. When "m" is large to obtain a significant speed increase, unnecessary light emission may become non-negligible.
Instead, according to the OLED removal technique, VDD is brought to a low voltage. This ensures that the OLED 251 is removed from the programming path, as shown in fig. 24.
In a programming cycle, SEL is at a high level and VDD becomes a reference voltage (Vref), where the OLED 251 is reverse biased. Therefore, the OLED 251 is removed from the current path during the programming cycle.
During a programming cycle, the pixel circuit 250 may be programmed with a proportional current by IDATA without experiencing unnecessary light emission.
In a programming cycle, pixel circuit 250 may be programmed with current using one of the techniques described above. The voltage of the IDATA line is read back to extract the threshold voltage of mirror transistor 253, which is the same as the threshold voltage of drive transistor 254.
In addition, during a programming cycle, pixel circuit 250 may be programmed with a voltage via the IDATA line using one of the techniques described above. The current of the IDATA line is read back to extract the same threshold voltage of mirror transistor 253 as the threshold voltage of drive transistor 254.
The reference voltage Vref is selected so that the voltage at the node B10 becomes smaller than the ON voltage of the OLED 251. Therefore, the OLED 251 is turned off and unnecessary light emission is zero. The voltage of the IDATA line includes:
V P +V T +ΔVT...(3)
wherein V P Including the drain-source voltage of the driving transistor 254 and the gate-source voltage, V, of the transistor 253 T Is the threshold voltage of the transistor 253 (254), Δ VT is V T Offset/mismatch of.
At the end of the programming cycle, VDD returns to its initial value, so the voltage at node B10 returns to the OLED voltage VOLED. In the driving period, SEL is at a low level. Since the switching transistors 255 and 256 are off, the gate terminal voltage of the transistor 254/253 is fixed and stored in the storage capacitor 252. Thus, in the driving period, the pixel current becomes equal to the threshold voltage V T Is irrelevant.
OLED removal techniques can be employed in hybrid drive techniques to extract V T Offset or V T Mismatch. From (3) it can be seen that if the pixel is programmed with current, the only variable parameter in the voltage of the IDATA line is V T Offset/mismatch (Δ V) T ). Therefore, Δ V can be extracted T And can use Δ V T The programming data is calibrated.
FIG. 25 shows one example of a system configuration for performing the OLED removal technique. The display array 260 includes a plurality of pixel circuits, such as the pixel circuit 250 of fig. 26. A display controller and scheduler 262 controls and schedules the operation of the display array 260. The driver 264 supplies an operating voltage to the pixel circuit. The driver provides operating voltages to the pixel circuit to remove the OLED from the programming path of the pixel circuit based on instructions/commands from the display controller and scheduler 262, as described above.
The controller and scheduler 262 may include the functionality of the display controller and scheduler 64 of fig. 3, or may include the functionality of the data processing and calibration unit 206 of fig. 16. The system shown in fig. 25 may have these functions, as well as any of the calibration-scheduling described above, the voltage/current extraction described above, or a combination thereof.
FIG. 26 shows the use of different V T The voltage on the IDATA line of (a). Referring to fig. 23-26, the voltage of the idata line includes an offset in the threshold voltage of transistors 253 and 254. The programming current was 1 μ A.
A significant reduction in unwanted luminescence would result in higher resolution. At the same time, separate extraction of circuit aging and light emitting device aging can be performed, which makes it possible to obtain more accurate calibration.
Note that each of the transistors shown in fig. 4-8, 14, 20, 21, 23, and 24 may be replaced with a p-type transistor using the concept of a compensation circuit.
All citations are incorporated herein by reference.
The invention has been described using one or more embodiments. However, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.

Claims (40)

1. A method of real-time calibration of a display array having a plurality of pixel circuits arranged in rows and columns, comprising the steps of:
generating a prioritized list of pixels for prioritizing pixels for calibration based on display and previous calibration data, using the prioritized list to select one or more (n) pixels, the selected one or more pixels being programmed with a current higher than a threshold current for calibration;
selecting n pixels in a selected column of the display array from a linked list;
programming pixels in the selected column, comprising:
monitoring pixel currents of the n pixels and obtaining calibration data;
updating a compensation memory based on the calibration data for calibration;
the next programmed priority list is sorted.
2. The method of claim 1, wherein the step of programming comprises:
a calibration mode is initiated for n pixels in the selected column and a normal operating mode is initiated for other pixels in the selected column.
3. The method of claim 1, wherein the step of ordering the list comprises:
the n pixels just calibrated are moved to the end of the priority list.
4. The method of claim 1, wherein the monitoring step comprises:
detecting a current, an
The current is compared to a desired current.
5. The method of claim 2, wherein the step of programming comprises:
the pixels of the normal operation mode are programmed based on a combination of the calibration data and the programming data stored in the compensation memory.
6. A system for real-time calibration of a display array having a plurality of pixel circuits arranged in rows and columns, each pixel circuit having a light emitting device and a drive transistor, the system comprising:
a calibration scheduler for controlling programming and calibration of the display array, comprising:
a priority list for listing one or more pixels for calibration based on the display data;
means for initiating a calibration mode for one or more pixels in a selected column selected from the priority list during a programming cycle, and a normal operating mode for the remaining pixels in the selected column during a programming cycle;
a monitor for monitoring pixel current of pixels in a calibration mode on the selected column;
a generator for generating calibration data based on the monitoring result;
a memory for storing calibration data; and
a regulator for regulating programming data applied to the display array based on the calibration data when programming pixels of a normal operation mode.
7. The system of claim 6, wherein the monitor includes a sensor for sensing current in the form of voltage, a converter for changing the programmed data in the form of current to desired voltage data, and a comparator for comparing the sensed voltage to the desired voltage data.
8. The system of claim 7, wherein the pixel circuit is a current programmed pixel circuit.
9. The system of claim 7, wherein the display array is coupled to a voltage data driver, and an input of the voltage data driver is changed based on calibration data stored in the memory.
10. The system of claim 7, wherein the monitor includes a switch for selectively connecting the selected column to the sensor.
11. The system of claim 9, wherein the monitor comprises a switch for selectively connecting a pixel in a calibration mode or a pixel in a normal operation mode to the voltage data driver.
12. A system for a display array having pixel circuits programmed through data lines, the system comprising:
a data source for providing programming data into the pixel circuit;
a current controlled voltage source associated with the voltage source for converting a current on the data line to a voltage associated with the current to extract a time varying parameter of the pixel circuit.
13. The system of claim 12, further comprising:
a controller for determining a time-varying parameter of the pixel circuit based on the extracted voltage.
14. The system of claim 12, further comprising a current conveyor for extracting a current of the data line, the current conveyor including X, Y and Z terminals, the voltage source applying a programming voltage to the Y terminal, the X terminal being connected to the data line, the X terminal having the same voltage as the Y terminal due to feedback, the current of the X terminal being copied to the Z terminal, the Z terminal being connected to the voltage source for current control.
15. The system of claim 12, wherein the pixel circuit is a current mirror based pixel circuit.
16. The system of claim 15, wherein the current mirror based pixel circuit comprises:
first and second mirror transistors having gate terminals, first terminals and second terminals, respectively;
first and second switching transistors having gate terminals, first terminals, and second terminals, respectively;
a storage capacitor; and
a light-emitting device is provided with a light-emitting element,
wherein a first terminal of the first mirror transistor is connected to the data line through the first switching transistor and to the storage capacitor through the second switching transistor, a second terminal of the first mirror transistor is connected to the storage capacitor and to the light emitting device, gate terminals of the first and second mirror transistors are connected to the storage capacitor and to the data line through the first and second switching transistors, a first terminal of the second mirror transistor is connected to a voltage supply line, and a second terminal of the second mirror transistor is connected to the storage capacitor and to the light emitting device.
17. A system for a display array comprising a plurality of pixel circuits, each pixel circuit comprising a drive transistor, at least one switching transistor, a storage capacitor, and a light emitting device, the system comprising:
a monitor for monitoring a current or a voltage of the pixel circuit;
a data processing unit for controlling operation of the display array, the data processing unit extracting information about aging of the pixel circuit based on the monitored current or voltage and determining a state of the pixel circuit;
a driver controlled by the data processing unit, the driver for providing programming and calibration data for the pixel circuit based on the state of the pixel circuit.
18. The system of claim 17, wherein the data processing unit estimates the intermediate threshold voltage V of the drive transistor based on the state of the pixel circuit TM 。
19. As claimed in claim18, wherein the data processing unit uses the previously extracted threshold voltage V T (i, j), or the threshold voltage V of the previous extraction T (i, j) and resolution V of said driver S To estimate the intermediate threshold voltage V TM 。
20. The system of claim 19, wherein V is based T (i, j) and program data to determine a program voltage for programming.
21. The system of claim 19, wherein V is based TM And a bias voltage to determine a calibration voltage for calibration.
22. The system of claim 17, wherein the monitor senses current flowing through a monitor line, the monitor line being connected to the pixel circuit.
23. The system of claim 22, wherein the switching transistor comprises first and second switching transistors,
each of the driving transistor, the first switching transistor and the second switching transistor including a gate terminal, a first terminal and a second terminal,
a gate terminal of the driving transistor is connected to a signal line through the first switching transistor and is connected to the storage capacitor, a first terminal of the driving transistor is connected to the light emitting device and is connected to the monitor line through the second switching transistor,
gate terminals of the first and second switching transistors are connected to the first and second selection lines, respectively.
24. The system of claim 23, wherein the first and second select lines are a common select line.
25. The system of claim 17, wherein the system sequentially performs, for each row of the display array, a fetch operation for fetching a threshold voltage of the driving transistor, a programming operation for programming the pixel circuit, and a driving operation for driving the pixel circuit.
26. The system of claim 17, wherein the system performs a fetch operation once for each row of the display array to fetch the threshold voltage of the drive transistor in the time of one frame.
27. A method of driving a display array comprising a plurality of pixel circuits, each pixel circuit comprising a drive transistor, at least one switching transistor, a storage capacitor and a light emitting device, the method comprising the steps of:
applying a current or voltage to the pixel circuit;
monitoring a current or voltage flowing through the pixel circuit;
extracting information about the aging of the pixel circuit based on the monitored current or voltage and determining a state of the pixel circuit;
providing an operating voltage to the pixel circuit, including determining programming and calibration data for the pixel circuit based on a state of the pixel circuit.
28. The method of claim 27, wherein the extracting step comprises the steps of:
estimating an intermediate threshold voltage V of the drive transistor based on the state of the pixel circuit TM 。
29. A method of driving a display array comprising a plurality of pixel circuits, each pixel circuit comprising a drive transistor, at least one switching transistor, a storage capacitor and a light emitting device, the method comprising the steps of:
applying a current or voltage to the light emitting device;
monitoring a current or voltage flowing through the light emitting device;
predicting a voltage shift of the light emitting device based on the monitored current or voltage and determining a state of the pixel circuit; and
providing a bias to the light emitting device associated with a voltage shift of the light emitting device.
30. The method of claim 29, wherein the light emitting device is an organic light emitting diode.
31. The method of claim 30, wherein the predicting step comprises the steps of:
estimating an intermediate voltage of the organic light emitting diode.
32. A system for driving a display array comprising a plurality of pixel circuits, each pixel circuit comprising a drive transistor, at least one switching transistor, a storage capacitor, and a light emitting device, the system comprising:
a monitor for monitoring a current or a voltage of the pixel circuit;
a data processing unit for predicting a voltage shift of the light emitting device based on the monitored current or voltage and determining a state of the pixel circuit; and
a circuit that provides a bias to the light emitting device that is associated with a voltage shift of the light emitting device.
33. The system of claim 32, wherein the light emitting device is an organic light emitting diode.
34. The system of claim 33, wherein the data processing unit estimates an intermediate voltage of the organic light emitting diode.
35. A system for a display array, the display array comprising a plurality of pixel circuits, each pixel circuit comprising a drive transistor, at least one switching transistor, a storage capacitor, and a light emitting device in a programming path for programming the pixel circuit, the system comprising:
a controller for controlling operation of the display array;
a driver for supplying an operating voltage to the pixel circuit based on control of the controller; and
a driver for providing an operating voltage to the pixel circuit during a programming cycle to cause the light emitting device to be removed from the programming path.
36. The display array system of claim 35, wherein the driver provides an operating voltage to the pixel circuit during a programming cycle to reverse bias the light emitting device.
37. The system of any one of claims 1-36, wherein the display array is an AMOLED array.
38. The system of claim 6, 32 or 35, wherein the light emitting device is an organic light emitting diode.
39. A system as claimed in claim 6, 32 or 35, wherein at least one transistor is a thin film transistor.
40. The system of claim 1, 6, 32 or 35, wherein the transistors of the pixel circuits are n-type or p-type TFTs.
CN2005800480205A 2004-12-15 2005-12-15 Method and system for programming, calibrating and driving a light emitting device display Active CN101116129B (en)

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CA2,490,860 2004-12-15
CA002490860A CA2490860A1 (en) 2004-12-15 2004-12-15 Real-time calibration scheduling method and algorithm for amoled displays
CA 2503237 CA2503237A1 (en) 2005-04-08 2005-04-08 Step calibration driving method and circuit for amoled displays
CA2,503,237 2005-04-08
CA2,509,201 2005-06-08
CA002509201A CA2509201A1 (en) 2005-06-08 2005-06-08 Oled luminance degradation compensation technique
CA002521986A CA2521986A1 (en) 2005-10-17 2005-10-17 A driving and aging extraction scheme for current programmed amoled pixel circuit with no unwanted emission
CA2,521,986 2005-10-17
PCT/CA2005/001897 WO2006063448A1 (en) 2004-12-15 2005-12-15 Method and system for programming, calibrating and driving a light emitting device display

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